AI Compute Cards Wiki Editorial

On September 22, 2026, multiple media outlets reported that DeepSeek's CEO explicitly stated the company is betting heavily on Huawei chips, expects to receive a new batch of Huawei chips for large-model training, and stressed that "this choice must succeed." Following earlier reports that "DeepSeek planned to procure 160,000 Ascend 950DT units for inference," this is the most significant alignment signal yet in the domestic compute ecosystem — an upgrade from inference procurement to a training bet.

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1. The Signal Chain: Four Steps to a "Training Bet"​

Piecing together the public information from the past six months, the DeepSeek–Ascend collaboration shows a clear escalation path:

Time	Signal	Nature
Mid-2026	DeepSeek V4 completes ecosystem migration from CUDA to CANN	Software adaptation
August 2026	Report: DeepSeek plans to procure 160,000 Ascend 950DT units for inference deployment	Inference procurement intent
2026-09-17	HC2026: 960DT ready three quarters ahead of schedule, 950DT ramping in Q4	Supply delivery
2026-09-22	DeepSeek CEO: betting on Huawei chips for LLM training, "must succeed"	Training bet

The key change is the workload tier: inference deployment means "cutting costs with off-the-shelf compute," while a training bet means "staking the existence of next-generation models on domestic chips" — training clusters demand an order of magnitude more in stability, interconnect efficiency, and software-stack maturity.

2. Huawei's Ability to Deliver​

DeepSeek's willingness to commit rests on a series of verifiable progress points on Huawei's supply side (all official figures):

• One generation per year, delivered: the 950PR is in mass production, the 950DT ramps in 2026 Q4, and the 960DT moved three quarters earlier than its original 2027 Q4 plan to ready in 2027 Q1 / launch in Q2 — the roadmap's credibility validated twice in a row;
• Deployment scale: Ascend supernodes have been commercially deployed at scale in over 1,000 sets, covering internet, finance, healthcare, and manufacturing;
• Ecosystem maturity: CANN has entered routine open-source operation, with external developers exceeding 61% for the first time and 5,200 monthly active developers; there are over 40 Ascend-native training models, making it the only domestic technology route supporting pretraining;
• Training evidence chain: China Telecom's Xing 4.0-29B-A4B agentic MoE model, open-sourced in September, was announced as trained end-to-end on Ascend (company claim) — "Ascend can train large models" is no longer just Huawei's self-attestation.

See the Ascend 950DT and Ascend 960 spec pages for details; for supernode analysis, see Ascend 960 Official Launch.

3. Why DeepSeek?​

DeepSeek's choice has strong structural drivers:

1. Supply certainty: under export-control constraints, NVIDIA's flagship supply to China keeps tightening; domestic compute is the only plannable large-scale training supply;
2. Cost structure: DeepSeek has always been known for extreme engineering efficiency (the V3 training cost set the industry benchmark), and domestic compute plus supernode system efficiency fits its approach;
3. Betting on ecosystem dividends: CANN open-sourcing plus deep binding with leading model vendors means model vendors can participate in shaping the toolchain's direction — something impossible within CUDA's closed system;
4. Self-fulfilling demonstration effect: a leading lab's public commitment pulls back on Huawei's production scheduling and upstream HBM and system investment, making "must succeed" a rational commitment rather than a slogan.

4. Risks and Open Questions​

Viewed coolly, this route still has three items that need time to verify:

• Actual training scale: the quantity, model type (950DT or 960DT), and delivery schedule of the new batch of chips are all undisclosed;
• MFU methodology: the MFU / latency gains Huawei cites all come from Markov-lab simulations, with no independent third-party measurements yet; the real effective compute of a training cluster depends on long-term data from large-scale production environments;
• Per-card generation gap: the 960DT's 4 PFLOPS (FP4) versus Rubin R200's 50 PFLOPS (FP4) — the per-card gap objectively exists, and training efficiency depends on whether supernode scale and software optimization can compensate; that is precisely the decisive battleground of "system-level competition."

5. Summary​

• DeepSeek confirms betting on Huawei chips for training large models — the first training-grade commitment from a leading lab in domestic compute;
• Signal chain: CUDA→CANN migration → 160,000-unit 950DT inference procurement rumor → 960 ready ahead of schedule → training bet;
• Supporting factors: one-generation-per-year delivery, 1,000+ supernode sets, and 61% external developers in the CANN open-source ecosystem;
• What to watch: actual arrival of the new chips and training-cluster scale, third-party MFU data, and training-compute disclosure in DeepSeek's next release.

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Further Reading​

• Ascend 960 spec page / Ascend 950DT spec page (this site)
• Ascend 960 Official Launch: FP4 Compute Doubled, World's First NPO Supernode
• Domestic Top Three in H2 2026: Localization Rate Breaks 40%, Heading Toward 60%
• Alibaba Zhenwu V900 Unveiled at Apsara Conference

References​

• Toutiao Tech Morning Report: DeepSeek confirms betting on Huawei chips for large-model training (2026-09-22)
• HUAWEI CONNECT 2026 official announcements (2026-09-17)
• Earlier report: DeepSeek plans to procure 160,000 Ascend 950DT units (2026-08)

This article is compiled from public reports and vendors' official statements. Details such as chip quantities and training-cluster scale are subject to subsequent disclosures from DeepSeek and Huawei.

Beyond the official Ascend 960 unveiling and the Zhenwu V900 launch, late September also delivered three ecosystem signals that headline coverage easily drowned out, yet whose structural significance rivals flagship chips: a carrier open-sourcing a model trained on Ascend, an OEM delivering a hundred-chip-class domestic inference system, and a cloud-compute chip startup closing a new funding round. This article breaks down each one.

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1. China Telecom Open-Sources Xing4.0: Carrier-Grade Endorsement for End-to-End Ascend Training​

On September 23 (as reported), China Telecom open-sourced Xing4.0-29B-A4B — an agentic mixture-of-experts (MoE) model that the company says was trained end-to-end on Huawei Ascend accelerators.

Why it matters:

• Third-party proof that "it can train": until now, evidence that "Ascend can train large models" came mainly from Huawei itself (40+ natively trained models); a carrier running training with its own data, engineering teams, and clusters — and open-sourcing it — is the first scaled training case outside the Huawei ecosystem;
• Agentic positioning: the 29B-A4B (29B total / 4B active) MoE form factor targets agent workloads directly — aligned with the open-source cadence of DeepSeek and Qwen, rather than a small experimental model;
• Open-source spillover: publishing model weights plus the training recipe means Ascend training engineering know-how can be reused by other institutions — the standard playbook for ecosystem diffusion.

Combined with Huawei's disclosure that "CANN has entered routine open-source operations, with external developers at 61%", the Ascend ecosystem is shifting from "vendor-led" to "community-operated".

2. Inspur MetaBrain SD200 Ultra: Measured Throughput Claims for a 128-Chip Domestic Inference System​

Inspur launched the MetaBrain SD200 Ultra inference system around the same time:

Metric	Value (company figures)
Domestic AI chips	128 chips (vendor did not disclose specific models)
Model served	Kimi K3
Token throughput	2.8T tokens (system throughput figure under that methodology)
Latency	5.85 ms

Three readings:

• Hundred-chip-class system integration: 128 chips cooperating across a heterogeneous setup to run very large MoE inference is a test of interconnect topology, scheduling, and fault tolerance — OEMs are now demonstrably capable of assembling domestic chips into large systems;
• Aimed at top open-source models: targeting Kimi K3 (already live on AWS Bedrock) as the benchmark workload shows the acceptance standard for domestic inference systems is "runs today's most popular models", not a self-referential demo;
• Mind the methodology: the 2.8T token throughput and 5.85ms latency are both vendor claims; the tested model version, concurrency, and batch size were not disclosed, so procurement evaluations should re-test under real workloads.

3. EVAS Closes RMB 2 Billion B+ Round: The Cloud Compute Chip Race Still Attracts Capital​

EVAS (Yixing Intelligence) completed a B+ round of RMB 2 billion, at a post-money valuation near RMB 15 billion, with Oriza Capital following on; earlier in the first half of the year it had closed a RMB 1.5 billion Series B and brought in China Mobile as a strategic investor. The company focuses on next-generation cloud compute chips.

In 2026, when the flagship chip lineup (Ascend / Cambricon / Moore Threads / Hygon / Zhenwu) looks settled, a cloud compute chip newcomer still raising RMB 2 billion suggests:

• Primary-market conviction in the "second tier of domestic compute": with top vendors' capacity booked into 2027, overflow demand gives newcomers a window;
• The role of carrier strategic investment: China Mobile is both a buyer and an investor — the demand side of domestic compute is using capital to lock in the supply side;
• Differentiated room remains for cloud inference DSA routes (see the ecosystem positioning of routes like Tsingmicro and Houmo).

4. Assembling the Week's Signals: The Loop Is Taking Shape​

Put the three signals together with this month's flagship launches, and every segment of the domestic compute loop now has players filling the gaps:

Segment	This Month's Evidence
Flagship chips	Ascend 960 early official unveiling (9-17), Zhenwu V900 launch (9-22)
Training validation	China Telecom's Xing4.0 end-to-end trained on Ascend and open-sourced, DeepSeek betting on Ascend training
Inference systems	Inspur SD200 Ultra running Kimi K3 on 128 chips
Software ecosystem	CANN routine open-sourcing, external developers at 61%
Capital supply	EVAS B+ round of RMB 2 billion (post-money near RMB 15 billion)
Demand side	DeepSeek's alignment, Kimi K3 live on overseas cloud platforms

Independent players are investing across all four segments — "chips, systems, models, capital" — the biggest difference from the "isolated breakthroughs" of 2024-2025.

5. Takeaways​

• China Telecom Xing4.0-29B: the first open-source model end-to-end trained on Ascend outside the Huawei ecosystem;
• Inspur SD200 Ultra: a 128-chip domestic inference system at 2.8T token throughput / 5.85ms (company figures, pending re-testing);
• EVAS RMB 2 billion B+ round: the cloud compute chip second tier is still getting real money;
• What to watch: Xing4.0's training cluster scale and MFU, third-party re-tests of the SD200 Ultra, and EVAS's tape-out cadence.

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Further Reading​

• Ascend 960 Spec Page / Ascend 910C Spec Page (this site)
• DeepSeek Confirms Bet on Huawei Chips for Large-Model Training
• Domestic Top Three in 2026 H2: Localization Rate Breaks 40% and Marches Toward 60%

References​

• The GPU Daily (2026-09-24): China Telecom open-sources Xing4.0-29B; Inspur MetaBrain SD200 Ultra
• Toutiao (2026-09-21): EVAS completes RMB 2 billion B+ round, post-money valuation near RMB 15 billion
• CSDN AI Daily (2026-09-21): Huawei CANN enters routine open-source operations, OceanStor M900 launched

This article is compiled from public reports. Xing4.0 training details and SD200 Ultra performance figures are company statements; testing conditions are subject to subsequent disclosures.

Just five days after Huawei officially announced the Ascend 960 at HUAWEI CONNECT on September 17, Alibaba unveiled its new unified training-and-inference AI chip, Zhenwu V900, at the Apsara Conference in Hangzhou on September 22 — which Alibaba calls "the most powerful Chinese self-developed AI chip in terms of compute performance to date." This article is compiled from Alibaba's official announcements and reports from Sina Tech, C114, Huanqiu.com, and other sources.

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1. Single Chip: 3x M890, 216GB + 1200GB/s​

Metric	Zhenwu V900 (this launch)	Zhenwu M890 (previous generation)
Performance	3x Zhenwu M890 (official figure; absolute value undisclosed)	FP16 600 TFLOPS (as catalogued on this site)
Memory	216 GB	144 GB (HBM3)
Chip-to-chip interconnect	1200 GB/s	—
Precision	Native FP8 / FP4 (including high-precision training)	—
Positioning	Unified training and inference (trillion-parameter-scale training + low-precision inference)	Unified training and inference
Mass production	2027 Q1, scaled deployment in Alibaba Cloud data centers	Already deployed at scale

Three takeaways:

• Memory crosses into the 200GB+ tier: 216GB puts it in the same capacity class as the Ascend 960DT (288GB self-developed HBM) and NVIDIA Rubin (288GB HBM4), leveling the capacity threshold for long-context and very large MoE models;
• 1200GB/s chip-to-chip interconnect: laying the foundation for the supernode's "memory-semantics interconnect" — the chip-level prerequisite that pairs with ICN Switch;
• Precision coverage across all scenarios: officially described as "high-precision training, low-precision and ultra-low-precision inference across all scenarios," with native FP8/FP4 support aligned with the common spec of 2026's new cards.

The absolute single-chip compute figure has not been officially disclosed; this site records it using the official relative figure of "3x M890." See the Zhenwu M890 spec page for M890 details.

2. System Level: ICN Switch + Panjiu Supernode, a 500,000-Card Single Cluster​

V900's real selling point is not the single chip but system-level collaboration:

• ICN Switch self-developed interconnect chip: once connected, the supernode gains native memory semantics and unified memory addressing, with a thousand cards interconnected at full bandwidth — over a thousand V900s can "work together like a single super chip";
• Panjiu supernode server: integrates V900 (compute) + ICN Switch (interconnect) + Panmai intelligent NIC (network) + Zhenyue SSD controller (storage), a fully self-developed compute-storage-network stack;
• 500,000-card single cluster: combined with Alibaba Cloud's next-generation intelligent computing center network architecture, a single cluster can scale up to 500,000 cards.

This mirrors Huawei's "11 key chips" approach: the unit of competition has shifted from the single chip to whole-system delivery capability — Zhenwu handles compute, Yitian handles general-purpose computing, Panmai handles networking, Zhenyue handles storage, and ICN Switch handles interconnect.

3. Business and Roadmap​

• The Zhenwu family has served over 650+ enterprise customers (as of June 2026), spanning autonomous driving, finance, large models, embodied AI, energy, and manufacturing;
• Supernodes based on the M890 are already deployed at scale, running models with over 2 trillion parameters such as Qwen3.8 and Kimi K3; Alibaba Cloud will add new serving nodes in Q4 to expand supernode supply;
• Roadmap: V900 enters mass production and sales in 2027 Q1; Zhenwu J900 is planned for release in 2027 Q3;
• CPU synergy: Yitian 720 / 730 arrive in 2027 (the 730 is the first to adopt T-Head's fully self-developed CPU microarchitecture, with single-core SPECint2017/GHz up to 1.4x that of Yitian 710); the 2029 Yitian 750 will interconnect directly with Zhenwu AI chips via the ICN bus;
• Alibaba Group CEO Eddie Wu said T-Head's AI chip annual shipment volume will increase substantially.

4. Competitive Coordinates: Two Swords in One Week​

Viewing the two mid-September launches side by side, the landscape of "system-level competition" among domestic AI chips is now clear:

Dimension	Huawei Ascend 960 (9-17)	Alibaba Zhenwu V900 (9-22)
Launch event	HC2026	Apsara Conference 2026
Per-card memory	288GB (self-developed HBM)	216GB
Memory bandwidth	9.6 TB/s	Undisclosed
Interconnect	LinJu UnifiedBus / NPO optical interconnect	ICN Switch memory-semantics interconnect
Supernode	Ascend 960 supernode (4,096 cards, 8 EFLOPS FP8)	Panjiu supernode (500,000-card single cluster)
Availability	2027 Q2	2027 Q1

Huawei is taking the "supernode + open-source CANN ecosystem" route, while Alibaba is taking the "full cloud stack + open-source model ecosystem" route; both still trail in per-card specs, but what they deliver are procurable, operable ultra-large-scale clusters. The substitution logic against NVIDIA's CUDA ecosystem is shifting from "performance parity" to "supply certainty + system efficiency."

5. Summary​

• V900: 3x M890, 216GB, 1200GB/s chip-to-chip interconnect, native FP8/FP4, mass production in 2027 Q1;
• System: ICN Switch with thousand-card full bandwidth, Panjiu supernode with a fully self-developed compute-storage-network stack, 500,000-card single cluster;
• Cadence: J900 in 2027 Q3, Yitian 730 in 2027, Yitian 750 in 2029 — T-Head's first three-year generational roadmap;
• What to watch: actual mass production and Alibaba Cloud deployment scale in 2027 Q1, disclosure of V900's absolute compute, and the possibility of external supply of ICN Switch.

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Further Reading​

• Zhenwu M890 spec page (this site)
• Ascend 960 Official Launch: FP4 Compute Doubled, World's First NPO Supernode
• Domestic Top Three in H2 2026: Localization Rate Breaks 40%, Heading Toward 60%

References​

• Huanqiu.com: T-Head launches new unified training-and-inference AI chip Zhenwu V900 (2026-09-22)
• Sina Tech / TechWeb: Alibaba T-Head launches new AI chip Zhenwu V900, mass production in the first quarter of 2027
• C114: Alibaba launches new AI chip Zhenwu V900, mass production in 2027 Q1

This article is compiled from Alibaba's official announcements and public reports. The absolute single-chip compute of V900 has not been officially disclosed; supernode and cluster scale figures are official claims, subject to actual future delivery.

This article is based on official announcements from the 2026 JD Global Technology Explorer Conference (September 9) and public market information; order values and revenue forecasts are brokerage/media estimates, not company announcements.

On September 9, at the 2026 JD Global Technology Explorer Conference, JD Cloud announced a milestone decision: partnering with Moore Threads to build a 100,000-card full-function GPU cluster, creating hyperscale domestic intelligent computing infrastructure.

Two keywords in this sentence deserve amplification: "full-function GPU" and "100,000-card-class core cluster." The former means it must run not just inference but the front lines of large model training, inference, and embodied AI; the latter means a domestic GPU has, for the first time, been placed at the core of a top AI cloud provider's compute base — not a pilot, not an adaptation, not an all-in-one appliance, but 100,000 cards.

1. Partnership Details: From 10,000 to 100,000 Cards — How Big Is the Order?​

• Prior foundation: JD Cloud has already built a domestic 10,000-card cluster with Moore Threads and other partners; this move is a magnitude leap from 10,000 to 100,000 cards
• Order scale: According to market and brokerage information, GPU modules are supplied exclusively by Moore Threads, with a total order value of about RMB 20-30 billion; revenue can be recognized as early as next year according to delivery cadence. Some brokerages have raised Moore Threads' revenue expectation for next year to RMB 15-20 billion (this estimate is not a company announcement; refer to official disclosures)
• Partnership depth: Full-stack coordination from chips and cloud platform to model training, supporting the iteration of JD's JoyAI model family and forming a closed loop of "data, training, simulation, deployment"
• Openness: Compute is open to all industries, focused on large model training, inference, and embodied AI

Moore Threads founder Zhang Jianzhong was direct on stage: "The Scaling Law still holds — 100,000-card clusters are an inevitable trend." JD Cloud President Cao Peng positioned domestic compute as a core pillar of JD's physical AI strategy.

2. Why Moore Threads? Three Calculations Behind the Procurement Logic​

Tech companies buy cards with no sentiment involved. JD's choice of Moore Threads comes down to three calculations that all add up:

1. The stability calculation: Moore Threads has commercially deployed thousand-card and 10,000-card large clusters under a single network, and has achieved breakthroughs in core training scenarios such as foundation models, embodied brains, and world models — the engineering validation of a 10,000-card cluster is the prerequisite for 100,000 cards; this is not a cold start.

2. The integration calculation: Full-function GPUs can plug into existing IT systems and cloud platform scheduling, and the MUSA software stack's adaptation to large model frameworks has already passed training-grade workloads.

3. The ROI calculation: This is the most critical shift. Buyers of domestic GPUs used to be mostly "policy-friendly" projects; JD writing a 100,000-card cluster into its capital expenditure means the product's return on investment can now stand up to investor scrutiny — the buyer structure shifting from "daring to use" to "rushing to use" is the hallmark of commercial maturity for domestic GPUs.

3. S6000: Next-Gen Chip Taped Out and Back, with a Dual-Supply Safeguard​

According to market information, Moore Threads' next-generation chip, the S6000, has successfully come back from the fab and been distributed to vendors for testing, with ample FAB and memory supply guarantees. Note that the S6000 has not been officially released and its specifications are not public; this article makes no speculation. The on-sale flagship MTT S5000 has on-site data of 400 TFLOPS FP16 and 80GB of memory (the 1.6TB/s bandwidth is HBM-class).

Regarding HBM supply constraints, Moore Threads' response strategy is reportedly "next-generation product iteration + multi-source supply chain safeguards" — until domestic HBM capacity ramp-up is complete, this is the same problem every domestic GPU vendor must solve.

4. "100,000 Cards" Is Not One Company's Game: The Domestic GPU Cluster Landscape​

It is worth widening the view — 100,000 cards is now a collective goal for domestic compute:

Player	100,000-Card Move	Compute Base
JD Cloud	Announced co-built 100,000-card cluster on September 9	Moore Threads full-function GPU
Sugon 8000	Released at WAIC in July, completed in Zhengzhou; a fully domestic 100,000-card AI compute cluster	Hygon DCU (of the Shensuan BW1000 family)
Huawei	Atlas 950 SuperPoD super node (8,192 cards); 100,000-card super node in 2027	Ascend 950/960

Two chip routes (full-function GPU vs DCU vs NPU) and two paths (commercial cloud vs national supercomputing) point to the same validation question: can domestic compute reliably run real training workloads at 100,000-card scale. It is worth emphasizing that there is currently no public third-party benchmark comparison for the Moore Threads x JD cluster, and no completion timetable — going from "usable" to "running well" at 100,000 cards still requires engineering validation.

5. The Capital Markets Perspective​

Moore Threads listed on the STAR Market in December 2025: an IPO price of RMB 114.28, closing at RMB 600.5 on the first day; 2025 revenue of RMB 1.505 billion (up 243.37% year over year), with a net loss of about RMB 1.001 billion. If the brokerage-raised revenue expectation of RMB 15-20 billion materializes, 2027 will be the key inflection point from "high-growth loss-making" to "profitable at scale" — which would also become the first complete answer sheet for the domestic GPU business model.

Summary​

From debuting with DeepSeek all-in-one appliances in 2025 to entering a 100,000-card core cluster in 2026, domestic GPUs completed the cognitive leap from "usable" to "commercially viable at scale" in under two years. The value of JD Cloud's order lies not in its amount but in its significance as a sample: when top internet buyers begin procuring domestic GPUs on ROI logic, substitution is no longer a policy narrative but a commercial fact.

(Order values, revenue forecasts, and supply chain status come from public market information and brokerage research estimates; refer to company announcements; chip specification data is available in the on-site full comparison table.)

2026 年 9 月 17 日，华为全联接大会（HC2026），华为常务董事、ICT 基础设施业务总裁汪涛正式发布昇腾 960。与 8 月数字中国峰会上的"路线图预告"不同，这次是完整的规格官宣——而且提前三个季度就绪。本文基于华为官网新闻稿及多方报道整理，逐项拆解 960 的规格、超节点与路线图含义。

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1. 昇腾 960：双版本，训练先行​

昇腾 960 分为两个版本，节奏错开一个季度：

指标	昇腾 960DT（训练版）	昇腾 960PR（推理版）
FP8 算力	2 PFLOPS（较 950 翻倍）	待披露
FP4 算力	4 PFLOPS	待披露
显存	288GB（自研 HBM）	待披露
显存带宽	9.6 TB/s	待披露
配套超节点	Atlas 860（风冷）	Atlas 960（液冷）
就绪 / 上市	2027 Q1 / 2027 Q2	2027 Q3

三个读数：

• 提前三个季度就绪：960DT 原计划 2027 年 Q4，现在 2027 Q1 就绪、Q2 上市——与 950DT"提前上线华为云"一脉相承，路线图可信度在持续兑现；
• 精度口径与英伟达对齐：FP8 / FP4 主口径（辅以自研 HiF8 / HiFP8），FP4 已是 2026 新卡的通用口径；
• 288GB 自研 HBM + 9.6TB/s：显存容量与带宽同步翻倍，对训练长上下文大模型是实打实的容量红利。

单卡规格详见昇腾 960 规格页；上一代昇腾 950DT 规格页。

2. 昇腾 960 超节点：全球首个 NPO 超节点​

这是本场发布真正的"重器"——昇腾 960 超节点是全球第一个采用 NPO（近封装光学）的超节点：

指标	昇腾 960 超节点
单节点规模	4096 卡
系统算力	8 EFLOPS FP8 / 16 EFLOPS FP4
HBM 总容量	1 PB
互联 RTT	低至 2μs
可用度	99.8%

NPO 意味着什么：传统光模块挂在交换机面板上，信号要先出封装再转电—光；NPO 把光引擎挪到交换芯片封装近旁，大幅缩短 SerDes 距离、降低功耗与时延。华为的具体数字：

• 5500 个自研 Hi-ONE 光引擎（业界首个量产 NPO，单引擎 7.2T）；
• 替代 4.8 万颗 800G 光模块；
• 降低功耗 550kW 以上，同时支撑 2μs 级互联时延。

对比 8 月数字中国峰会的口径（Atlas 960 单超节点 15488 卡），官方最新口径为单超节点 4096 卡（1 个超集群可由多超节点组成）——以华为官网最新新闻稿为准。

⚠️ 华为还给出了"MFU 提升 2.75 倍""推理时延降低 70%"等收益数据，均出自华为马尔科夫实验室仿真，尚无独立第三方实测，阅读时注意口径。

3. 一年一代：970（2028）→ 980（2029）​

华为首次把"一年一代"从愿景变成官宣承诺：

年份	产品	状态
2026	昇腾 950 系列	950PR 已量产，950DT Q4 放量
2027	昇腾 960	本次官宣，提前就绪
2028	昇腾 970	HC2026 确认
2029	昇腾 980	HC2026 确认

支撑这一节奏的是华为提出的"韬定律"：算力规格每代翻倍，访存带宽、访存容量、互联带宽同步大幅提升。

生态侧的同场数据也值得记录：CANN 外部开发者占比首次超过 61%、月活开发者 5200 人；910C 超节点部署已超 1000 套。

4. 竞争坐标：单卡有代差，系统级对打​

把 960DT 放到 2027 年的棋盘上看：

• 对 NVIDIA Rubin（R200：288GB HBM4 / 50 PFLOPS FP4）：单卡 FP4 算力约为 R200 的 8%（4 vs 50 PFLOPS），单卡代差客观存在；但 4096 卡超节点 + NPO 互联是系统级竞争——用"可交付的超大集群"对打单卡性能；
• 对采购方：960 的价值主张是"在国产量产约束内拿到最大可用集群"。DeepSeek 拟采购 16 万颗 950DT 跑推理的订单已经证明：当供给与生态到位，头部实验室愿意主动选国产；
• 对国产链条：950→960 的显存翻倍直接拉动国产 HBM 迭代，这是整条链的胜负手。

5. 小结​

• 960DT：FP8 2P / FP4 4P、288GB HBM、9.6TB/s，2027 Q2 上市，提前三个季度；
• 960 超节点：全球首个 NPO 超节点，4096 卡 / 8 EFLOPS FP8 / 1PB HBM / RTT 2μs；
• 路线图：一年一代官宣至 2029，950、960 均提前兑现，规划可信度显著上升；
• 看什么：2027 Q2 实际交付节奏、国产 HBM 产能、CANN 生态的第三方模型覆盖度。

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相关阅读​

• 昇腾 960 规格页（本站，含双版本与超节点完整参数）
• 国产三强 2026 H2：国产化率突破 40% 向 60% 迈进（已按 960 官宣更新）
• 2026 H2 AI 芯片路线图重大更新（已按 960 官宣更新）
• 昇腾 950 超节点 Q4 上市，中兴、新华三、曙光全线跟进

参考资料​

• 华为官网：发布全球首个采用 NPO 的超节点（昇腾 960 超节点）（2026-09-17）
• 电子工程专辑：国产 AI 芯片新突破！华为昇腾 960 芯片将提前发布
• 环球网：华为全联接大会 2026 主题演讲报道

本文基于华为官网新闻稿与公开报道整理。MFU、时延等收益数据为华为实验室仿真口径；2028 / 2029 产品仅为路线图官宣，规格以未来发布为准。

On September 16, MLCommons released the MLPerf Inference v6.1 Closed Division results, and NVIDIA's Vera Rubin NVL72 completed its benchmark debut. The same day, CoreWeave announced that a multi-rack Vera Rubin cluster was live on its cloud — a "rent the new hardware on launch day" cadence that is compressing the cycle from next-generation compute announcement to billable output down to a quarter.

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1. Debut Results: 3.7x and 2.5x​

NVIDIA, via preview submissions (entries 6.1-0106 / 6.1-0074), provided an apples-to-apples comparison of its two flagship generations:

Benchmark Model	Vera Rubin NVL72 vs GB300 NVL72	Software Stack
Qwen3-VL-235B-A22B (235B multimodal MoE)	Throughput up to 3.7x (across offline / server / interactive scenarios)	vLLM + NVIDIA Dynamo
DeepSeek-R1-671B (671B inference model)	Throughput up to 2.5x	TensorRT-LLM

The three technologies behind these numbers:

• NVFP4 precision: compresses the memory footprint of model weights, attention tensors, and the KV Cache, enabling significantly larger effective batch sizes;
• Disaggregated serving: prefill (compute-intensive) and decode (bandwidth-intensive) are split across separate GPU pools, each independently optimized;
• Expert parallelism: MoE expert layers route across chips in a distributed fashion, paired with sixth-generation NVLink / NVLink Switch (NVIDIA claims 10x the packet rate of commodity Ethernet at 3x lower latency).

2. Same-Session Highlights: Scaling Efficiency and the Software Dividend​

• GB300 four racks, 288 chips, 99% scaling efficiency: in the DeepSeek-R1 offline scenario, scaling from a single rack of 72 chips to 4 racks of 288 chips shows almost no loss (entries 6.1-0073 / 6.1-0074) — the first time rack-scale interconnect scaling efficiency has been validated at the 288-chip level;
• The software dividend is still being paid out: on the same GB300 hardware, v6.1 software optimizations deliver up to 1.6x Qwen3-VL gains over v6.0; NVIDIA also reported post-submission gains for GPT-OSS-120B and DLRMv3 (not verified by MLCommons);
• 19 partners submitted, 8 of them using multi-node Blackwell NVL72 configurations (ASUS, Azure, Cisco, CoreWeave, Crusoe, Dell, Fujitsu, HPE, Lambda, Nebius, OCI, Supermicro, and others); Nebius also submitted Vera Rubin preview results.

3. CoreWeave Online the Same Day: Rentable at Launch​

On the same day the MLPerf results were published, CoreWeave announced that its multi-rack Vera Rubin NVL72 cluster was live on its cloud:

• Spectrum-X networking links hundreds of Rubin GPUs into a single scale-out cluster, with each GPU paired with 2 ConnectX-9 SuperNICs (1.6Tb/s scale-out bandwidth);
• The AI object store LOTA cuts read latency by 8x;
• On the operations side: Valvey software-defined liquid cooling (NVIDIA spec: 45°C liquid inlet), the Racky rack control layer, and Rack LifeCycle Controller manage an entire NVL72 rack as a single programmable entity;
• Back in July, CoreWeave's own testing put Vera Rubin at 10x tokens/s/MW versus GB200 NVL72 on DeepSeek R1 (company figures, not MLCommons-verified).

4. The Competitive Picture​

• AMD + Crusoe: set MLPerf's all-time high aggregate throughput of 5.75M tokens/s on 512 chips (AMD had the broadest submission coverage this round);
• SemiAnalysis AgentX preview: Vera Rubin up to 30x over GB300 on agentic workloads (preview figures); the MLPerf Endpoints benchmark is forthcoming and will bring agentic inference into standardized measurement;
• Pending validation: Vera Rubin results are preview submissions awaiting independent reproduction; no quantified quality metrics were given for NVFP4's "virtually lossless" claim; per-token cost and power-consumption scaling comparisons have not been published. Matching submissions from Google TPU v7 and AMD MI455X UALoE72 are expected within 2026.

On-site spec comparisons: Rubin R200 (288GB / 22TB/s), B300 Ultra (GB300-class core).

5. Takeaways​

• Vera Rubin NVL72 debut: Qwen3-VL 3.7x, DeepSeek-R1 2.5x over GB300 NVL72 (preview figures);
• GB300 across four racks of 288 chips at 99% scaling efficiency — rack-scale interconnects have entered the usable range;
• CoreWeave brought a multi-rack cluster online the same day — the cycle from next-gen compute launch to billable output is now measured in quarters;
• What to watch: independent reproductions and formal (non-preview) submissions, TPU v7 / MI455X comparison results, and measured per-MW token throughput.

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Further Reading​

• Rubin R200 Spec Page / B300 Ultra Spec Page (this site)
• NVIDIA Vera Rubin Mass Production and Liquid Cooling Deployment
• Hot Chips 2026 Full Recap: Rubin, MI455X, Crescent Island on the Same Stage

References​

• NVIDIA Blog: Vera Rubin NVL72 Makes Its First Appearance in MLPerf Inference v6.1 (2026-09-16)
• MLCommons: MLPerf Inference v6.1 Closed Division results (entries 6.1-0073 / 6.1-0074 / 6.1-0106)
• CoreWeave Investor Relations: multi-rack Vera Rubin NVL72 availability announcement (2026-09-16)
• AMD Blogs: MLPerf Inference v6.1 submission results

This article is compiled from public MLCommons results and vendor official statements. Vera Rubin results are preview submissions; some gain figures are not MLCommons-verified and are flagged item by item.

本周（2026 年 9 月 1 日–5 日）AI 算力行业的题眼，是两条相反方向的成本重构：海外，英伟达以史上最大并购吞下开发者生态入口，同时给旗舰减配显存——"内存太贵"倒逼硬件从单卡堆料走向系统级互联；国内，DeepSeek 16 万颗昇腾订单把"国产替代"从口号变成头部实验室的资产负债表决策，字节近 300 亿美元融资为算力扩张装上杠杆。

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1. DeepSeek 拟购 16 万颗昇腾 950DT：国产算力的"标志性订单"​

彭博社 9 月 4 日报道，DeepSeek 计划在内蒙古乌兰察布新建的约 1GW 数据中心部署至少 16 万颗华为昇腾 950DT，主要用于推理而非训练。按每颗约 11.1 万元的市场价估算，订单总额约 178 亿元人民币（约 25.6 亿美元）——这是迄今已知规模最大的昇腾集群，是半年前深圳首个万卡级集群的 16 倍。

三个关键读数：

• 主动选择，而非被迫替代：DeepSeek 是公认最会"榨干"算力的实验室。创始人梁文锋 7 月曾直言：华为超节点能完成 GB300 的任务、延迟没有明显差别，但约需 4 颗昇腾才抵 1 颗英伟达、技术上落后约两年。选择昇腾跑推理，是在综合成本、供应链安全与本土化后的理性决策——推理对软件生态依赖较浅，正是国产芯片的突破口；
• 瓶颈在供给端：受高端内存（HBM）短缺制约，昇腾 950DT 今年产量仅数十万颗（2026 年全部昇腾 die 计划约 160 万颗），DeepSeek 希望加购更多但产能所限，整单交付或需一年以上——国产 HBM 与先进封装成为整条链的胜负手；
• 过渡性押注：DeepSeek 同时在与中芯国际合作开发自研推理芯片，并于 6 月完成约 500 亿元融资、继续洽谈数十亿美元基建融资。国产算力的终局是多元自主，而非单一依赖。

单颗 950DT：144GB HBM、4.0TB/s 带宽、2.0TB/s 互联，原生支持 FP8/FP4/HiF8，详见昇腾 950DT 规格页。

2. 英伟达 129.3 亿美元收购 Hugging Face：买下"铲子的交易所"​

当地时间 9 月 3 日，英伟达宣布以 129.3 亿美元收购全球最大开源 AI 平台 Hugging Face，超过 2020 年 69 亿美元收购 Mellanox，成为其史上最大并购。交易含约 119 亿美元股权款与最高约 10 亿美元员工留任计划，预计 2027 年上半年完成，待监管批准。

Hugging Face 托管超 300 万个模型、50 万个数据集，服务超 1800 万名开发者。黄仁勋承诺平台继续开放中立运营：不强制绑定英伟达资源、开源属性完整保留。

解读：算力霸主的护城河从"芯片 + 网络 + 软件栈"一路修到了"模型分发 + 开发者生态"——卖铲人开始收购铲子的交易所。平台的"中立性"承诺能否兑现，将成为全球监管与竞争性云厂商持续盯防的焦点；对国内产业而言，模型托管、权重分发这类"轻资产 AI 基础设施"与芯片一样，正在成为大国科技博弈的卡点。

3. Rubin Ultra 显存减配：内存占 TCO 40% 后的算术题​

SemiAnalysis 最新报告（科创板日报 9 月 3 日转引）显示，英伟达已将旗舰 Rubin Ultra 的 HBM 配置从 HBM4E 12-Hi（384GB 档）下调至 HBM4 8-Hi（192GB），三星正配合开发 8 层产品。

• 动因：HBM/DRAM 涨价后，内存已占整机 TCO 约 40%；减配后 HBM 成本降超 50%，即便计入 2026 年 HBM 涨价预期，内存占总资本开支比例也将从 40% 压至 28%；
• 钱去了哪：转向 Scale-up 纵向扩展网络——以 NVL576 NPO 方案测算，光模块取代机架间互连后，Scale-up 网络占机架总支出比例从 4% 升至 12%；
• 连锁反应：TrendForce 显示英伟达自 2026 Q3 起并行评估 HBM4E 8-Hi / 12-Hi / HBM4 8-Hi 多套方案，部分云厂商也在考虑下调下一代自研 ASIC 的 HBM 容量。

连定价权最强的英伟达都给旗舰"减配求量"，等于官宣：当前 AI 硬件最紧的约束是内存（美光高管称新增内存供应 2028 年前难有实质放量），单卡堆料的军备竞赛告一段落，硬件价值重心正迁移到光互联、CPO、高速交换与 PTFE 背板。华泰测算 2027 年存储供需缺口将从约 -7% 收窄至 -3%——上行周期未逆转，但从"普涨"走向"结构性紧缺"。

详见本站已同步更新的 Rubin Ultra 规格页与HBM4 量产竞速分析。

4. 推理 ASIC 军备提速：谷歌"一年两款"，Jalapeño 规格落地​

• 谷歌 TPU 迭代周期从两年一代压缩至"每年两款"（华创证券 9 月 4 日研报）：第八代已拆分为训练（8t）与推理（8i）双架构，8i 把内存/算力配比拉到 8t 的 1.65 倍，专为推理放量设计；
• OpenAI Jalapeño 规格披露：6 堆栈 HBM4 共 216GB、带宽 15.4TB/s、700W，围绕投机解码设计；OpenAI 称在 DeepSeek R1 负载下 tokens/kW 达 GB300 的 1.7 倍；RTL 冻结到流片 9 个月，首批硅片后约 10 周承载 ChatGPT 流量。详见规格页（本站已更新）；
• workload-specific 时代开场：训练、推理、推荐各自长出专用芯片，上游 HBM/封装/光互联的供应节奏必须跟上"半年一代"。

5. 国内动态：字节 296 亿美元加杠杆，摩尔线程 Token 超节点投产​

• 字节跳动获约 296 亿美元融资安排（彭博 9 月 3 日），较最初约 200 亿美元目标大幅上调，用于数据中心与 AI 基建；另据产业报道正洽谈在内蒙古新增 5-6GW 算力产能——中国 AI 公司迄今最大规模基建融资之一，算力正被当作可融资、可证券化的重资产经营；
• 摩尔线程 × 趋境科技 "Token 超节点"投产（光明网 9 月 4 日）：以 MTT S500 承担 Prefill 与 KV Cache 生成、高带宽 GPU 专注 Decode 的 PD 异构方案，实测平均生成速度超 50 TPS、KV Cache 命中率超 90%、稳定性 99.9%，已承接头部模型厂商官方业务流量——超节点竞争维度从"单卡参数"转向"单位 Token 生产成本"；
• OpenAI 发布 GPT-6 Astra（9 月 4 日）：超 10 万颗 GPU 在 Stargate 集群完成训练，推理放量与超大规模集群仍是全球算力叙事主线；
• SemiAnalysis 基准：AMD MI355X 新提交在 AgentX 基准低交互区间tokens/$ TCO 击败 B300——vLLM + LMCache 软件栈的贡献首次被独立机构量化认可。

6. 市场：中美算力资产一涨一调​

美东 9 月 4 日，美国 8 月非农仅增 8.9 万人（预期 16 万），10 年期美债收益率回落至 3.78%，成长股走强：科技板块 XLK 周涨 4.2%，英伟达周涨 8.7% 收于 230.36 美元。A股 9 月 4 日反向回调：AI 算力芯片板块 -1.99%、服务器 -2.51%、超节点 -2.86%，浪潮信息跌停、寒武纪 -2.54%——基本面无恶化（博通、戴尔、中际旭创订单与财报持续验证景气），更多是交易层面获利兑现。

下周起三连催化密集：CIOE 光博会（9/9-11）→ 华为全联接大会（9/17-19）→ 云栖大会（9/22-24）。国产超节点从"发布会 PPT"到"批量交付"的成色，将迎来集中检验。

本周一句话​

内存太贵改变了所有人的算法：英伟达给旗舰减配显存、把钱投给互联；DeepSeek 用 16 万颗昇腾买推理确定性；谷歌把 TPU 迭代压到半年一代。2026 年 Q4 起，"每兆瓦/每美元 token 数"将取代"单卡 PFLOPS"，成为算力采购的第一指标。

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相关链接​

• 华为昇腾 950DT 规格页
• NVIDIA Rubin Ultra 规格页
• OpenAI Jalapeño 规格页
• NVIDIA Rubin 规格页

参考资料​

• 彭博社（转引）：DeepSeek 拟部署 16 万颗昇腾 950DT（2026-09-04）
• cnBeta/今日头条：DeepSeek 据称采购 16 万颗华为昇腾 950DT 芯片（2026-09-05）
• 科创板日报：SemiAnalysis 拆解 Rubin Ultra 减配（2026-09-03）
• Natural News/DailyAI：Nvidia To Acquire Hugging Face For $12.9B（2026-09-05）
• 光明网：摩尔线程 × 趋境科技 PD 异构推理方案投产（2026-09-04）
• AGI Hunt：AI News Daily 2026-09-05

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本文基于彭博社、科创板日报、SemiAnalysis、TrendForce、华创证券研报及光明网等公开报道整理。订单金额与市场数据为媒体/机构预估口径，实际以相关公司正式披露为准。

This article is based on official announcements from AWS and NVIDIA (September 5, 2026) and public statements by executives of both companies.

On September 5, 2026, AWS and NVIDIA announced an expanded strategic partnership: on top of the "1 million additional GPUs starting in 2026" plan announced at GTC 2026, they will deploy 2 million more NVIDIA GPUs, covering three architecture generations — Blackwell Ultra, Rubin, and Rubin Ultra — with a deployment window of 2027-2028. Demand growth exceeding all previous forecasts was the direct reason both companies cited.

This is no longer a simple "chip purchase" — it is a full-stack partnership spanning GPUs, CPUs, interconnect, memory, open-source models, and software. We break the key information into six points.

1. Composition and Timeline of the 2 Million GPUs​

• Scale: 2 million GPUs (added on top of the original 1 million GPU plan, tripling the total committed scale)
• Architectures: Blackwell Ultra, Rubin, Rubin Ultra
• Timeline: 2027-2028, deployed across AWS global infrastructure (including newly built AI factories)
• Context: Amazon's 2026 capital expenditure guidance has been raised from $200 billion to $220 billion, and CEO Andy Jassy has explicitly said it is still not enough to meet AI compute demand

For reference, the figures Jensen Huang gave at GTC 2026 put cumulative orders and demand for the Blackwell and Rubin platforms through 2027 on track to reach $1 trillion (at GTC 2025, the estimate for 2026 was roughly $500 billion). AWS's add-on order is one of the heaviest puzzle pieces in that big picture.

2. Vera CPU Comes to AWS for the First Time​

This is the most structurally significant change in the partnership: NVIDIA Vera CPU infrastructure will enter AWS.

The Vera CPU is the general-purpose processor in the Vera Rubin platform designed for agentic AI, positioned to efficiently turn AI resources into "completed agent tasks." As agentic workloads rise, CPU-side pressure on task orchestration, memory management, and data scheduling rises in step — pure GPU expansion is no longer enough, and AWS needs a matching high-performance CPU layer. This also aligns with AWS's strategy of "offering the broadest compute choices, from in-house chips (Graviton/Trainium) to partner chips": Vera does not replace Trainium, but fills in the CPU compute layer alongside the accelerated infrastructure.

3. NVLink Fusion × NVHBM: Open Architecture Goes Deeper​

At re:Invent 2025, AWS announced that its next-generation Trainium chip would support NVIDIA NVLink Fusion high-speed interconnect. This time, both companies took the partnership one step further:

• Amazon Annapurna Labs will support NVIDIA's new custom high-bandwidth memory NVHBM (developed in collaboration with memory vendors)
• Trainium thereby gains a faster, more power-efficient memory option
• Trainium and GPUs can work together within the same rack-scale architecture, sharing scale-up interconnect

For the chip industry, this is a signal worth watching closely: NVLink Fusion + NVHBM means NVIDIA's interconnect and memory technologies have started "supplying" competing ASICs. The boundary between the in-house ASIC camp (Trainium, TPU, MTIA) and the NVIDIA GPU camp is shifting from "either/or" to "hybrid deployment."

4. 100,000 GPUs: The U.S. Government Sovereign AI Factory​

A dedicated public-sector business is carved out of the partnership: AWS and NVIDIA will build AI factories for the U.S. government, deploying 100,000 GPUs on secure AWS infrastructure to host federal and national security workloads (Impact Level 6 and above), supporting the development of advanced AI models within strict regulatory frameworks.

Sovereign AI turning from a slogan into concrete numbers is a defining feature of this cycle — government customers are becoming first-class buyers of AI compute.

5. Software and Physical AI Deepen in Parallel​

Beyond hardware, the software layer of the partnership is also strengthening:

• NVIDIA Nemotron open-source models continue to arrive on Amazon Bedrock and SageMaker
• Amazon EMR data processing and OpenSearch vector indexing are accelerated by cuDF / cuVS
• Amazon Robotics officially adopts the NVIDIA physical AI platform (Jetson, Omniverse, Isaac) for warehouse automation and next-generation robotics

Physical AI (robotics, embodied intelligence) is becoming a new growth pole in cloud providers' compute narratives — the same trend as JD.com, Tesla, and others writing embodied intelligence into their compute procurement logic.

6. Implications for Compute Buyers​

Observation	Implication
Demand "beat all forecasts"	Supply tightness is not a short-term phenomenon; the 2027-2028 compute window must be locked in now
Mixed procurement across three architectures	During the Rubin/Rubin Ultra production ramp-up, Blackwell Ultra remains the delivery mainstay; procurement needs cross-generation planning
CPU layer revalued	agentic AI pushes the bottleneck from GPU to CPU orchestration and memory bandwidth; do not focus only on accelerator cards when selecting
Sovereign AI lands	Government-scale orders enter the market, further tightening the allocatable supply of high-end GPUs

For decision-makers weighing build versus rent, every massive add-on order from cloud giants reprices the future rental curve. If you are evaluating GPU purchase or rental options, we recommend running a quantitative calculation with the TCO Calculator: enter chip price, power draw, utilization, and rental rates to compare 3-year total cost of ownership.

Summary​

2 million GPUs, Vera CPU in the cloud, NVHBM opening up, 100,000 sovereign compute GPUs — this round of expansion between AWS and NVIDIA pushes the "AI factory" race into the full-stack era. Compute scarcity will most likely only tighten before 2027; whether you are buying, renting, or betting on domestic alternatives, locking in supply and cost curves early is the surest move right now.

(The data in this article comes from official AWS/NVIDIA announcements and public statements by executives of both companies; architecture performance figures are as released by the vendors.)

7 月 Advancing AI 2026 大会上的承诺正在兑现：AMD Helios 机架已进入全面量产，2026 年 Q3 末启动客户出货、Q4 放量。管理层透露客户拉货进度"领先于初始预测"——对英伟达而言，第一次有一个对手在"机架级系统"这个自己定义的战场上，拿到了真金白银的订单。

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1. Helios：AMD 第一台真正意义上的"机架级计算机"​

指标	Helios（72 × MI455X）	对比 Vera Rubin NVL72
显存	31TB HBM4 池化（单卡 432GB）	Rubin 单卡 288GB（+50%）
显存带宽	1.4PB/s（单卡 19.6TB/s）	22TB/s（单卡）
FP4 推理	2.9 ExaFLOPS	3.6 EFLOPS
FP8 训练	1.4 ExaFLOPS	1.2 EFLOPS
Scale-up 互联	260TB/s（UALink/UALoE）	130TB/s（NVLink6，约 2 倍差距）
机架售价	约 525 万美元	—
出货节奏	2026 Q3 末起，Q4 放量	2026 年 9 月批量出货

MI455X 采用 CDNA 5 架构：8 个 TSMC N2 制程加速 die + N3P 互联 die，256 个工作组处理器、192MB 全局 L2，12 层堆叠 HBM4 让它成为首款显存超过 400GB 的 AMD GPU。同系列还有面向主权 AI 与 HPC 的 MI430X（推理特化）、面向企业的 MI440X（8 GPU + 1 EPYC Venice 一体化服务器）——三条产品线覆盖从云到边缘的完整光谱，规格详见本站 MI455X、MI440X、MI430X 卡片。

配套的 EPYC Venice（Zen 6） 是业界首款 2nm x86 服务器 CPU，最高 256 核，性能较上代 Turin 提升约 1.7 倍，承担 Helios 机架内编排、数据搬运与 CPU 密集型负载。

2. 12GW 订单簿：四大锚定客户全部落地​

AMD 在 AI 加速器市场最大的变化，是从"卖芯片"变成"签产能"：

客户	协议规模	关键条款	交付节奏
OpenAI	6GW 跨代际	首批 1GW MI450；附最高 1.6 亿股认股权证（与部署进度及股价挂钩）	2026 H2 起部署，2027 加速
Meta	最高 6GW / 五年	最高 600 亿美元；Meta 获收购 AMD 最多 10% 股份的选择权	2026 H2 部署 Helios
甲骨文	5 万颗 MI450	从 2026 Q3 起部署	2026 Q3 起
Anthropic	最高 2GW	AMD 投资最高 50 亿美元；双方用 Claude 优化 ROCm	首批 1GW 2027 H1 上线

分析师对 OpenAI 协议中 GPU 部分的收入估计约 800 亿美元；Piper Sandler 估计 Meta 协议五年内可为 AMD 带来约 1000 亿美元收入。合作模式也已升级——不再是简单的采购合同，而是"定制开发 + 资本投入 + 长期联合优化"的深度绑定：Anthropic 甚至披露 Claude 曾在一个周末内自主完成 AMD AI 服务器的配置。

值得关注的是，Cerebras 也宣布与 AMD 达成合作，从 Cerebras 数据中心内部开始部署 AMD 服务器——推理芯片初创公司与 GPU 巨头的"竞合"正在成为新常态。

3. 最大的变量不是英伟达，是封装产能​

AMD 2027 年数据中心营收翻倍的目标，瓶颈不在需求，在供给侧：

• CoWoS-L 产能：汇丰分析指出，要达成目标，CoWoS-L 产能需求需比基础情景高出 12%–35%；AMD 选择将设备托管至 SPIL、PTI 等二线封装厂（一线供应商 2027 年前几乎没有产能富余），低良率风险不可忽视；
• HBM 供应：MI455X 单卡 432GB HBM4 对存储供应提出极高要求，2027 年 HBM4 供给依然紧张（详见本站 HBM4 竞速分析）；
• 资本开支：AMD Q2 资本支出已跃升至 8.08 亿美元，专门用于向外包封测厂托管 CoWoS 设备以保障 Venice CPU 量产。

摩根大通提醒：这是 AMD 首次机架级产品量产，执行风险在 2027 财年内仍然显著，毛利率稀释效应将随出货量逐步显现。

4. ROCm 与 CUDA：真正的前线​

AMD 高管提出"随着 PyTorch、vLLM 等高层抽象框架普及，底层 CUDA 或 ROCm 的差异对开发者日益模糊"。这个判断有部分道理——但 CUDA 的护城河不止是编程接口，还包括数学库、通信库、调试工具和二十年积累的硬件级优化能力。处理自定义算子、混合精度、稀疏计算和千卡集群故障排查时，底层软件栈依然决定成败。

AMD 的聪明之处在于借力打力：让 Anthropic 用 Claude 优化 ROCm——用 AI 优化 AI 芯片的软件栈，这可能是缩小生态差距最快的一条路。

5. 对采购方的启示​

• 第二供应源已是现实选项：2027 年规划推理集群时，MI455X/Helios 值得进入正式评估名单，其 432GB 显存对大参数模型推理的容量优势是实打实的；
• 锁定交付窗口：Helios 为 OCP 开放机架参考设计，最终交付由 OEM/ODM 完成——下单时确认液冷、电源与系统集成责任方，避免"芯片到了机柜没到"；
• 关注 Q4 爬坡数据：年底前 Helios 是否真在 OpenAI 基础设施中大规模上线，是检验 AMD 机架级交付能力的第一个硬指标。

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相关链接​

• AMD MI455X 规格页
• AMD MI440X 规格页
• AMD MI430X 规格页
• NVIDIA Rubin 规格页

参考资料​

• Tech Insider：AMD Advancing AI 2026 — Helios Hits $5.25M, 12GW Booked
• Lumien AI：AMD Helios AI Servers Enter Full Production, OpenAI Commits to Deployment
• 超级金属市场新闻网：AMD AI 战略受限于产能瓶颈（2026-09）
• 大数跨境：全球首款 2nm GPU 炸场，OpenAI、Meta、微软站台

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本文基于 AMD Advancing AI 2026 大会披露与后续供应链报道整理。订单规模、收入预测均为分析师口径，实际以 AMD 财报为准。

芯片追不上，系统来补。这是国产算力过去一年最清晰的战略共识。2026 年下半年，国产超节点正式从"概念发布"进入"产品密集发布、联合适配和商业部署"阶段：华为 Atlas 950 SuperPoD 真机已亮相并计划 Q4 上市，中兴、新华三、中科曙光、壁仞、沐曦等一众厂商相继入局。

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1. 华为 Atlas 950：业界最大 1024 卡超节点，Q4 上市​

继 7 月 WAIC 2026 真机首秀后，华为昇腾 950 超节点的商用脚步持续加快。核心规格：

指标	Atlas 950 SuperPoD
互联规模	最大 1024 × 昇腾 950DT（灵衢高速互联）
AI 算力	1 EFLOPS FP8/mxFP8/HiF8、2 EFLOPS FP4
全局内存	256TB 统一编址，片上内存最大 1024 × 96GB @ 4.0TB/s
互联带宽	单柜最大 64 × 1.68 TB/s（双向），3μs 超低 RTT
形态	满配 128 计算柜 + 32 互联柜，占地约 1000㎡，8192 颗 950DT
供电散热	全液冷，100kW 供电，380V AC/336V DC/240V DC
上市时间	2026 年第四季度

在 WAIC 展台之外，两个数字更能说明商业化进度：昇腾 384 超节点已商用落地 750 多套，规模应用于互联网、运营商、金融、教育、医疗等行业，并且是国内唯一训练出 SOTA 模型的超节点；更远期规划中，Atlas 950 SuperCluster（超 50 万颗昇腾芯片）同样定于 2026 Q4，Atlas 960 SuperPoD（15488 卡）与 Atlas 960 SuperCluster（超 100 万卡）将于 2027 Q4 接力。

华为的路线图背后是"Tau Scaling Law"——在 EUV 光刻机受限的前提下，通过系统级扩展突破单芯片物理极限，并计划到 2031 年将晶体管密度推升至 1.4nm 级工艺水平。

2. 超节点赛道全面开花：三条技术路线​

WAIC 之后，国产超节点形成了三类清晰的技术路线：

第一类：华为全栈自研。 同时掌握昇腾芯片、灵衢互联、Atlas 硬件、CANN 软件栈和 MindSpore 框架。CANN 已全面开源：社区上线 67 个项目、开源代码超 1244 万行、月活开发者突破 3500 人；昇腾开发者总数超 400 万。

第二类：中兴、新华三的兼容路线。 中兴发布 OEX 超节点新品，依托协议标准化与接口统一，全面兼容多元 GPU 生态；新华三 UniPoD S80000 系列可从 32 卡扩展至 1024 卡、最大支持 16384 卡互联，将 Scale-up/Scale-out 网络、液冷、供电、管理和故障恢复整合进同一套架构。

第三类：国产 GPU 联合创新。 中兴联合曦智、壁仞、沐曦、燧原、天数智芯等，基于 OEX+dOCS 架构打造国产高性能 Matrix 超节点；壁仞计划发布 BR20x 系列 GPU，基于自研 BLink 2.0 互联协议实现单超节点 1024 卡 Scale-up；沐曦推出"曦景"S 系列超节点。

在更大的 Scale-out 层面，中科曙光"曙光 8000（登峰）"全国产十万卡 AI 超集群已落成并接入国家超算互联网——它不是单体超节点，而是由大量计算节点、超节点和网络存储组成的超集群，检验的是国产算力的大规模调度、应用适配和工程交付能力。

3. 为什么"超节点"成了国产算力的主战场​

根本原因在于衡量标准变了：国产算力的评价体系，正从"比较单颗芯片的峰值性能"转为"一整套系统能够调动多少有效算力"。华为副董事长徐直军对此直言：单芯片上英伟达仍领先且短期难以追赶，但在超节点和集群层面，华为有信心。

这一转向的产业逻辑：

• 出口管制下的现实选择：单卡制程受限 → 用高速互联把更多 NPU 组织成一台"大计算机"；
• 需求侧真实拉动：万亿参数 MoE 模型的训练与推理，天然需要大规模低时延互联，超节点恰是对症下药；
• 生态护城河前移：CANN 开源 + MindSpore 兼容 PyTorch，把 CUDA 生态的竞争从"算子覆盖"层面拉回到"开发者规模"层面。

东兴证券指出，全球超节点赛道已聚集微软、Meta、亚马逊、三大运营商、阿里、字节、腾讯、百度、曙光、中兴、浪潮、新华三、海光、沐曦等数十家厂商——格局未定，但英伟达一家独大的局面正在被谷歌 TPU、AMD Helios、华为 Atlas 三股力量同时挑战。

4. 三道关卡：从"造出来"到"卖得动"​

业内人士普遍认为，国产超节点距离真正成熟还有三道坎：

1. 单芯片性能与单柜算力密度：受制程限制，单卡性能差距仍存，现阶段靠多柜互联和规模扩展另辟蹊径；
2. 规模扩展效率：超节点扩展到一定规模后性能提升边际递减，通信复杂度、能耗和容错成本持续上升；
3. 可验证的商业价值：下一阶段的比拼是有效算力利用率、单位 token 成本、模型适配广度与客户复购意愿。

一句话总结：2026 年是"中国超节点元年"，2027 年见真章——届时 Atlas 950 与 Vera Rubin NVL 系列将在全球两个平行市场各自接受规模化交付的检验。

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相关链接​

• 华为昇腾 950 规格页
• 华为昇腾 950DT 规格页
• 华为昇腾 910C 规格页

参考资料​

• 21 世纪经济报道：WAIC 上的算力重器——华为昇腾 950 超节点真机现身（2026-07-17）
• 昇腾社区：Atlas 950 SuperPoD 液冷超节点产品规格
• RCR Wireless：Huawei unveils new offering for AI infra at Shanghai event
• Seoul Economic Daily：Huawei Unveils Atlas 950 SuperPoD

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本文基于 WAIC 2026 现场报道、昇腾社区官方规格与公开研报整理。超节点性能数据均为厂商公布口径，独立第三方评测结果尚待观察。