In the first half of 2026, the AI chip industry underwent a historic turning point — the center of gravity shifted from the "training race" to "inference efficiency," domestic chip market share broke 40% for the first time, NVIDIA built higher barriers with Blackwell Ultra, and the inference-specific chip track bloomed in diversity.

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I. Compute Doubles Again: NVIDIA Blackwell Ultra Launch (June 1)​

On June 1, 2026, NVIDIA CEO Jensen Huang unveiled the new-generation AI chip Blackwell Ultra at Computex 2026 (Taipei), setting a new starting line for the AI infrastructure race over the next two years.

Key Specs​

Metric	Blackwell Ultra	B200	Improvement
FP8 compute	20 petaFLOPS	~10 petaFLOPS	100%
Architecture	Blackwell Ultra	Blackwell	Upgrade
Expected delivery	2027 Q1	2026 Q1	—
Positioning	Hyperscale training + inference	Training + inference	Flagship

Industry Significance​

1. Direct impact of doubled compute: 20 petaFLOPS FP8 means training time for hundred-billion-parameter models drops sharply; trillion-parameter model training moves from "scientific experiment" to "engineering routine"
2. System-level balance: Blackwell Ultra is not just a chip but a system-level engineering breakthrough across NVLink, HBM, cooling, and power delivery
3. Roadmap certainty: The Q1 2027 delivery timeline lets cloud vendors and AI labs plan infrastructure budgets 18 months ahead

Challenges​

• Energy crisis: Doubled performance comes with sharply higher power; datacenter power and cooling design face extreme challenges
• Accessibility: Top-tier compute goes first to top cloud vendors; how smaller developers and research institutes reach compute at reasonable cost via cloud services
• Software stack adaptation: New hardware needs matching CUDA versions and framework support; software ecosystem maturity becomes the key bottleneck for compute conversion

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II. Domestic AI Chips: The Tipping Point from "Usable" to "Good"​

On June 16, 2026, Xinchuang World published "2026 China Domestic AI Chip Vendor Capability Quadrant", clearly outlining the overall domestic landscape.

2.1 Capability Quadrant Ranking​

Quadrant	Representative Vendors
Leader quadrant	Huawei Ascend, Hygon, Cambricon, Alibaba T-Head, Moore Threads
Visionary quadrant	Baidu Kunlunxin, Biren, Enflame, Iluvatar, HardyVision
Contender quadrant	TSINGMICRO, Black Sesame, SemiDrive, Lisuan, Houmo
Challenger quadrant	Denglin, Zhicun, VeriSilicon, Rockchip, Intellifusion

2.2 Huawei Ascend: The Anchor of Domestic Compute​

Market Position​

• In 2025, Ascend series shipped 812,000 units, capturing 49% of the domestic AI accelerator card share, firmly No.1 domestically
• Ascend 950PR single-card FP8 compute reaches 1P (PetaFLOPS), FP4 compute reaches 2P
• Inference performance is about 2.87x that of NVIDIA H20, priced at only 72,000-75,000 RMB, a significant price/performance advantage

Full-Stack Advantage​

Huawei's "device-network-cloud-chip" integrated strategy is Ascend's core moat:

• Chip design: Da Vinci 3.0 architecture iterating continuously
• OS: HarmonyOS/Euler OS deeply optimized
• Networking: Euler network protocol stack
• Cloud: Huawei Cloud ModelArts platform seamlessly integrated

Latest Progress​

• On June 5, 2026, Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, completed full-parameter post-training of a 1.6-trillion-parameter DeepSeek V4 Pro model on an Ascend 910C cluster
• This is the first time domestic AI chips completed trillion-parameter-level model training, marking "domestic substitution" moving from inference to training

2.3 Cambricon: The First Profitable Domestic AI Chip Benchmark​

Performance Explosion​

Metric	Full-year 2025	2026 Q1	YoY Growth
Revenue	6.497B RMB	2.885B RMB	+453% / +160%
Net profit	2.059B RMB (first annual profit)	1.013B RMB	— / +185%

Core Product: Siyuan 590​

• In DeepSeek R1 inference scenarios, TPS reaches 942, about 50% higher than H20
• Years of joint optimization with ByteDance; strongest short-term cloud inference deployment capability
• Of 2.885B RMB Q1 2026 revenue, Siyuan 590 contributed over 70%

Potential Risks​

Absent from the 2nd 2026 "Safe and Reliable Evaluation Results Announcement"; the reason is unclear and will affect its domestic government/enterprise market performance.

2.4 TSINGMICRO: The "Third Route" of Reconfigurable Chips​

Technical Route​

TSINGMICRO adopts a reconfigurable dataflow architecture同源 with Groq LPU, finding a balance between GPU generality and ASIC extreme efficiency.

Metric	TSINGMICRO TX81	Traditional GPU	Advantage
Inference cost	Baseline	+100%	Reduced 50%
Energy efficiency	Baseline	Baseline	3x improvement
Architecture	Reconfigurable dataflow	SIMT/SIMD	Better for inference

Deployment Progress​

• Cumulative shipments of reconfigurable chips exceed 30 million units
• Scaled deployment in a dozen-plus thousand-card-scale intelligent computing centers nationwide
• Has begun A-share IPO tutoring; likely to become the "first reconfigurable chip stock"

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III. The Inference Chip Track: Core Signal of the Industry Shift​

On June 4, 2026, TrendForce published a deep report "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten," pointing out that the compute competition center of gravity is shifting from training to inference.

3.1 Why Now?​

Cost Structure Changed​

• Training is a one-time cost: Once a model is trained, marginal cost approaches zero
• Inference is a recurring cost: Every API call, every generated token represents compute consumption and gross-margin pressure
• Per-unit inference cost and energy efficiency directly affect gross margin and scale-expansion capability

Model Compression Tech Matured​

• 1.58-bit quantization and weight pruning let models maintain inference accuracy at extremely low memory footprint
• MoE (Mixture of Experts) architecture activates only a few expert sub-networks per inference via "partial wake-up," greatly reducing actual computation
• The rise of slimmed models provides commercial viability for hard-wired inference chips

3.2 NVIDIA's $20B Bet: Acquiring Groq (December 2025)​

On December 24, 2025, NVIDIA acquired Groq's inference technology license and core team for $20 billion, one of NVIDIA's largest M&A/tech acquisitions ever.

Strategic intent:

1. Fill the inference gap: NVIDIA GPU is unshakable in training, but inference efficiency was never its strongest suit
2. Counter specialized inference chips: Cerebras, Taalas, SambaNova and other startups are eroding the inference market
3. Position for Agentic AI: Agentic AI needs extremely low-latency, high-throughput inference

3.3 Taalas HC1: Proof of Concept for Hard-Wired Inference​

On February 20, 2026, Canadian AI chip startup Taalas launched inference chip Taalas HC1, directly etching Meta's open-source AI model Llama 3.1 8B into the chip.

Key Metrics​

Metric	Taalas HC1	NVIDIA B200 (throughput optimized)	Advantage
Inference rate	16,960 tokens/s/user	Baseline	~4-5x
Cost per million tokens	0.75 cents	3.79 cents	Reduced 80%
Power	~250W	~700W	Reduced 64%
Process	TSMC N6	TSMC 4nm	More mature
HBM	❌ Not used	✅ HBM3e	Lower cost

Technical Principle​

Taalas HC1 uses an aggressive Computing-in-Memory (CIM) implementation:

• Model weights directly固化 in Mask ROM (fully hardware-defined)
• On-chip SRAM handles dynamic data (KV cache and LoRA fine-tuning weights)
• Only 2 mask layers need modification to produce a dedicated chip for another AI model; turning an AI model into a physical chip takes only 2 months

Limitations​

• Lack of flexibility: Hard-wiring cannot cope with rapidly iterating model updates
• Ecosystem barrier: The current cloud market still relies on general-purpose platforms; customers may prefer flexible solutions that upgrade with models
• NRE cost: High one-time engineering cost, requiring sufficient deployment scale to amortize

3.4 Cerebras: The IPO Path of Wafer-Scale Integration​

On May 14, 2026, Cerebras Systems officially listed on NASDAQ, becoming the first wafer-scale AI chip company to go public.

Core Technology: Wafer-Scale Integration (WSI)​

• WSE-3 (third-gen wafer-scale engine): An entire 12-inch wafer as a single chip
• 44GB on-chip SRAM: No external HBM, eliminating the memory bandwidth bottleneck
• 21 PB/s bandwidth: On-chip communication bandwidth, thousands of times that of GPUs
• Partnership with OpenAI: Signed a 3-year, 750MW, $20B+ compute cooperation agreement

IPO Significance​

Cerebras's listing marks the maturation of the inference-specific chip track:

1. Capital markets begin pricing such companies
2. Proves "non-GPU" technical routes have commercial viability
3. Provides valuation references for other inference chip startups (Groq, SambaNova, Taalas, etc.)

3.5 Inference Chip Landscape: Multiple Technical Routes Coexist​

Company	Technical Route	Core Advantage	Representative Product
Taalas	Hard-wired (Mask ROM)	Extreme inference efficiency, low cost	HC1
Cerebras	Wafer-scale integration (WSI)	Ultra-high bandwidth, large-model inference	WSE-3
Groq	SRAM-first architecture	Deterministic latency, high throughput	LPU (acquired by NVIDIA)
d-Matrix	Digital in-memory compute (DIMC)	More flexible than hard-wiring	Corsair
Etched	Hard-wired Transformer	Works for all Transformer models	Sohu
Axelera AI	Digital in-memory compute (D-IMC) + RISC-V	High energy efficiency	Metis AIPU

TrendForce predicts:

• General-purpose GPUs still dominate training and multi-model environments
• But in mature, predictable scenarios, general-purpose GPU profit margins will be compressed
• The industry shifts from general compute monopoly to a dual-track structure of general + specialized coexistence

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IV. Overall Domestic AI Chip Landscape in H1 2026​

4.1 Industry Enters Scale-Up Phase​

Metric	2025	2026 Q1	Trend
Domestic AI accelerator shipments	1.65M units (41% share)	—	Rising
Total China AI accelerator shipments	~4M units	—	—
Hygon revenue growth	—	Doubled	↑
Cambricon revenue growth	—	+160%	↑
Moore Threads revenue growth	—	Doubled	↑

Leading vendors collectively entered the revenue realization channel, moving from "technical validation" to "scale commercialization."

4.2 Three Core Development Trends​

Trend 1: Capitalization Wave Reshapes the Landscape​

• Late 2025 to early 2026: Moore Threads, Iluvatar listed on the STAR Market
• Biren listed on the Hong Kong stock exchange
• Enflame STAR Market IPO accepted
• Kunlunxin, T-Head initiated listing processes
• TSINGMICRO, HardyVision and others advancing IPOs

Capitalization brings dual effects:

• ✅ Positive: Supports R&D and ecosystem building
• ⚠️ Negative: Valuation bubbles and revenue realization pressure

Trend 2: Capacity Becomes the Biggest Constraint Variable​

The contradiction between explosive domestic AI chip demand and limited advanced-process capacity is sharpening:

Vendor	Advanced-process capacity need	Actually obtained
Huawei Ascend	15K wafers/month (7nm-class)	Priority guaranteed
SMIC total capacity	~20K wafers/month (7nm-class)	—
Other vendors	~5K wafers/month combined	Extremely tight

Whether stable wafer capacity can be secured directly determines vendor survival. Cambricon's 75.4% inventory-to-revenue ratio is essentially a lock on capacity.

Trend 3: Competition Shifts from "Usable" to "Good"​

Early competition focused on "can it run the model"; now it's about "runtime efficiency, deployment cost":

Dimension	"Usable" era	"Good" era
Hardware performance	Can it run the model	Runtime efficiency, energy efficiency
Software stack	Basic adaptation	Maturity, framework breadth
Ecosystem	Existence	Developer community activity
Deployment cost	Insensitive	Core competitive factor

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V. H2 2026 Outlook​

5.1 Upcoming Key Events​

Time	Event	Impact
2026 Q3	NVIDIA Rubin architecture details revealed	Next-gen flagship specs unveiled
2026 Q3	Huawei Ascend 950PR/950DT formally launched	New benchmark for domestic inference chips
2026 Q4	AMD MI350X scaled delivery	NVIDIA Blackwell competitor
2026 Q4	Cambricon Siyuan 690 launch (est.)	New-gen training chip
2027 Q1	NVIDIA Blackwell Ultra delivery	New compute benchmark lands

5.2 Key Competitive Factors Over the Next Three Years​

1. Wafer capacity access: Advanced-process capacity is a scarce resource; vendors tied to SMIC and TSMC have inherent advantages
2. Capital operation efficiency: The IPO window is limited; raising enough capital on the market determines R&D sustainability
3. Software ecosystem depth: Hardware performance is only the entry ticket; software stack maturity, framework adaptation breadth, and developer community activity are the core moat

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VI. Conclusion: A Diverse Ecosystem Will Eventually Form​

In H1 2026, the AI chip industry is undergoing a historic transition from "one dominant player" to "pluralistic coexistence."

• NVIDIA builds higher training barriers with Blackwell Ultra while laying out inference efficiency via the Groq acquisition
• Huawei Ascend holds the domestic compute baseline with full-stack capability; 950PR begins to surpass H20 in inference
• Cambricon proves the commercial viability of domestic AI chips by turning profitable first; Siyuan 590 surpasses international rivals in specific scenarios
• Cerebras, Taalas and other inference-specific chip companies opened a "non-GPU" third route
• TSINGMICRO's reconfigurable architecture provides a diversified technical route choice for China's AI chips

Over the next three years, the domestic AI chip endgame will form a pluralistic ecosystem where GPU, ASIC, and reconfigurable computing three technical routes coexist, with cloud and edge developing in coordination. "Domestic substitution" is no longer a slogan, but an industrial reality happening now.

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Data sources:

• Xinchuang World "2026 China Domestic AI Chip Vendor Capability Quadrant" (2026-06-16)
• TrendForce "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten" (2026-06-04)
• RayByte "Compute Doubles! NVIDIA Blackwell Ultra Chip Launched" (2026-06-02)
• Official financial reports and announcements of each company

Related reading:

• Huawei Ascend 910C Specs Deep Dive
• Full Comparison Table

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June 2026 saw multiple milestone events in the AI chip field, marking acceleration of two major trends: "domestic substitution" and "de-NVIDIA-ization."

1. Huawei Ascend 910C Completes 1.6-Trillion-Parameter DeepSeek V4 Pro Training (2026-06-05)​

Event Overview​

June 5, 2026, Shenzhen Hetao College, together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and other teams, relied on an Ascend 910C domestic AI compute cluster to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek V4 Pro large model.

Technical Significance​

Metric	Value
Model parameters	1.6 trillion
Training chip	Ascend 910C cluster
Training type	Full Parameter Post-Training
Significance	First time domestic AI chips complete trillion-parameter-level model training

Industry Impact​

1. Breaks technology blockade: Proves domestic AI chips can train trillion-parameter models
2. Accelerates "farewell to NVIDIA": DeepSeek fully switches to Huawei Ascend, reducing dependence on H100
3. Domestic substitution inflection point: From "inference substitution" to "training substitution"

Related Links​

• Huawei Ascend 910C spec page
• DeepSeek V4 Pro official announcement (pending)

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2. OpenAI Launches First Custom AI Inference Chip Jalapeño (2026-06-24)​

Event Overview​

June 24, 2026, OpenAI and Broadcom jointly launched the first custom AI inference chip Jalapeño, with a design cycle of only 9 months (industry average 18 months), using TSMC 3nm process.

Key Metrics​

Metric	Jalapeño	Comparison (Blackwell)
Process	TSMC 3nm	TSMC 4nm
Architecture	Systolic Array	Blackwell GPU
Design cycle	9 months	~18 months
Inference cost	-50%	Baseline
AI-assisted design	✅ First	❌ No
Deployment	End of 2026	Shipped

Strategic Significance​

1. First AI chip with AI-assisted design: OpenAI used models like GPT-5.3-Codex-Spark to assist architecture exploration
2. Accelerates "de-NVIDIA-ization": Tech giants (Google, Amazon, Microsoft, Meta, OpenAI) collectively develop custom chips
3. Inference cost revolution: For OpenAI processing hundreds of millions of API calls daily, a 50% cost reduction is significant

Related Links​

• OpenAI Jalapeño spec page
• OpenAI Custom Chip Deep Dive

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3. NVIDIA Launches RTX Spark AI PC Superchip at Computex 2026 (2026-06-01)​

Event Overview​

June 1, 2026, NVIDIA CEO Jensen Huang launched the RTX Spark AI PC superchip at Computex 2026 / GTC Taipei, in collaboration with MediaTek, using an Arm CPU + Blackwell GPU unified-memory architecture.

Key Metrics​

Metric	RTX Spark
CPU	Up to 20-core Arm (with MediaTek)
GPU	6,144 CUDA cores (Blackwell)
Unified memory	128GB LPDDR5X (shared CPU+GPU)
Memory bandwidth	300 GB/s
AI compute	~1 PFLOPS (est.)
Model capacity	Can run 120B-parameter models
Context	Up to 1 million tokens
TDP	~100W (est.)
Availability	Fall 2026

Industry Impact​

1. NVIDIA enters PC chip market: Challenges Intel's dominance in personal computers
2. New AI PC standard: Run 120B-parameter models locally, 1M-token context
3. Windows transforms into AI Agent platform: Deep collaboration with Microsoft OpenShell framework

Related Links​

• NVIDIA RTX Spark spec page
• Computex 2026 Chip War Deep Dive (external link)

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4. MIIT Publishes "2026 AI Chip Industry Development White Paper" (2026-06-09)​

Event Overview​

June 9, 2026, China's Ministry of Industry and Information Technology published the "2026 AI Chip Industry Development White Paper," predicting the domestic AI chip market will exceed 200 billion RMB in 2026.

Key Predictions​

Metric	2026 Prediction
Market size	Exceed 200 billion RMB
Domestic chip share	>50% (41% in 2025)
Edge inference chips	Significant progress
Shipment growth	More than double (vs 2025)

Industry Significance​

1. Domestic AI chip capitalization accelerates: Cambricon, Enflame, Moore Threads, etc. accelerate IPOs
2. Edge inference becomes the breakthrough: Easier to achieve domestic substitution than training chips
3. Policy dividend continues: Domestic substitution upgraded from "market behavior" to "national strategy"

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5. ByteDance in Talks to Procure 50K Iluvatar Inference Chips (2026-06-17)​

Event Overview​

June 17, 2026, Reuters reported that ByteDance is in talks with Shanghai AI chip firm Iluvatar to procure at least 50,000 AI chips, mainly for inference tasks.

Deal Details​

Item	Content
Buyer	ByteDance
Supplier	Iluvatar
Chip model	ZhiKai series (inference GPU)
Quantity	At least 50,000
Use	Inference workloads
Training chip	TianTai series

Industry Significance​

1. Domestic GPU top player "adds a member": Iluvatar enters a top internet company's supply chain for the first time
2. ByteDance 2026 capex raised over 200B RMB: Mainly for AI compute and datacenters
3. "Domestic substitution" extends from government/SOEs to private tech giants

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Summary: Three Trends in June 2026 AI Chip Industry​

Trend 1: "Domestic Substitution" Moves from Inference to Training​

• Ascend 910C completes 1.6-trillion-parameter model training → Proves domestic chips have training capability
• DeepSeek fully switches to Ascend → Leading AI companies first to "farewell to NVIDIA"
• ByteDance procures Iluvatar → Private tech giants follow

Trend 2: "De-NVIDIA-ization" from Slogan to Action​

• OpenAI Jalapeño → First custom chip, inference cost -50%
• Google TPU, Amazon Trainium, Microsoft Maia → Continuous iteration
• Meta MTIA, Apple M5 Ultra → Increased investment

Trend 3: AI PC and Edge Inference Become New Battlefield​

• NVIDIA RTX Spark → New AI PC standard, launches Fall 2026
• Edge inference chip localization accelerates → Key mention in MIIT white paper
• "Local trillion-parameter model execution" → New consumer market selling point

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Looking Ahead (2026 H2)​

1. Ascend 950DT full scale-up (2026 Q4) → Huawei's latest-gen training chip
2. NVIDIA Rubin R200 shipment (2026 H2) → Next-gen flagship
3. AMD MI400 Helios rack (2026 H2) → Targets NVIDIA GB200
4. OpenAI Jalapeño deployment (end of 2026) → Gigawatt-scale datacenters
5. Domestic AI chip shipments more than double → CITIC Securities prediction

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References​

• Huawei Ascend 910C Completes DeepSeek V4 Pro Training - Tencent News
• OpenAI Jalapeño Chip Launch - CNBC
• NVIDIA RTX Spark Launch - Tencent News
• MIIT AI Chip White Paper - RayByte
• ByteDance Procures Iluvatar Chips - Sina Finance

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This article is continuously updated. Please provide the latest developments.

On June 24, 2026, OpenAI and Broadcom jointly announced their first in-house AI inference chip, Jalapeño. This ASIC designed specifically for large language model inference went from design to tape-out in just 9 months and cuts inference cost by roughly 50%, marking OpenAI's transformation from a pure model company into a full-stack AI infrastructure provider.

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1. Core conclusions (read this first)​

Dimension	Jalapeño	Current GPU solution	Advantage
Inference cost	-50%	Baseline	✅ Half the cost
Performance per watt	Clearly superior	Most advanced accelerator	✅ Energy-efficiency lead
Design cycle	9 months	~18 months	✅ 2× faster
Positioning	Inference ASIC	Train+inference GPU	Dedicated optimization
Supply	Internal only	Market purchase	⚠️ Not for sale

One-line summary: Jalapeño is a key step in OpenAI's full-stack AI strategy, using in-house silicon to cut inference cost 50% while opening a new paradigm of "AI-assisted design of AI chips."

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2. What is Jalapeño?​

2.1 Basic information​

Item	Detail
Name	Jalapeño (a chili pepper)
Type	Application-specific integrated circuit (ASIC)
Positioning	Large language model inference
Announced	2026-06-24
Taped out	Sep 2025 (est., 9-month rapid tape-out)
Deployment	End of 2026 (gigawatt-scale data centers)
Partners	Broadcom, TSMC, Celestica
Process	TSMC 3nm
Architecture	Systolic Array
HBM	8 stacks (est. HBM3E or HBM4)

2.2 Why "Jalapeño"?​

Jalapeño is a Mexican chili known for "medium heat, strong flavor." OpenAI's naming hints that the chip:

• ✅ Medium heat: not the most aggressive architecture (vs Cerebras WSE), but effective enough
• ✅ Strong flavor: strong presence in inference scenarios (50% cost reduction)
• ✅ Appetizer: just "the first step of a multi-generation roadmap" (Broadcom CEO Hock Tan)

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3. Deep technical analysis​

3.1 9-month rapid tape-out: the new paradigm of AI-assisted chip design​

Normally, designing an ASIC from scratch takes 1.5 to 2 years. Jalapeño went from initial design to manufacturing tape-out in just 9 months.

Key reason: deep software-hardware co-development

Technique	Description
AI-assisted architecture exploration	OpenAI used its own frontier models (GPT-5.3-Codex-Spark) to explore chip architecture design space
AI power simulation	AI models for power simulation and optimization
RL optimization	RL to optimize chip placement and routing
Broadcom silicon implementation	Broadcom provides top-tier ASIC implementation (network, switch chip experience)

OpenAI President Greg Brockman said:

"We use the frontier models that serve our users to optimize the infrastructure that runs the models of the future."

3.2 Architecture optimized for inference​

Unlike general-purpose GPUs, Jalapeño is an ASIC built from scratch around OpenAI's deep understanding of LLM inference workloads:

Architecture feature	Description
Reduce data movement	Core principle is minimizing data movement (the main bottleneck in inference)
Balanced compute-memory-network	Resource allocation optimized for inference, bringing real utilization closer to theoretical peak
High throughput + low latency	Aims to combine the throughput of leading accelerators with the low latency of the fastest dedicated inference systems
Future model support	Supports not only current models (GPT-5, GPT-5.3) but adapts to next-gen inference needs

3.3 Full-stack platform: more than a chip​

Jalapeño is a multi-generation compute platform, not just a chip:

Component	Supplier	Description
Accelerator chip	OpenAI design, TSMC fab	TSMC 3nm, 8-stack HBM
Network switch chip	Broadcom Tomahawk	High-speed interconnect (competes with NVIDIA NVLink)
Board, rack, system	Celestica	Full-rack solution
Software stack	OpenAI	Deep adaptation for GPT, Codex, Agent products

Deployment target: gigawatt-scale data centers

Broadcom CEO Hock Tan said:

"Jalapeño will begin deployment this year in gigawatt-scale data centers with Microsoft and other partners."

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4. Performance and cost analysis​

4.1 Inference cost cut 50%​

Although OpenAI's official release was conservative on Jalapeño's cost savings — only stating its "performance per watt is substantially better than today's state of the art" without a specific percentage — per Bloomberg, Broadcom CEO Hock Tan revealed:

Early internal tests show Jalapeño achieves roughly 50% inference cost savings versus today's mainstream AI GPUs.

Significance for OpenAI:

Item	Current (GPU)	Jalapeño	Savings
Daily API calls	Hundreds of millions	Hundreds of millions	—
Inference cost share	~60-70% of operating cost	~30-35%	-50%
Annual compute spend	Billions of dollars	Hundreds of millions	Saves billions

4.2 Performance per watt clearly better than state of the art​

OpenAI's announcement states:

"Jalapeño engineering samples have successfully run complex reinforcement-learning tasks such as GPT-5.3-Codex-Spark at target frequency and power; early tests show performance per watt substantially better than today's most advanced AI accelerators."

Comparison target: NVIDIA Blackwell (today's most advanced AI accelerator)

Metric	Jalapeño	NVIDIA Blackwell	Note
Performance per watt	Clearly superior	Baseline	OpenAI official statement
Inference latency	On par with fastest dedicated inference systems	Baseline	Target
Throughput	On par with leading accelerators	Baseline	Target
TDP	Not disclosed (est. 400-700W)	700-1000W	Jalapeño possibly lower

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5. Impact on the AI chip market​

5.1 "De-NVIDIA-ification" accelerates​

Jalapeño's launch is another footnote in big-tech's collective challenge to NVIDIA's market dominance:

Vendor	In-house chip	Type	Status	Relation to OpenAI
Google	TPU v6e / Ironwood	Train+inference	✅ Commercial	Google Cloud supplies OpenAI
Amazon	Trainium 3	Training	✅ Launched	AWS supplies OpenAI
Microsoft	Maia 100	Train+inference	✅ Launched	OpenAI exclusive partner
Meta	MTIA	Train+inference	✅ Launched	—
Apple	Neural Engine	On-device inference	✅ Commercial	—
OpenAI	Jalapeño	Inference	🚧 Deploy end of 2026	Internal + possibly sold to third parties

5.2 OpenAI is not about to fully "abandon" NVIDIA​

Brockman admitted:

"We simply cannot get compute fast enough."

Currently OpenAI is simultaneously procuring chips from NVIDIA, AWS, AMD, and Cerebras; Jalapeño is a structural supplement to its explosive compute demand, not a replacement.

5.3 Possibly sold to third parties​

Broadcom CEO Hock Tan specifically emphasized:

"This is just 'the start of a multi-generation roadmap'; OpenAI and Broadcom aim to jointly build gigawatt-scale compute clusters."

This means OpenAI may sell its hardware to third parties, provided it can secure enough supply from Broadcom and TSMC.

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6. Jalapeño vs other in-house chips​

Metric	Jalapeño (OpenAI)	TPU v6e (Google)	Trainium 3 (Amazon)	Maia 100 (Microsoft)
Announced	2026-06-24	2024	Q4 2025	2023
Type	Inference ASIC	Train+inference TPU	Training ASIC	Train+inference
Process	TSMC 3nm	TSMC 4nm	TSMC 5nm (est.)	TSMC 5nm (est.)
For sale	❌ Internal only (maybe later)	✅ GCP	✅ AWS	❌ Internal only
Design cycle	9 months	~18 months	~18 months	~18 months
AI-assisted design	✅ First	❌ No	❌ No	❌ No
Cost advantage	-50% inference cost	Optimized	Optimized	Optimized

Key differences:

• ✅ Jalapeño is the first AI chip designed with AI assistance
• ✅ Jalapeño design cycle only 9 months (industry average 18 months)
• ⚠️ Jalapeño not for sale (at least for now)

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7. Future roadmap​

7.1 Multi-generation chip platform​

Jalapeño is just "the start of a multi-generation roadmap":

Time	Event
End of 2026	Jalapeño initial deployment (gigawatt-scale data centers)
2027	Jalapeño v2 (est., architecture optimization)
2027-2028	Jalapeño training version (est., challenging TPU/Trainium)
2028 and beyond	Gigawatt-scale compute cluster fully built

7.2 OpenAI full-stack AI infrastructure strategy​

Layer	OpenAI in-house	Outsourced/procured
Models	✅ GPT-5, GPT-5.3, Codex	—
Chips	✅ Jalapeño (inference)	NVIDIA GPU, AWS Trainium, AMD GPU
Systems	✅ With Celestica	Microsoft Azure data centers
Network	✅ Broadcom Tomahawk	Microsoft Azure network
Cloud platform	❌ None	Microsoft Azure (exclusive partner)

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8. Industry reaction and expert views​

8.1 Supportive views​

Expert	View
Broadcom CEO Hock Tan	"Jalapeño is just the start of a multi-generation roadmap; the goal is to jointly build gigawatt-scale compute clusters."
OpenAI President Greg Brockman	"We use the frontier models that serve our users to optimize the infrastructure that runs the models of the future."
Industry insiders	"Jalapeño's launch is another footnote in big-tech's collective challenge to NVIDIA's market dominance."

8.2 Skeptical views​

Concern	Description
Not for sale	Currently internal only; third parties cannot purchase, limited impact on NVIDIA's market share
Software ecosystem	OpenAI must build its own software stack; competing with CUDA is hard
Supply capacity	TSMC capacity is limited; can it meet OpenAI + Broadcom + other customers' demand?
Opaque performance data	OpenAI has not released specs (compute, memory, bandwidth, TDP), hard to assess objectively

---

9. Significance for developers​

9.1 If OpenAI sells Jalapeño to developers in the future...​

Scenario	Current (NVIDIA GPU)	Future (Jalapeño)
Inference cost	Baseline	-50%
Inference latency	Baseline	Possibly lower
Software stack	CUDA + TensorRT	OpenAI API (possibly open-source stack)
Procurement difficulty	High (export controls, supply shortage)	Low (OpenAI direct supply)

9.2 Worth watching even if not sold​

• ✅ 50% inference cost cut forces NVIDIA, AMD, Intel to lower GPU prices
• ✅ The AI-assisted chip design paradigm will be rapidly copied by the industry
• ✅ The 9-month tape-out cycle becomes a new industry benchmark

---

10. Summary​

Dimension	Assessment
Technology innovation	⭐⭐⭐⭐⭐ First AI chip designed with AI assistance, 9-month tape-out
Cost advantage	⭐⭐⭐⭐⭐ 50% inference cost cut, billions saved annually
Strategic significance	⭐⭐⭐⭐⭐ OpenAI transforms from pure model company to full-stack AI infrastructure provider
Market impact	⭐⭐⭐⭐ "De-NVIDIA-ification" accelerates, big-tech in-house chip camp grows
Openness	⭐⭐ Internal only for now, possibly sold to third parties later

Final recommendations:

• 🇨🇳 China market: Keep watching Huawei Ascend, Cambricon MLU, Moore Threads MTT (Jalapeño not sold to China)
• 🌍 International market: Watch whether Jalapeño is eventually sold externally and its impact on NVIDIA's market share
• 💡 Developers: Watch for possible OpenAI API price cuts (50% inference cost cut may partially pass through)

---

References​

• OpenAI official announcement (technical white paper pending)
• Broadcom CEO Hock Tan interview
• Bloomberg: Jalapeño inference cost cut 50%
• SemiWiki: Jalapeño technical details
• Tom's Hardware: Jalapeño architecture analysis
• ESMChina: Jalapeño 9-month tape-out

---

Disclaimer: Some specs in this article are estimates, subject to OpenAI's official technical white paper. OpenAI will release a detailed performance white paper in the coming months.

Last updated: June 26, 2026

Against the backdrop of U.S. export controls, China's AI chip market is forming a "three-way standoff." This article compares the technical routes, product specs, software ecosystems, and commercial progress of the three major domestic AI chip vendors: Huawei Ascend, Cambricon MLU, and Moore Threads MTT.

---

Key Points​

• Huawei Ascend: leader in domestic AI training chips; Ascend 950 in mass production; most mature software ecosystem
• Cambricon MLU690: the "China H100," compute close to H200, clear efficiency advantage
• Moore Threads MTT S5000: full-function GPU route; achieved Day-0 support for Qwen3.5 and GLM-5.2 in June 2026
• Shared challenge: affected by U.S. export controls, primarily aimed at the Chinese market, limited internationally

---

I. Vendor Overview​

Vendor	Founded	Founder	Listed	2025 Revenue	Main Customers
Huawei Ascend	2018 (division)	Ren Zhengfei	private (wholly owned by Huawei)	~¥20B (est.)	Chinese gov, SOEs, military
Cambricon	2016	Chen Tianshi (CAS)	2020-07 (STAR Market 688256)	~¥5.2B	ByteDance, Alibaba, Baidu
Moore Threads	2020	Zhang Jianzhong (ex-NVIDIA China)	2023-12 (STAR Market 688495)	~¥1.5B (est.)	gov, SOEs, gaming cos.

Strategic Positioning​

Vendor	Tech route	Core strength	Main challenge
Huawei Ascend	AI-training-specific (Da Vinci)	co-optimized HW/SW, carrier channels	sanctions, process limits
Cambricon	AI-training-specific (MLUarch)	high efficiency, competitive price	immature ecosystem
Moore Threads	Full-function GPU (MUSA)	graphics + AI + general compute, Day-0 support	compute below dedicated AI chips

---

II. Flagship Product Comparison​

1. Huawei Ascend 950DT (2026 flagship)​

Item	Spec
BF16 compute	1,000 TFLOPS
Memory	144GB HiZQ 2.0 (in-house HBM)
Memory bandwidth	4 TB/s
TDP	400W
Process	N+2 (improved 7nm)
Released	2026-04
Mass production	2026-Q2
Unit price	~¥80,000 (est.)

Strengths:

• ✅ High large-model inference throughput: 144GB memory friendly to DeepSeek R1 (671B MoE)
• ✅ Most mature ecosystem: CANN ~85% operator coverage, supports PyTorch, TensorFlow
• ✅ Strong carrier channel: China Mobile, China Telecom large purchases

Weaknesses:

• ❌ Process limited: N+2 below TSMC 4nm
• ❌ Mediocre efficiency: 400W TDP, 2.5 TFLOPS/W

---

2. Cambricon MLU690 (2026 flagship)​

Item	Spec
BF16 compute	600 TFLOPS
Memory	64GB HBM3
Memory bandwidth	2 TB/s
TDP	280W
Process	TSMC 7nm
Released	2025-Q4
Mass production	2026-Q1
Unit price	~¥140,000 (est.)

Strengths:

• ✅ Best efficiency: 280W TDP, 2.14 TFLOPS/W (1.5x H100)
• ✅ Competitive price: ~$20,000, 33% cheaper than H100
• ✅ Top-tier customer orders: ByteDance, Alibaba, Baidu

Weaknesses:

• ❌ Small memory: 64GB limits large-model training scale
• ❌ Immature ecosystem: NeuWare ~75–85% coverage; complex LLMs need manual tuning

---

3. Moore Threads MTT S5000 (2025 flagship)​

Item	Spec
FP16 compute	~1,000 TFLOPS (est.)
Memory	80GB GDDR6X
Memory bandwidth	1.6 TB/s
TDP	~350W
Process	TSMC 4nm (est.)
Released	2025-02
Mass production	2025-Q2
Unit price	~¥50,000 (est.)

Strengths:

• ✅ Full-function GPU: graphics + AI + general compute, broader scenarios
• ✅ Strong Day-0 support: June 2026 Day-0 support for Qwen3.5, GLM-5.2, MiniMax M3
• ✅ Lowest price: ~¥50,000, high cost-performance

Weaknesses:

• ❌ Compute below dedicated AI chips: FP16 ~50% of H100
• ❌ Low memory bandwidth: 1.6 TB/s (48% of H100), limits large-model training

---

III. Compute Comparison (BF16/FP16)​

Chip	BF16 compute	Memory	Bandwidth	TDP	Efficiency
Huawei Ascend 950DT	1,000 TFLOPS	144GB	4 TB/s	400W	2.5 TFLOPS/W
Cambricon MLU690	600 TFLOPS	64GB	2 TB/s	280W	2.14 TFLOPS/W
Moore Threads MTT S5000	~1,000 TFLOPS	80GB	1.6 TB/s	~350W	~2.86 TFLOPS/W
NVIDIA H100	989 TFLOPS	80GB	3.35 TB/s	700W	1.41 TFLOPS/W
NVIDIA H200	989 TFLOPS	141GB	4.8 TB/s	700W	1.41 TFLOPS/W

Key insights:

1. Ascend 950DT has the highest compute (1,000 TFLOPS) but mediocre efficiency
2. Cambricon MLU690 has the best efficiency (2.14 TFLOPS/W), TDP only 280W
3. Moore Threads MTT S5000 wins on full-function versatility but low bandwidth

---

IV. Software Ecosystem​

Vendor	Stack	Framework support	Coverage	Maturity
Huawei Ascend	CANN	PyTorch, TensorFlow, MindSpore	~85%	⭐⭐⭐⭐ (4/5)
Cambricon	NeuWare	PyTorch-Cambricon, TensorFlow-Cambricon	~75–85%	⭐⭐⭐ (3/5)
Moore Threads	MUSIFY	PyTorch, TensorFlow, ONNX	~70%	⭐⭐⭐ (3/5)
NVIDIA	CUDA	all	~99%	⭐⭐⭐⭐⭐ (5/5)

Ecosystem Maturity Assessment​

Huawei Ascend CANN:

• ✅ Strength: highest operator coverage, supports MindSpore (in-house framework)
• ❌ Weakness: steep learning curve, incomplete docs

Cambricon NeuWare:

• ✅ Strength: PyTorch/TensorFlow compatible, low migration cost
• ❌ Weakness: complex LLMs need manual tuning

Moore Threads MUSIFY:

• ✅ Strength: strong Day-0 support, ONNX support
• ❌ Weakness: lowest operator coverage, dual graphics+AI engine complexity

---

V. Commercial Progress​

Vendor	2026 commercial progress	Main customers	Shipments
Huawei Ascend	Ascend 950 mass production; China Mobile large purchase	China Mobile, China Telecom, gov	~100K/yr (est.)
Cambricon	MLU690 mass production; ByteDance, Alibaba orders	ByteDance, Alibaba, Baidu	~50K/yr (est.)
Moore Threads	MTT S5000 mass production; Day-0 Qwen3.5	gov, SOEs, gaming cos.	~30K/yr (est.)

Latest as of June 2026​

Huawei Ascend:

• ✅ Ascend 950DT fully ramping
• ✅ ¥1B procurement agreement with China Mobile

Cambricon:

• ✅ MLU690 in volume shipment
• ✅ ByteDance order ~20K units

Moore Threads:

• ✅ Day-0 support for Qwen3.5, GLM-5.2, MiniMax M3
• ✅ MTT S5000 2nd-gen released

---

VI. Selection Advice​

Scenario 1: Trillion-parameter training (GPT-4 class)​

Recommended: Huawei Ascend 950DT

• ✅ 144GB large memory supports super-large models
• ✅ Most mature ecosystem (~85% coverage)
• ✅ Strong carrier channel, Chinese government backing

Alternative: Cambricon MLU690 (high efficiency, but small memory)

Scenario 2: Tens-to-hundreds-of-billions parameter training​

Recommended: Cambricon MLU690

• ✅ Best efficiency (2.14 TFLOPS/W), low TCO
• ✅ Competitive price (~$20,000)
• ✅ Validated by top customers (ByteDance, Alibaba)

Alternative: Huawei Ascend 920 (more compute, mediocre efficiency)

Scenario 3: Cloud AI inference​

Recommended: Huawei Ascend 950PR (inference-specific)

• ✅ Well-optimized inference throughput
• ✅ 128GB memory friendly to MoE models
• ✅ Mature stack, low deployment cost

Alternative: Moore Threads MTT S5000 (full-function GPU, inference + graphics)

Scenario 4: Edge AI / on-device inference​

Recommended: Moore Threads MTT S5000

• ✅ Full-function GPU, graphics + AI
• ✅ Lowest price (~¥50,000)
• ✅ Strong Day-0 support

Alternative: Huawei Ascend 310 (low power, 8W TDP)

Scenario 5: Domestic substitution (gov, SOEs)​

Recommended: Huawei Ascend 950DT

• ✅ Chinese government first choice, carrier bulk buys
• ✅ Co-optimized HW/SW, stable performance
• ✅ Supported by national semiconductor fund

Alternative: Cambricon MLU690 (high efficiency, competitive price)

---

VII. Future Roadmap​

Vendor	2026 H2	2027	2028
Huawei Ascend	950DT ramp	960 (FP8 ~2 PFLOPS)	970 (N+3 process)
Cambricon	MLU690 ramp	MLU790 (5nm, BF16 ~1,000 TFLOPS)	MLU890 (3nm)
Moore Threads	MTT S5000 2nd-gen	MTT S6000 (HBM3, FP16 ~1,500 TFLOPS)	MTT S7000

---

VIII. Summary: Who Is the "China H100"?​

Dimension	Ascend 950DT	MLU690	MTT S5000
Compute	⭐⭐⭐⭐⭐ (5/5)	⭐⭐⭐ (3/5)	⭐⭐⭐ (3/5)
Memory	⭐⭐⭐⭐⭐ (5/5)	⭐⭐ (2/5)	⭐⭐⭐ (3/5)
Efficiency	⭐⭐⭐ (3/5)	⭐⭐⭐⭐⭐ (5/5)	⭐⭐⭐⭐ (4/5)
Ecosystem	⭐⭐⭐⭐ (4/5)	⭐⭐⭐ (3/5)	⭐⭐⭐ (3/5)
Price	⭐⭐⭐ (3/5)	⭐⭐⭐⭐ (4/5)	⭐⭐⭐⭐⭐ (5/5)
Overall	⭐⭐⭐⭐ (4/5)	⭐⭐⭐ (3/5)	⭐⭐⭐ (3/5)

Final conclusion:

• Huawei Ascend 950DT is the domestic AI training chip closest to H100, strongest overall
• Cambricon MLU690 is the most efficient domestic AI chip, lowest TCO
• Moore Threads MTT S5000 is the cheapest full-function GPU, suited to edge AI and graphics+AI

---

References​

• Huawei Ascend 950 series — MirrorFrog detailed specs
• Cambricon MLU690 — MirrorFrog detailed specs
• Moore Threads MTT S5000 — MirrorFrog detailed specs
• Full AI chip comparison table — 100+ chip specs
• 2026 H2 AI chip roadmap major update — latest roadmap

---

Disclaimer: Data based on public sources; actual specs per vendor official. MirrorFrog continuously updates domestic AI chip data — corrections welcome.

Changelog: 2026-06-23 initial release

In 2026, against the backdrop of U.S. export controls on AI chips to China, Cambricon's MLU690 has drawn intense attention as a "China-made H100." This article compares the two in depth across compute, memory, power, software ecosystem, measured performance, and price to help you make a selection decision.

Core Verdict (Read This First)​

Dimension	MLU690	H100	Winner	Gap
BF16 compute	600 TFLOPS	989 TFLOPS	H100	+65%
Memory capacity	64GB HBM3	80GB HBM3	H100	+25%
Memory bandwidth	2 TB/s	3.35 TB/s	H100	+68%
TDP	280W	700W	MLU690	-60%
Energy efficiency	2.14 TFLOPS/W	1.41 TFLOPS/W	MLU690	+52%
Software ecosystem	NeuWare (~75% coverage)	CUDA (100% coverage)	H100	large gap
Price	~¥140,000	~¥200,000	MLU690	-30%
Availability	domestic spot stock	export-controlled	MLU690	✅

One-line summary: MLU690 delivers roughly 60% of H100's compute, but at only 40% of the power and 70% of the price — a strong fit for AI training and inference in the Chinese market.

---

1. Detailed Spec Comparison​

1.1 Compute​

Precision	MLU690	H100 SXM5	H200 SXM5	Note
FP8	~300 TFLOPS (est.)	3,958 TFLOPS	3,958 TFLOPS	H100 supports FP8; MLU690 likely does not
BF16/FP16	600 TFLOPS	989 TFLOPS	989 TFLOPS	H100 leads by 65%
FP32	~150 TFLOPS (est.)	60 TFLOPS	60 TFLOPS	MLU690 estimate; H100 actually higher
INT8	1,200 TOPS	1,979 TOPS	1,979 TOPS	H100 leads by 65%

Key findings:

• ✅ MLU690 reaches 60% of H100's BF16 compute
• ⚠️ H100 supports FP8 (4-bit); MLU690 likely does not (needs confirmation)
• ⚠️ H100's higher INT8 compute favors inference scenarios

1.2 Memory​

Item	MLU690	H100	H200	Note
Capacity	64GB HBM3	80GB HBM3	141GB HBM3e	H200 largest
Bandwidth	2 TB/s	3.35 TB/s	4.8 TB/s	H200 highest
Type	HBM3	HBM3	HBM3e	H200 uses latest HBM3e

Key findings:

• ⚠️ MLU690 has 20% less memory than H100 (64GB vs 80GB)
• ⚠️ MLU690 bandwidth is 40% lower than H100 (2 TB/s vs 3.35 TB/s)
• ❌ When running 70B+ parameter models, MLU690 may run out of memory (model parallelism required)

1.3 Power​

Item	MLU690	H100	H200
TDP	280W	700W	700W
Efficiency (FP16/W)	2.14 TFLOPS/W	1.41 TFLOPS/W	1.41 TFLOPS/W
8-card server power	~3.5kW	~6kW	~6kW
Annual electricity (¥0.6/kWh)	~¥18,400	~¥36,800	~¥36,800

Key findings:

• ✅ MLU690 draws only 40% of H100's power, sharply cutting data-center electricity cost
• ✅ MLU690 leads efficiency by 52%, better suited to large-scale deployment
• ✅ For power-sensitive inference, MLU690 has a clear edge

---

2. Software Ecosystem​

2.1 Framework Support​

Framework	MLU690 (NeuWare)	H100 (CUDA)	Note
PyTorch	✅ (PyTorch-Cambricon)	✅ native	MLU690 needs an extra plugin
TensorFlow	✅ (TensorFlow-Cambricon)	✅ native	same
JAX	⚠️ partial	✅ native	MLU690 limited
ONNX	⚠️ partial	✅ native	same
vLLM	⚠️ in progress	✅ native	MLU690 awaits community port

2.2 Operator Coverage​

Category	MLU690	H100	Note
Basic operators	✅ 95%	✅ 100%	conv, matmul, etc.
Transformer operators	✅ 85%	✅ 100%	Attention, LayerNorm, etc.
Custom operators	⚠️ hand-written	✅ CUDA C++	MLU690 harder to develop
LLM inference opt.	⚠️ basic	✅ mature (FlashAttention, PagedAttention)	H100 leads

Key findings:

• ⚠️ NeuWare is only 5–6 years old, with ~75–85% operator coverage
• ❌ Complex LLMs (e.g., GPT-4, Claude) may need manual optimization
• ✅ Common models (Llama, Qwen, GLM) are essentially already supported

---

3. Measured Performance​

3.1 Training​

Model	MLU690 (time)	H100 (time)	Speedup
Llama 7B	~48 h (est.)	~30 h	1.6x
Llama 70B	~7 days (est.)	~4.5 days	1.6x
Qwen 72B	~8 days (est.)	~5 days	1.6x

Note: above figures are estimates; real performance depends on software optimization.

3.2 Inference​

Model	MLU690 (tok/s)	H100 (tok/s)	Note
Llama 7B	~80 tok/s (est.)	~120 tok/s	H100 +50%
Llama 70B	~20 tok/s (est.)	~35 tok/s	H100 +75%
Qwen 72B	~18 tok/s (est.)	~30 tok/s	H100 +67%

Key findings:

• ⚠️ H100 leads inference by 50–75%
• ✅ But MLU690 draws only 40% the power, with better efficiency
• ✅ For cost-sensitive inference, MLU690 is more economical

---

4. Price​

4.1 Hardware Procurement​

Item	MLU690	H100	H200
Per-card (domestic)	~¥140,000	~¥200,000	~¥300,000
8-card server (turnkey)	~¥1,200,000	~¥1,800,000	~¥2,600,000
Cost gap	-	+50%	+117%

4.2 TCO (3 years)​

Item	MLU690	H100	Note
Hardware	¥1,200,000	¥1,800,000	MLU690 33% cheaper
Electricity (3y)	¥55,200	¥110,400	MLU690 50% cheaper
Facility	¥150,000	¥250,000	MLU690 40% cheaper
TCO (3y)	¥1,405,200	¥2,160,400	MLU690 35% cheaper

Key findings:

• ✅ MLU690's TCO is 35% lower than H100's
• ✅ For large-scale deployment (100+ cards), the cost advantage is pronounced

---

5. Selection Advice​

5.1 Choose MLU690 if...​

• ✅ Your business is primarily in the Chinese market
• ✅ You are affected by U.S. export controls and cannot buy H100/H200
• ✅ You are power-sensitive (edge data centers, high electricity-cost regions)
• ✅ Your models use common architectures (Llama, Qwen, GLM)
• ✅ You have domestic-substitution requirements (government, SOEs, military)

5.2 Choose H100/H200 if...​

• ✅ Your business is global
• ✅ You need to train frontier models (GPT-4 class)
• ✅ Your models use complex operators (need the CUDA ecosystem)
• ✅ You demand extreme performance (low-latency inference)
• ✅ You can legally procure H100/H200

5.3 Hybrid deployment (recommended)​

Scenario	Recommended
Training	H100 (high perf) + MLU690 (low-cost scale-out)
Inference	MLU690 (cost-sensitive) + H100 (low-latency)
Domestic project	all MLU690
International market	all H100/H200

---

6. Outlook​

6.1 MLU690's weaknesses​

• ⚠️ Immature software ecosystem: 75–85% operator coverage; complex models need manual tuning
• ⚠️ Small memory: 64GB limits support for 70B+ parameter models
• ⚠️ Weak interconnect: Cambricon Link bandwidth below NVLink
• ⚠️ Limited international market: affected by U.S. export controls

6.2 MLU690's improvement path​

• 📅 MLU790 (2027): expected 5nm process, ~2x compute
• 📅 Memory upgrade: next gen may adopt HBM3e, capacity up to 128GB
• 📅 Software: NeuWare ecosystem improving, operator coverage target 95%

---

7. Summary​

Dimension	MLU690	H100	Recommended scenario
Compute	⭐⭐⭐⭐	⭐⭐⭐⭐⭐	H100 for top-tier training
Memory	⭐⭐⭐	⭐⭐⭐⭐	H100 for large models
Power	⭐⭐⭐⭐⭐	⭐⭐⭐	MLU690 for inference
Ecosystem	⭐⭐⭐	⭐⭐⭐⭐⭐	H100 for complex models
Price	⭐⭐⭐⭐⭐	⭐⭐⭐	MLU690 for large-scale deployment
Domestic	⭐⭐⭐⭐⭐	❌	MLU690 for Chinese market

Final recommendation:

• 🇨🇳 Chinese market: prefer MLU690 (domestic + low cost)
• 🌍 International market: prefer H100/H200 (performance + ecosystem)
• 💡 Hybrid: train on H100, infer on MLU690

---

References​

• Cambricon MLU690 spec page
• NVIDIA H100 spec page
• Full AI chip comparison table
• TCO calculator

---

Disclaimer: Data in this article is based on public sources and reasonable estimates; actual performance is subject to vendor official testing. MLU690's software ecosystem is evolving rapidly — watch NeuWare updates.

Last updated: 2026-06-23

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.

---

Key Takeaways​

• Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
• AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
• Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
• Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
• NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

---

1. Qualcomm: Mobile Giant Moves Into Datacenter AI​

AI 100 → AI 200 → AI 250​

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

Model	Launch	Availability	Key Features
AI 100	2025-10	2026 H2	Rack-scale AI inference, 768GB LPDDR per card
AI 250	2025-10	2027 H1	Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed​

1. Low TCO: LPDDR memory is far cheaper than HBM
2. Energy efficiency: Mobile chip design heritage, excellent power control
3. Inference-focused: Not chasing training performance, focused on inference scenarios
4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact​

• Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
• Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
• Diversifies choice: Breaks NVIDIA's monopoly in the inference market

---

2. AMD MI400 Series: Three Models, Precise Positioning​

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)​

Feature	Spec
Positioning	HPC + sovereign AI
FP32/FP64	Supported (key differentiator)
Use cases	Scientific computing, climate simulation, national AI infrastructure
Competitor	NVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)​

Feature	Spec
Positioning	Enterprise 8-GPU servers
Compatibility	Works with existing datacenter infrastructure
Use cases	Enterprise AI, private cloud, edge inference
Advantage	Cheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)​

Feature	Spec
Positioning	Flagship AI training + inference
Optimized precision	FP4/FP8/BF16
Helios rack	Core component
Competitor	NVIDIA Rubin R200

Helios Rack-Scale Solution​

AMD also launched the Helios rack-scale AI solution at CES 2026:

• 18 Zen 6 CPUs (2nm process)
• 72 MI455X GPUs
• Direct liquid cooling
• Shipment expected in 2026 H2

---

3. Huawei Three-Generation Roadmap: 950 → 960 → 970​

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)​

Model	Launch	Key Features
950PR	2026-Q1	PR (inference-optimized), already in mass production
950DT	2026-Q4	DT (Decode + training), expected to scale up

Technical highlights:

• Added FP8/MXFP8/MXFP4 support
• Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)​

• Doubled compute: All specs double versus the 950 series
• FP8: ~2 PFLOPS expected
• Process: N+3 (equivalent to 5nm)
• Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)​

• Third-generation flagship: Only timeline announced, specs TBD
• Significance: Huawei's first complete generation-spanning roadmap
• Signal: China's domestic AI chips have entered a "roadmap-driven" phase

---

4. Intel Jaguar Shores: Timeline Uncertain​

Original Plan​

• Launch: 2026
• Architecture: Xe-HPC + Gaudi fusion
• Process: 18A (Intel's most advanced)
• Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments​

• Possible delay: Some sources suggest a slip to 2027
• Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
• Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap​

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.

---

5. NVIDIA Rubin Platform: Full Mass Production​

Rubin R200 (2026-Q2 full mass production)​

Feature	Spec
HBM	288GB HBM4
Compute	50 PFLOPS FP4
NVLink	NVLink 6 (1800 GB/s)
Process	TSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)​

• 72 Rubin GPUs
• 36 Vera CPUs
• 1.8 EFLOPS FP4
• Direct liquid cooling

Vera CPU (Debut)​

• Architecture: Custom CPU replacing Grace
• Positioning: Deep co-design with Rubin GPU
• Significance: NVIDIA's transformation from a GPU company into a computing platform company

---

6. Google TPU v8: Training/Inference Officially Split​

TPU 8t (training) + TPU 8i (inference)​

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

Feature	TPU 8t (training)	TPU 8i (inference)
Optimization	High compute, high bandwidth	Low latency, low cost
Interconnect	Optical interconnect	Ethernet
Launch	2027	2027

Significance​

• Industry trend: Specialization of training/inference chips
• Followers: Qualcomm AI 200 is also inference-only
• NVIDIA pressure: Does it need an inference-specific chip?

---

7. Cerebras WSE-4: Wafer-Scale Engine Evolves​

Core Specs​

Feature	Spec
Transistors	1.4 trillion
Compute	125 PFLOPS FP8
Launch	2026 H2
Process	TSMC 5nm

Competitive Advantages​

• Massive model training: A single WSE-4 can train 10T+ parameter models
• Low-latency inference: Entire model on one chip, no communication overhead
• Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

---

8. Market Landscape Analysis​

Training Market​

Rank	Vendor	Product	Market Share (est.)
1	NVIDIA	Rubin R200	70%
2	AMD	MI455X	15%
3	Google	TPU v8t	10%
4	Huawei	Ascend 960	5% (mostly China)

Inference Market (New Battlefield)​

Rank	Vendor	Product	Advantage
1	NVIDIA	H200 / Rubin CPX	Mature ecosystem
2	Qualcomm	AI 200	Low TCO
3	AMD	MI440X	Good compatibility
4	Intel	Gaudi 4	Low price

---

9. Key Trends​

Trend 1: Rise of Inference-Specific Chips​

• Qualcomm AI 200: Mobile giant enters the market
• NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
• Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard​

• NVIDIA NVL72: 72 GPU + 36 CPU
• AMD Helios: 18 CPU + 72 GPU
• Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase​

• Huawei three-generation roadmap: 950 → 960 → 970
• Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
• Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck​

• SK hynix: HBM4 capacity already booked by NVIDIA
• Samsung: HBM4E samples delivered to AMD
• Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

---

10. Procurement Recommendations​

If Procuring in 2026 H2​

1. Training scenarios:

   • First choice: NVIDIA Rubin R200 (best performance)
   • Alternative: AMD MI455X (better price/performance)
   • Domestic: Huawei Ascend 950DT (China-based customers)

2. Inference scenarios:

   • First choice: NVIDIA H200 (mature ecosystem)
   • Best value: Qualcomm AI 200 (if available)
   • Cost-sensitive: AMD MI440X

3. HPC scenarios:

   • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027​

• Wait for Rubin Ultra: Performance possibly 2x R200
• Watch MI500: AMD's next-generation product
• Evaluate TPU v8: If already on Google Cloud

---

Conclusion​

2026 H2 will be the most fiercely contested half-year in AI chip market history:

• NVIDIA continues to lead, but its advantage is narrowing
• AMD precisely positions three models; market share will keep rising
• Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
• Huawei has a clear three-generation roadmap; domestic substitution accelerates
• Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.

---

References​

• AI Compute Card Future Roadmap - MirrorFrog real-time updates
• NVIDIA Rubin R200 deep dive (see related articles on this site)
• AMD MI400 series CES 2026 launch (see related articles on this site)
• Qualcomm AI 100 launch analysis (coming soon)

---

Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement

On January 5, 2026, on the opening day of CES 2026 (Consumer Electronics Show), AMD Chair and CEO Dr. Lisa Su unveiled in her keynote: the Instinct MI400 series AI accelerators.

The most eye-catching is MI455X — AMD's most powerful AI accelerator ever, using a 2nm + 3nm hybrid process, 432GB HBM4, with FP4 compute up to 40 PFLOPS (20 PFLOPS FP8).

Key highlights​

• MI455X: FP4 40 PFLOPS, FP8 20 PFLOPS, 10× over MI355X
• MI450: cost-performance version, FP4 28 PFLOPS, 288GB HBM4
• Process upgrade: world's first AI chip with 2nm + 3nm hybrid process (GCD on 2nm, MCD on 3nm)
• Memory upgrade: from MI350X's 288GB HBM3e to 432GB HBM4 (MI455X)
• Bandwidth upgrade: from MI350X's 8 TB/s to 19.6 TB/s (2.45×)
• Architecture upgrade: from CDNA 4 to CDNA 5
• Mass production: MI455X Q4 2026, MI450 Q3 2026

Full MI400 series specs​

📌 Important correction (2026-06-16): After official spec verification, MI455X memory is 432GB HBM4 (not the earlier reported 288GB), and FP4 compute is 40 PFLOPS. Corrected herein.

Model	Positioning	Memory	FP4 compute	FP8 compute	TDP (est.)
MI455X	Flagship training+inference	432GB HBM4	40 PFLOPS	20 PFLOPS	~1,000W
MI450	Cost-performance training	288GB HBM4	28 PFLOPS	14 PFLOPS	~800W
MI440X	Enterprise inference	216GB HBM4	25 PFLOPS	12.5 PFLOPS	~600W
MI430X	HPC / scientific computing	192GB HBM4	20 PFLOPS	10 PFLOPS	~500W
MI400X	General / edge inference	128GB HBM4	12 PFLOPS	6 PFLOPS	~400W

Key upgrades (vs MI350 series):

• Memory: HBM3e → HBM4, capacity +50% (432GB vs 288GB)
• Bandwidth: 19.6 TB/s (vs MI350's 8 TB/s, +2.45×)
• Compute: FP4 40 PFLOPS (vs MI355X's 20 PFLOPS, +2×)
• Process: 2nm + 3nm hybrid (GCD on 2nm, MCD on 3nm)
• Architecture: CDNA 5 (vs MI350's CDNA 4)

Performance vs. MI355X​

Metric	MI355X (2025)	MI455X (2026)	Improvement
FP4 compute	20 PFLOPS	40 PFLOPS	2×
FP8 compute	10 PFLOPS	20 PFLOPS	2×
Memory capacity	288GB HBM3e	432GB HBM4	1.5×
Memory bandwidth	8 TB/s	19.6 TB/s	2.45×
Process	TSMC 3nm	2nm + 3nm hybrid	New gen
Architecture	CDNA 4	CDNA 5	New gen
TDP	800-1000W	~1,000W	Flat

Lisa Su at CES 2026:

"Four years ago, MI250's AI performance was X. Today, MI455X's performance is 1000× that. That's the pace of AI chip progress."

CDNA 5 architecture in detail​

The MI400 series adopts the CDNA 5 architecture (MI355X uses CDNA 4):

Key upgrades​

1. Matrix Core upgrade: FP8/INT8/FP16 support, sparsity acceleration
2. HBM4 controller: 12-layer HBM4 (vs HBM3e's 8 layers)
3. Infinity Fabric 4.0: 50% higher die-to-die / die-to-GPU bandwidth
4. Native sparsity support: MoE Expert-Parallel optimization
5. Long-context optimization: 1M+ token KV Cache acceleration

vs. NVIDIA Blackwell / Rubin​

Metric	AMD MI455X	NVIDIA B200	NVIDIA Rubin R200 (2026 Q4)
FP4 compute	40 PFLOPS	20 PFLOPS (45 sparse)	~40 PFLOPS (est.)
FP8 compute	20 PFLOPS	10 PFLOPS (22.5 sparse)	~20 PFLOPS (est.)
Memory	432GB HBM4	192GB HBM3e	288GB HBM4
Memory bandwidth	19.6 TB/s	8 TB/s	13 TB/s
TDP	~1,000W	700-1000W	~1,000W
Process	2nm + 3nm hybrid	TSMC 4np	TSMC 3nm
Mass production	2026 Q4	2024 Q4	2026 Q4
Software ecosystem	ROCm	CUDA	CUDA
Strength	Memory capacity, open ecosystem	Most mature ecosystem	Next-gen architecture
Weakness	Software ecosystem gap	Smaller memory	Not yet launched

Conclusion: MI455X leads B200 in FP4/FP8 compute and memory capacity/bandwidth, but software ecosystem remains a weak point. Versus Rubin R200, paper specs are close, but Rubin has the CUDA ecosystem moat.

Production timeline​

Time	Event
June 12, 2025	MI400 series specs first announced at Advancing AI
January 5, 2026	MI455X/MI450/MI440X formally launched at CES 2026
2026 Q3	MI450 sampling begins
2026 Q4	MI455X mass production
2026 Q4	MI440X (enterprise inference) launched
2027 Q1	MI430X/MI400X (HPC/edge inference) launched
2027	MI500 series (next gen)

AMD AI chip roadmap (2025-2027)​

Time	Product	Process	Notes
Q4 2024	MI325X	TSMC 5nm	HBM3e upgraded
Q3 2025	MI355X (MI350 series)	TSMC 3nm	CDNA 4, 288GB HBM3e
Q4 2026	MI455X (MI400 series)	2nm + 3nm hybrid	CDNA 5, 432GB HBM4
Q1 2027	MI500 series	TSMC 2nm (est.)	Next gen, further gains

Software ecosystem: ROCm's progress and challenges​

✅ Progress​

• PyTorch 2.5+: native MI300X/MI455X support
• Hugging Face Transformers: official AMD GPU support
• vLLM 0.8+: MI300X inference support (experimental)
• JAX: AMD adapting (vs Google TPU)

⚠️ Challenges​

• Framework optimization: PyTorch on AMD GPUs still below NVIDIA
• Operator coverage: some niche operators need hand-written HIP
• Multi-card communication: RCCL (vs NCCL) still lags
• Developer ecosystem: tutorials, cases, community activity far below NVIDIA

Competitive comparison​

Vendor	Product	FP4 compute	Memory	Mass production	Strength	Weakness
AMD	MI455X	40 PFLOPS	432GB HBM4	2026 Q4	Largest memory, open ecosystem	Software gap
NVIDIA	B200	20 PFLOPS	192GB HBM3e	2024 Q4	Most mature ecosystem	Smaller memory
NVIDIA	Rubin R200	~40 PFLOPS	288GB HBM4	2026 Q4	Next-gen architecture, CUDA	Expensive
Huawei	Ascend 910C	~1.6 PFLOPS	64GB HBM	2026 Q2	China-localized	Export-controlled
Google	TPU 8t	~9.2 PFLOPS	~256GB HBM3e	Late 2027	Gemini-integrated	Google Cloud only

Industry impact​

1. Impact on NVIDIA​

On paper, AMD MI455X has already caught up to B200 (FP4 40 PFLOPS vs 20 PFLOPS), even leading substantially in memory capacity (432GB vs 192GB).

But:

• NVIDIA has the CUDA ecosystem moat
• NVIDIA has the Vera Rubin platform (full solution, 2026 Q4)
• AMD only sells cards/nodes, NVIDIA sells AI factories
• MI455X mass production (2026 Q4) coincides with Rubin R200 — head-on competition

2. Pressure on domestic chips​

MI455X's launch means: mainstream international AI chips enter the 2nm + HBM4 era in 2026.

Domestic chips (Huawei Ascend, Cambricon, MetaX, etc.) need to:

• Catch up to 5nm + HBM3e by 2026-2027
• Otherwise the gap widens from "1 generation" to "2 generations"

3. Significance for cloud providers​

MI455X gives cloud providers a second option beyond NVIDIA:

• Microsoft Azure: already deployed MI355X, may follow with MI455X
• Google Cloud: in-house TPU, won't use AMD
• Amazon AWS: in-house Trainium/Inferentia, won't use AMD
• Alibaba Cloud, Tencent Cloud: may procure MI455X as NVIDIA alternative

Related chips​

• AMD MI455X - the new launch
• AMD MI300X - previous flagship
• AMD MI325X - HBM3e upgraded
• NVIDIA B200 - direct competitor
• NVIDIA Rubin R200 - same-generation competitor

References​

• MI455X chip - Baidu Baike - official specs
• AMD drops its most powerful two-gen AI chips! World's first 432GB HBM4 - Zhihu - on-site report
• Taking on NVIDIA: AMD launches MI440X for enterprise AI data centers - Tencent News
• AMD MI400 packs 432GB HBM4: specs crush NVIDIA on paper - CocoLoop
• AMD CES 2026 keynote replay

---

This article is compiled from AMD CES 2026 official announcements, Baidu Baike, and Zhihu on-site reports; specs verified against official sources. Updated 2026-06-16: corrected MI455X memory (288GB → 432GB) and compute (FP8 6 PFLOPS → FP4 40 PFLOPS).

On April 22, 2026, at Google Cloud Next '26 in Las Vegas, Google officially launched its 8th-generation Tensor Processing Unit (TPU). For the first time in Google's history, it split AI training and inference onto two independent chips:

• TPU 8t: designed for model training
• TPU 8i: focused on high-concurrency inference

This launch introduces no new physical concept, but focuses on solving the core pain points of AI data centers: ten-thousand-card cluster scaling efficiency, Agentic AI workload optimization, and performance per watt.

TPU 8i (inference-specific): eliminating the "waiting room effect"​

TPU 8i is the first inference-specific chip co-designed by Google and MediaTek, aimed at eliminating the "waiting room effect" — where user requests are intentionally queued or delayed to maximize hardware utilization.

TPU 8i core specs (estimated)​

Parameter	TPU 8i	TPU v7 Ironwood
Positioning	Inference-specific	Mostly inference
Process	TSMC 2nm	—
Die design	Dual compute die (est.)	—
Memory	8× HBM3e 12-layer (~192GB est.)	8× HBM3 (192GB)
Memory bandwidth	~7 TB/s (est.)	7,380 GB/s
FP8 compute	~4,614 TFLOPS (est.)	4,614 TFLOPS
TDP (per chip)	1,300 W	1,000 W
Interconnect	ICI 3D Torus	ICI 3D Torus
Integrated CPU	Arm Axion (64 cores)	None
Cooling	Air or liquid	4th-gen liquid
Announced	2026-04-22	2025-08-25
Mass production	End of 2027	2026

Key features:

• ✅ High-concurrency inference optimization: built for Agentic AI, supports inference chains of thousands of steps
• ✅ Arm Axion CPU integration: 64-core Neoverse V2, host CPU + data preprocessing synergy
• ✅ Low latency: eliminates the "waiting room effect", extremely low TTFT (time to first token)
• ✅ 117% better performance per watt: vs Ironwood (at equal price)

TPU 8t (training-specific): the "engine" of Gemini 3/4​

TPU 8t is designed for training Google's frontier models like Gemini 3 / Gemini 4, continuing Google's long-term partnership with Broadcom.

TPU 8t core specs​

Parameter	TPU 8t	TPU v7 Ironwood	Improvement
Positioning	Training-specific	Mostly inference	Form-factor split
Process	TSMC 2nm	—	New gen
Die design	Dual compute die	—	Architecture upgrade
Memory	8× HBM3e 12-layer (~256GB per chip est.)	8× HBM3 (192GB)	Upgrade
Memory bandwidth	~7 TB/s (per chip est.)	7,380 GB/s	Flat
Pod chip count	9,600 chips	9,216	+4%
Pod total HBM	2 PB	—	Far exceeds
Pod FP4 compute	121 EFLOPS	~42 EFLOPS (est.)	~3×
Integrated CPU	Arm Axion (64 cores)	None	New
TDP (per chip)	1,300 W	1,000 W	+30%
Mass production	End of 2027	2026	—

Key features:

• ✅ Native MoE training support: Expert-Parallel optimization (DeepSeek / Mixtral style)
• ✅ Long-context training: 1M+ token context training optimization
• ✅ RLHF / post-training: native Online RL (DPO/PPO/GRPO) optimization
• ✅ Arm Axion CPU synergy: data preprocessing / weight init offloaded to CPU
• ✅ SparseCore acceleration: MoE routing and recommendation systems

Strategic significance of the 8th-generation TPU​

1. Training and inference split for the first time​

Previously, Google's TPU design philosophy was "one architecture for both training and inference" (e.g., TPU v5p, v6e). But the arrival of the Agentic AI era changed that:

• Training workloads: large-scale matrix multiply, long-sequence backpropagation, sparse MoE
• Inference workloads: high concurrency, low latency, KV Cache-intensive, dynamic batching

These two workloads impose very different demands on chip architecture. After the split:

• TPU 8t can focus on optimizing compute density and memory capacity
• TPU 8i can focus on optimizing inference throughput and performance per watt

2. Dual-track partnership with Broadcom and MediaTek​

• Broadcom: continues designing TPU 8t (training), extending the long-term partnership since TPU v1
• MediaTek: first-time collaboration designing TPU 8i (inference), bringing mobile-chip low-power design expertise

This "dual-track" strategy lets Google:

• Pursue peak performance on training chips (combined with Broadcom's high-end ASIC experience)
• Pursue peak energy efficiency on inference chips (combined with MediaTek's mobile-chip experience)

3. Versus NVIDIA Vera Rubin​

Comparison	Google TPU 8t + 8i	NVIDIA Vera Rubin
Strategy	Training/inference split	Unified architecture (GPU+CPU)
Process	TSMC 2nm	TSMC 3nm (est.)
Ecosystem	Google Cloud only	Globally available
Software	JAX / PyTorch-XLA	CUDA / PyTorch
Mass production	End of 2027	Fall 2026
Strength	Deep Gemini integration	Most mature ecosystem

Deep technical analysis​

TSMC 2nm: why 2nm?​

Google is the first vendor to adopt TSMC 2nm on an AI accelerator (NVIDIA Rubin uses 3nm). 2nm (N2) vs 3nm (N3E):

• Transistor density: ~15-20% higher
• Power reduction: ~25-30% (at equal performance)
• Performance gain: ~10-15% (at equal power)

For TPU 8t/8i, which already hit 1,300W, 2nm is mandatory — otherwise 4nm/3nm couldn't integrate dual compute dies and 8× HBM3e within reasonable power.

Arm Axion CPU: Google's in-house CPU enters the TPU node for the first time​

Previously, TPU nodes used Intel Xeon or AMD EPYC as host CPUs. TPU 8t/8i integrate Google's in-house Arm Axion CPU (64-core Neoverse V2) for the first time:

Significance:

1. Data preprocessing offload: tokenization, data augmentation can run entirely on Axion, freeing TPU compute
2. Weight initialization: large-model training weight init on CPU, accelerating training startup
3. Inference scheduling: Axion handles request scheduling and load balancing for multi-model inference

This marks the TPU node's evolution toward a "SuperNode": no longer a pure accelerator, but a TPU + Axion CPU co-design system, comparable to NVIDIA's Vera CPU.

4th-gen liquid cooling: the 1,300W thermal challenge​

TPU 8t/8i TDP reaches 1,300W (30% over Ironwood's 1,000W), posing a huge data-center cooling challenge.

Google adopts a 4th-gen liquid cooling solution:

• Cold-plate liquid cooling: directly cools GPU die and HBM
• Immersion cooling: optional (ultra-high-density deployment)
• Smart thermal control: dynamically adjusts pump speed and fan RPM by workload

Production timeline and use cases​

Time	Event
2026-04-22	Cloud Next '26 official announcement
H2 2026	Internal testing (Google DeepMind first)
End of 2027	Mass production, Google Cloud availability
2028	Next-gen TPU (possibly TPU 9)

Target use cases:

• ✅ Frontier model training (Gemini 3/4, external customers)
• ✅ MoE large-model inference (high concurrency, low latency)
• ✅ Multimodal AI (ViT + LLM simultaneous inference)
• ✅ Agentic AI (Agentic AI workloads)

Competitive comparison​

Vendor	Product	Process	TDP	Mass production
Google	TPU 8i (inference)	TSMC 2nm	1,300W	End of 2027
Google	TPU 8t (training)	TSMC 2nm	1,300W	End of 2027
NVIDIA	Rubin GPU	TSMC 3nm (est.)	~1,000W	Fall 2026
NVIDIA	Vera CPU	TSMC 3nm (est.)	~500W	Fall 2026
AMD	MI455X (MI400)	TSMC 3nm (est.)	~700W	2026
Huawei	Ascend 950PR	—	~500W	Q1 2026

Industry impact​

1. AI chips enter the 2nm era: Google leads with TSMC 2nm; NVIDIA and AMD will follow
2. Training/inference split becomes a new trend: other vendors (NVIDIA, AMD) may follow suit
3. In-house CPUs become standard: Google (Axion), NVIDIA (Vera), Huawei (Kunpeng) all do CPU+accelerator co-design
4. Liquid cooling becomes inevitable: 1,300W TDP means air cooling can no longer suffice

Related chips​

• Google TPU 8i - inference-specific TPU detailed specs
• Google TPU 8t - training-specific TPU detailed specs
• Google TPU v7 Ironwood - previous-gen inference TPU
• NVIDIA Rubin R200 - same-generation competitor
• NVIDIA Vera CPU - counterpart to Google Axion

References​

• Google blog: Introducing new TPUs at Cloud Next '26
• Google Cloud Next '26 keynote replay
• Tencent News: Google 8th-gen TPU deep dive

---

This article is compiled from Google's official announcements and public sources; some specs are estimates, subject to final official release.

On June 5, 2026, Shenzhen announced a major piece of news: Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, used 1,000 Huawei Ascend 910C chips to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model.

This was no tentative attempt, but a milestone technological breakthrough. It proved with irrefutable engineering results that: domestic AI chips are fully capable of supporting world-class, super-large-parameter model training.

Why this matters​

The two thresholds of AI chips: "inference" and "training"​

• Inference: using an existing model to chat, write copy. Domestic chips could already do this
• Training: adjusting model parameters to learn new capabilities. Full-parameter training adjusts all 1.6 trillion parameters at once — maximum difficulty

Previously, full-parameter training of trillion-scale models was monopolized by NVIDIA H100/H200. Domestic chips could only do inference, not large-scale training.

The significance of this breakthrough: domestic compute leapt from "usable" to "useful", from "inference" to "training".

Technical details​

Training configuration​

Item	Parameter
Chips	Huawei Ascend 910C × 1,000
Model	DeepSeek-V4-Pro
Parameters	1.6 trillion (1600B)
Training type	Full-parameter post-training
Framework	MindSpore + torch_npu
Completed	Announced June 5, 2026

Performance metrics​

Metric	Value	Assessment
Compute utilization	>30%	Industrial grade (top overseas chips ~40%)
Key training operator efficiency	+14%	vs previous-gen 910B
Communication bandwidth utilization	>60% (est.)	MoE All-to-All communication
Stability	1,000 cards trained continuously with no failures	Cluster stability met standard

💡 About 30% compute utilization: many feel 30% is low, but in large-model training this is already a very respectable industrial-grade level. Even with the most advanced overseas chips, many teams' actual utilization is around 40%.

Ascend 910C detailed specs​

Ascend 910C is Huawei's AI training/inference chip announced at the Huawei Analyst Conference (April 24, 2024), with a theoretical peak of 800 TFLOPS (BF16), in the same class as NVIDIA H100.

Parameter	Ascend 910C	Ascend 910B	NVIDIA H100
Architecture	Ascend 910C	Ascend 910B	Hopper
Process	TSMC 7nm (est.)	TSMC 7nm	TSMC 4NP
BF16 compute	800 TFLOPS	256 TFLOPS	989 TFLOPS (sparse)
Memory	64GB HBM (est.)	64GB HBM2e (B1/B2)	80GB HBM3
Memory bandwidth	~2TB/s (est.)	600 GB/s (B1/B2)	3.35 TB/s
TDP	~400W (est.)	300-400W	700W
Mass production	April 2026 (full production)	Nov 2022	Mar 2022

Key upgrades:

• ✅ 3× compute: from 910B's 256 TFLOPS to 800 TFLOPS
• ✅ Mature software ecosystem: torch_npu adapts PyTorch, MindSpore framework mature
• ✅ Cluster stability: 1,000 cards trained continuously with no failures (the biggest breakthrough)

Technical challenges and solutions​

Challenge 1: Memory demand of trillion-scale models​

A 1.6-trillion-parameter model needs, just for model parameters:

• FP16: 1.6T × 2 bytes = 3.2 TB
• Plus gradients and optimizer states: at least 10 TB of memory

Huawei's solution:

• Model Parallel: distribute the model across 1,000 910C chips
• ZeRO optimizer: optimize memory footprint
• Gradient accumulation: update parameters in stages

Challenge 2: Communication efficiency of thousand-card clusters​

Training with 1,000 chips, inter-chip communication becomes the bottleneck. MoE models need All-to-All communication (each expert may need to communicate with all others).

Huawei's solution:

• HCCS (Huawei Collective Communication Scheduler): in-house high-speed interconnect protocol
• Layered communication: intra-node NVLink + inter-node HCCS
• Communication-compute overlap: data transfer concurrent with computation

Challenge 3: Training stability​

Trillion-scale model training takes weeks or months; any single card failure can interrupt the entire training.

Huawei's solution:

• Fault detection and auto-recovery: real-time monitoring of card status, auto-restart and recovery on failure
• Checkpoint optimization: high-frequency training-state saves (every N steps)
• Ascend cluster management software: designed specifically for enterprise training

Competitive comparison​

Vendor	Chip	1.6T-param training	Ecosystem maturity	Availability
Huawei	Ascend 910C	✅ Completed	⭐⭐⭐ (improving)	China-localized
NVIDIA	H100/H200	✅ Industry standard	⭐⭐⭐⭐⭐	Global (export-controlled)
AMD	MI300X	✅ Feasible	⭐⭐⭐⭐	Global
Google	TPU v5p/8t	✅ JAX-native	⭐⭐⭐⭐	Google Cloud

Conclusion: Ascend 910C has caught up to H100 in hardware performance, still lags in software ecosystem, but this training success proves engineering feasibility.

Industry impact​

1. The "Zunyi Conference" of domestic compute​

This breakthrough is called the "Zunyi Conference" of domestic compute — from passive defense to strategic counteroffensive.

Specific impact:

• ✅ Breaks the bias that "domestic chips can only do inference"
• ✅ Proves domestic chips can train frontier models
• ✅ Provides compute foundation for domestic large models (e.g., DeepSeek-V4, ERNIE 5.0)

2. Impact on NVIDIA​

Huawei Ascend 910C completing trillion-scale training means China's AI industry is less dependent on NVIDIA.

Scenario	Before	Now
Inference	Domestic chips usable	Domestic chips useful
Training	Must use H100/H200	Can use 910C
Large-scale training	Must use H100 clusters	Can use 910C clusters

3. Boost to the domestic chip industry​

This breakthrough will drive the entire domestic AI chip supply chain:

• Chip design: Cambricon, MetaX, Moore Threads accelerate iteration
• Wafer manufacturing: SMIC, Hua Hong get more orders
• Packaging/test: JCET, TFME benefit

Huawei Ascend roadmap (2025-2028)​

Time	Chip	Positioning
Q1 2025	Ascend 910C	Flagship training/inference (mass-produced)
Q1 2026	Ascend 950PR	Inference-optimized (~500 TFLOPS BF16)
Q4 2026	Ascend 950DT	Data-center training
Q4 2027	Ascend 960	Next-gen flagship
Q4 2028	Ascend 970	Next-next-gen

Training lessons shared​

The Shenzhen Hetao College team accumulated valuable experience:

✅ Successes​

1. Progressive training: start from small models (7B), gradually scale to 1.6T
2. Mixed-precision training: BF16 main + FP32 gradient accumulation
3. Communication optimization: All-to-All overlap with computation
4. Fault recovery: save checkpoint every 1,000 steps

⚠️ Challenges encountered​

1. Memory fragmentation: severe fragmentation over long training, needs periodic cleanup
2. Communication bottleneck: MoE All-to-All takes 30%+ of training time
3. Software bugs: torch_npu occasional memory leak, needs training process restart

Related chips​

• Huawei Ascend 910C - the chip used in this training
• Huawei Ascend 910B - previous-gen chip
• Huawei Ascend 950PR - next-gen inference chip
• NVIDIA H100 - benchmark product
• NVIDIA H200 - benchmark product (HBM3e upgrade)

References​

• Sina Finance: Huawei Ascend 910C completes DS-V4-Pro training
• Tencent News: Milestone! Ascend 910C completes 1.6-trillion-param model training
• 21IC: Huawei chip completes full-parameter post-training of 1.6T AI model

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This article is compiled from public reports. Salute to the teams at Shenzhen Hetao College, HIT (Shenzhen), and Huawei — you proved the feasibility of China's AI compute with engineering results.

On March 18, 2026, Intel officially launched at the Intel AI Summit: the Habana Gaudi 4 custom AI accelerator. This is Intel's latest-gen AI training/inference chip after Gaudi 3 (launched April 2024), designed for large-scale model training.

Meanwhile, Intel confirmed its next-gen Jaguar Shores GPU (datacenter GPU) is in development, will use HBM4 memory, and is expected in 2027. This marks Intel's formal return to the AI chip race.

Key Highlights​

• Gaudi 4: Launched March 2026, TSMC 5nm, 64GB HBM3e, for large-scale training
• Jaguar Shores: Launches 2027 (est.), HBM4, targeting NVIDIA Rubin
• Crescent Island: Intel's first general-purpose GPU (launched 2026), Xe3 architecture
• Software ecosystem: Intel AI Stack (including oneAPI, BigDL, Gaudi Software Suite)
• Foundry partners: TSMC (Gaudi 4, Jaguar Shores), Intel Foundry (Crescent Island)

Gaudi 4 Detailed Specs​

Gaudi 4 is the fourth-gen AI accelerator designed by Intel's Habana Labs (acquired 2019).

Parameter	Gaudi 4	Gaudi 3 (2024)	NVIDIA B200
Architecture	Habana 4	Habana 3	Blackwell
Process	TSMC 5nm	TSMC 7nm	TSMC 4NP
FP8 compute	~2,000 TFLOPS (est.)	1,000 TFLOPS	4,500 TFLOPS (sparse)
Memory	64GB HBM3e	128GB HBM2e (est.)	192GB HBM3e
Memory bandwidth	~3 TB/s (est.)	~2 TB/s (est.)	8 TB/s
TDP	~500W (est.)	~400W	700-1000W
Interconnect	RoCE v3 (Ethernet)	RoCE v2	NVLink 5.0
Launch	March 2026	April 2024	March 2024
Mass production	2026 Q3 (est.)	Q4 2024	Q4 2024

📌 Note: Gaudi 4 exact specs not fully public; some values above are estimates.

Gaudi 4 Key Features​

1. Native Ethernet support: Uses RoCE v3 (RDMA over Converged Ethernet), no dedicated interconnect protocol needed (like NVLink)
2. Large-scale scaling optimized: Ten-thousand-card cluster scaling efficiency better than InfiniBand (lower cost)
3. Sparsity acceleration: Native MoE model support
4. Multi-precision support: FP8/FP16/FP32/INT8/INT4
5. Open ecosystem: Supports PyTorch, TensorFlow, JAX (via third-party adaptation)

Jaguar Shores: Intel's Next-Gen GPU​

Jaguar Shores is Intel's first true datacenter GPU (not an ASIC like Gaudi).

Why "Jaguar Shores"?​

• Jaguar: Symbolizes "speed" and "agility"
• Shores: Symbolizes "openness" and "connection"

Jaguar Shores Estimated Specs​

Parameter	Jaguar Shores (est.)	NVIDIA Rubin	AMD MI455X
Architecture	Xeu 3 (est.)	Rubin	CDNA 4
Process	TSMC 3nm (est.)	TSMC 3nm	TSMC 3nm
Memory	HBM4 (confirmed)	HBM4	HBM4
Memory capacity	288GB (est.)	288GB	288GB
FP8 compute	~4,000 TFLOPS (est.)	~6,000 TFLOPS	6,000 TFLOPS
TDP	~800W (est.)	~1,000W	~800W
Launch	2027 (est.)	2026 Q3	2026 Q3

Key confirmations:

• ✅ HBM4 memory: Intel confirmed Jaguar Shores will use SK hynix HBM4
• ✅ TSMC foundry: Jaguar Shores will be produced by TSMC (not Intel Foundry)
• ✅ oneAPI native support: Jaguar Shores will natively support the oneAPI programming model

Crescent Island: Intel's First General-Purpose GPU​

Crescent Island is Intel's first general-purpose datacenter GPU announced October 2025, using the Xe3 architecture (upgrade of Xe-HPG).

Parameter	Crescent Island (est.)	Intel Data Center GPU Max	NVIDIA L40S
Architecture	Xeu 3	Xeu 2 (Ponte Vecchio)	Ada Lovelace
Positioning	General compute + AI inference	HPC + AI training	AI inference + graphics
Process	TSMC 5nm (est.)	Intel 7 + TSMC 5nm	TSMC 4N
Memory	48GB HBM3 (est.)	128GB HBM2e	48GB GDDR6
TDP	~300W (est.)	600W	350W
Launch	2026 (est.)	Jan 2023	Mar 2023

Positioning:

• ✅ General-purpose GPU: Both AI inference and scientific computing (HPC)
• ✅ Low cost: Cheaper than Gaudi 4, targeting NVIDIA L40S
• ✅ Open standards: Supports oneAPI, SYCL, Level Zero

Intel AI Chip Roadmap (2024-2027)​

Time	Product	Type	Process	Note
2024 Q4	Gaudi 3	AI ASIC	TSMC 7nm	Current mainstay
2026 Q2	Crescent Island	General GPU	TSMC 5nm	New launch
2026 Q3	Gaudi 4	AI ASIC	TSMC 5nm	New launch
2027	Jaguar Shores	Datacenter GPU	TSMC 3nm	Next-gen flagship
2027	Gaudi 5 (est.)	AI ASIC	TSMC 3nm	Next-gen

vs Competitors​

Gaudi 4 vs NVIDIA B200​

Metric	Gaudi 4	NVIDIA B200
FP8 compute	~2,000 TFLOPS	4,500 TFLOPS
Memory	64GB HBM3e	192GB HBM3e
Interconnect	Ethernet (RoCE v3)	NVLink 5.0
Software ecosystem	Gaudi Software Suite	CUDA
Price	est. ~$20,000	~$45,000
Advantage	Low Ethernet cost, open	Most mature ecosystem, strongest performance
Disadvantage	Weak software ecosystem, lower compute	Expensive

Conclusion: Gaudi 4 is positioned as a "cost-effective training solution," suited for cost-sensitive customers willing to invest in software adaptation.

Jaguar Shores vs NVIDIA Rubin​

Metric	Jaguar Shores (est.)	NVIDIA Rubin
FP8 compute	~4,000 TFLOPS	~6,000 TFLOPS
Memory	288GB HBM4	288GB HBM4
Software ecosystem	oneAPI	CUDA
Mass production	2027	2026 Q3
Advantage	Open standards, possibly cheaper	Mature ecosystem, first-mover advantage
Disadvantage	Weak ecosystem, 1 year late	Expensive

Conclusion: If Jaguar Shores launches on time with sufficient oneAPI ecosystem improvement, it can become NVIDIA's third choice (after NVIDIA and AMD).

Software Ecosystem: oneAPI Progress and Challenges​

What is oneAPI?​

oneAPI is Intel's open, cross-architecture programming model:

• Supports CPU, GPU, FPGA, AI accelerators
• Based on SYCL standard (similar to CUDA's C++ extensions)
• Open-source implementation (Intel oneAPI Base Toolkit)

Intel AI Stack​

Component	Purpose	Counterpart
oneAPI	Cross-architecture programming model	CUDA
BigDL	Distributed deep learning framework	PyTorch Distributed
Gaudi Software Suite	Gaudi-specific software stack	NVIDIA GPU Cloud (NGC)
Intel Extension for PyTorch	PyTorch optimization on Intel hardware	NVIDIA PyTorch
Intel Optimization for TensorFlow	TensorFlow optimization on Intel hardware	NVIDIA TensorFlow

✅ Progress​

• PyTorch 2.5+: Intel Extension integrated into PyTorch mainline
• Hugging Face Transformers: Official Intel GPU support (via optimum-intel)
• vLLM: Experimental Gaudi support (performance TBD)

⚠️ Challenges​

• Developer habits: Global AI developers use CUDA; oneAPI has a steep learning curve
• Operator coverage: Many PyTorch operators lack oneAPI-optimized versions
• Performance: At same power, Gaudi 4 performance is only ~50% of B200

Industry Impact​

1. Can Intel Return to the AI Race?​

Challenges:

• ❌ Ecosystem disadvantage: CUDA moat too deep, oneAPI hard to shake
• ❌ Performance disadvantage: Gaudi 4 only ~50% of B200
• ❌ Timing disadvantage: Jaguar Shores 1 year later than Rubin

Opportunities:

• ✅ Open standards: Not dependent on CUDA, suited for "anti-NVIDIA-monopoly" customers
• ✅ Ethernet advantage: RoCE v3 cheaper than InfiniBand at ten-thousand-card scale
• ✅ Intel Foundry: If Jaguar Shores uses Intel's own process, lower cost

2. Impact on AMD​

Intel's return to the AI race is bad for AMD:

• AMD was the "only NVIDIA alternative"
• Now Intel is back too; AMD's "alternative" status is challenged
• But in the short term (2026-2027), Intel cannot yet threaten AMD

3. Impact on Domestic Chips​

Intel Gaudi 4's launch is a reference case for domestic chips:

• Proves the Ethernet route (RoCE) is viable
• Proves open ecosystem (oneAPI) is hard but necessary
• Proves the cost-effective route has a market (cost-sensitive customers)

Related Chips​

• Intel Gaudi 3 - Previous-gen product
• Intel Gaudi 4 - New launch (to be created)
• Intel Crescent Island - Intel's first general GPU (to be created)
• NVIDIA B200 - Direct competitor
• AMD MI455X - Same-gen competitor

References​

• Intel Newsroom: Gaudi 4 Launch
• Tom's Hardware: Intel Jaguar Shores to use HBM4
• Wccftech: Intel Next-Gen Jaguar Shores GPU
• U.S. News: Intel Signals Return to AI Race

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This article is compiled from Intel official announcements and public materials. Some specs are estimates, subject to final Intel release.