On June 1, 2026, NVIDIA founder and CEO Jensen Huang officially announced at COMPUTEX 2026 (Taipei) that: the Vera Rubin platform has entered full production. This marks a fundamental paradigm shift for AI hardware from "discrete accelerators" to "integrated AI factories."

Key Highlights​

• Rubin GPU: Next-gen AI compute chip, FP4 compute is 3.6× that of Blackwell
• Vera CPU: 88 custom Arm cores (176 threads), replacing the Grace CPU
• NVLink 6: GPU-to-GPU interconnect bandwidth reaches 260 TB/s (double Blackwell)
• CX8 SuperNIC: 800Gb/s network, ConnectX-9 link reaching 28.8 TB/s
• HBM4 memory: 288GB per chip, 13 TB/s bandwidth
• Agentic throughput: 10× over Grace Blackwell

Complete Vera Rubin Platform Specs​

Vera Rubin is not a single GPU but a complete AI factory platform comprising 7 chips:

Rubin GPU Detailed Specs (estimated)​

📌 Note: Rubin's exact specs are not fully public yet; some values above are estimates.

Vera CPU: The New Host CPU Replacing Grace​

Vera CPU is NVIDIA's self-designed Arm-architecture CPU, replacing the previous Grace CPU:

Key upgrade: Vera's co-design with the Rubin GPU achieves end-to-end optimization in compute, data loading, and preprocessing, comparable to Google TPU 8t's Arm Axion integration.

Performance vs Blackwell​

NVIDIA officially claims that under the same POD configuration (144 GPU chips):

💡 Why "10× agentic throughput"? Agentic AI workloads differ from training/inference: one prompt may trigger multiple stages including reasoning, retrieval, tool calls, and response generation, involving thousands of steps. The Rubin platform is optimized for this long-chain, high-concurrency workload.

MGX Third-Gen Rack-Scale System​

Vera Rubin adopts the MGX third-gen open rack-scale system design:

• Five-rack synergy: Vera Rubin NVL72 system + Vera CPU + Groq 3 LPX + Vera BlueField-4 STX storage + Spectrum-6 SPX Ethernet
• Global supply chain: 30 countries, 350+ factories, hundreds of partners (Dell, HPE, Lenovo, Supermicro, Asus, Foxconn, etc.)
• Spectrum-X Ethernet silicon photonics: World's first switch based on CPO (co-packaged optics) supporting 200Gb/s SerDes, now in mass production

Mass Production Timeline​

AI Factory: From Selling Chips to Selling "Smart Production Lines"​

Huang said something at the launch that shook the industry:

"Rubin's Agentic AI throughput is 10× that of Blackwell. Rubin is a complete AI factory platform."

This marks a fundamental shift in NVIDIA's business model:

• Past: Sold GPUs (H100/B200), customers built systems themselves
• Now: Sells "complete AI factory solutions" (Vera Rubin POD), including GPU, CPU, network, storage, software stack
• Future: Becomes the "TSMC" of global AI infrastructure (providing smart production capacity)

vs Competitors​

Industry Impact​

1. AI labs: Frontier model training time shrinks from "months" to "weeks"
2. Cloud providers: Must decide whether to procure Vera Rubin POD (conflicts with self-developed chip strategy)
3. Hyperscale datacenters: AI factory becomes a new competitive dimension (whoever has the strongest compute can train the strongest model)
4. Domestic chips: Ascend 910C/950, Cambricon MLU590, etc. must catch up to Blackwell in 2026-2027, or the gap will widen to the Rubin era

Related Chips​

• NVIDIA Rubin R200 - Rubin architecture GPU detailed specs
• NVIDIA Vera CPU - Vera CPU detailed specs
• NVIDIA B200 - Previous-gen Blackwell architecture
• AMD MI455X - Direct competitor (MI400 series)

References​

• NVIDIA Blog: Vera Rubin Full Production
• COMPUTEX 2026 Keynote
• NVIDIA Official Newsroom

This article is compiled from NVIDIA official announcements and public materials. Some specs are estimates, subject to final official release.

In 2026, China's domestic AI chip industry has entered a period of full-scale explosion. The three giants — Huawei Ascend, Baidu Kunlun, and Alibaba T-Head — have successively launched next-generation products, while Cambricon, MetaX, Enflame, and Iluvatar have also achieved important breakthroughs.

This article comprehensively analyzes 2026 domestic AI chip progress across four dimensions: product launches, technology breakthroughs, market dynamics, and ecosystem building.

1. Huawei Ascend: 950 series launched, 960/970 roadmap clear​

1.1 Ascend 950PR (launched Q1 2026)​

Core specs:

Technology innovations:

• First adoption of Huawei in-house HBM solution (HiBL 1.0), lowering cost
• Supports FP8 low-precision compute, 3× inference energy-efficiency improvement
• Optimized for inference scenarios such as video recommendation and real-time interaction

Commercialization progress:

• Mass supply began in Q1 2026
• Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud
• Priced around ¥100,000/card (¥80,000 for key accounts), ~30% lower than comparable competitors

1.2 Ascend 950DT (launched Q4 2026)​

Core specs:

Technology innovations:

• Adopts HiZQ 2.0 memory technology, 2× data-movement efficiency
• Supports FP8/FP4 low-precision compute, balancing performance and efficiency
• Optimized for scenarios such as dialogue generation and large-model training

1.3 950 SuperNode (launched Q4 2026)​

System specs:

Performance comparison:

• 950 SuperNode outperforms NVIDIA's 2027 NVL576 system
• Leads by 20% in trillion-parameter model training

1.4 Ascend 960/970 roadmap​

Technology breakthroughs:

• Process upgrade: from N+2 (7nm-class) to N+3 (5nm-class)
• Memory capacity doubled: from 144GB (950DT) to 288GB (960/970)
• Energy efficiency improved: 960/970 are 30%+ better than 910C
• Precision optimized: 970 supports FP4 precision, optimized for next-gen AI architectures (MoE, etc.)

1.5 Commercialization progress​

Shipment data:

• 384-card SuperNode: over 500 units deployed, the only truly large-scale commercial SuperNode in China
• 2026 shipment target: 800k chips (1M cumulative)
• Market share: 60% of China's AI chip market

Ecosystem building:

• CANN compiler: open-sourced end of 2025, seamless PyTorch/TensorFlow migration
• Mind series toolchains: fully open, lowering the developer barrier
• Ecosystem partners: over 3,000
• Developer community: over 500k registered developers

2. Baidu Kunlun: M100 inference-specific, Tianchi SuperNode deployed​

2.1 Kunlun M100 (launched early 2026)​

Core specs:

Technology innovations:

• Adopts RISC-V open instruction set, adding 50+ AI-specific instructions
• Compute per watt reaches 8.3 TOPS/W, 2.1× the industry average
• Supports models from 10 billion to 100 billion parameters for inference

Commercialization progress:

• Mass supply in Q2 2026
• Key customers: Baidu Smart Cloud, China Merchants Bank, Southern Grid, Geely Auto
• Priced around ¥60,000/card, clear cost-performance advantage

2.2 Kunlun M300 (launched early 2027)​

Core specs:

Technology innovations:

• Adopts HBM4 memory, bandwidth up to 3.2 TB/s
• Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
• Native support for multimodal model training (text + image + video)

2.3 Tianchi 256-card SuperNode (launched June 2026)​

System specs:

Performance breakthroughs:

• Fully domestic SuperNode, fully autonomous and controllable from chip to network
• 97% effective training rate, surpassing NVIDIA DGX SuperPOD's 95%
• Training validation completed for Baidu ERNIE 5.1 and other key large models

2.4 Commercialization progress​

Shipment data:

• P800: 150k shipped in 2025, 200k target in 2026
• Ten-thousand-card clusters: multiple P800-based clusters delivered
• Market share: 20% of China's AI chip market

Customer coverage:

• External customer revenue share: over 50% in 2025
• China Mobile AI server procurement: P800-based bids won 70%, 70%, 100% shares
• Key customers: China Merchants Bank, Southern Grid, Geely Auto, iFlytek

IPO progress:

• May 2026: officially launched STAR Market IPO tutoring
• Plans "A+H" model — simultaneous A-share and Hong Kong listings
• Valuation exceeds ¥10 billion

3. Alibaba T-Head: M890 3× performance, Zhenwu series ships 560k units​

3.1 T-Head M890 (launched Q2 2026)​

Core specs:

Technology innovations:

• Adopts in-house ICN inter-chip protocol, inter-chip latency under 150 ns
• Companion PCCF communication library and ICN Switch chip enable full-bandwidth interconnect of 64 chips within a single node
• Supports FP8/FP4 low-precision compute, balancing performance and efficiency

3.2 T-Head V900 (launched Q3 2027)​

Core specs:

3.3 T-Head G900 (launched Q3 2028)​

Core specs:

3.4 Zhenwu series commercialization progress​

Shipment data:

• Cumulative shipments: over 560k units as of April 2026
• Customers served: 20+ industries, 400+ customers
• Autonomous driving: over 130k units, 30+ customers
• Finance: over 100k units, 150+ customers

Performance advantage:

• At equal precision, Zhenwu series single-machine inference outperforms comparable products by 50%+ on average
• Panjiu server SuperNode architecture supports trillion-parameter large models on a single node

Full product line:

• Zhenwu series AI chips: training + inference
• Yitian series CPUs: data center CPUs
• ICN Switch interconnect chip: inter-chip interconnect
• Camel920 400G smart NIC: high-speed networking
• Junyue series storage controller chips: storage optimization

4. Other domestic chip vendor progress​

4.1 Cambricon MLU590 (launched Q1 2026)​

Core specs:

Technology innovations:

• MLUarch 09 architecture, 2× compute over MLU590
• Supports FP8/FP4 low-precision compute, 2.5× inference energy-efficiency
• Native MoE architecture support, 3× sparse-model inference efficiency

Commercialization progress:

• Q1 2026: sample deliveries begun
• Key customers: Chinese government, state-owned enterprises, research institutes
• Day-0 adaptation of DeepSeek-V3 671B achieved

4.2 MetaX Xiyun C600 (launched Q2 2026)​

Core specs:

Technology innovations:

• MXMACA 3.0 architecture, CUDA-compatible, low migration cost
• Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
• Fully domestic supply chain, autonomous and controllable from chip to packaging

Commercialization progress:

• Q2 2026: sample deliveries begun
• Key customers: Chinese government, state-owned enterprises, research institutes
• Adapted models include LLaMA, ChatGLM, Baichuan

4.3 Enflame S60 (launched Q3 2026)​

Core specs:

Technology innovations:

• GCU 3.0 architecture, 2.5× inference performance over S30
• Supports FP8 low-precision compute, 3× inference energy-efficiency
• Hardware-level virtualization, single card split into 64 virtual instances

Commercialization progress:

• Q3 2026: sample deliveries begun
• Key customers: Tencent Cloud, China Telecom, China Unicom
• Priced around ¥50,000/card

4.4 Iluvatar VA10 (launched Q4 2026)​

Core specs:

Technology innovations:

• HVMA 2.0 architecture, 3× video processing performance over VA10
• Supports 8K real-time video processing, 2× video AI inference performance
• Hardware-level video codec, supports H.264/H.265/AV1

Commercialization progress:

• Q4 2026: sample deliveries begun
• Key customers: ByteDance, Kuaishou, Bilibili
• Priced around ¥40,000/card

4.5 Hygon DCU K100 (launched Q2 2026)​

Core specs:

Technology innovations:

• DCU architecture, x86-compatible, extremely low migration cost
• Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
• Fully domestic supply chain, autonomous and controllable from chip to packaging

Commercialization progress:

• Q2 2026: sample deliveries begun
• Key customers: Chinese government, state-owned enterprises, research institutes
• Adaptation of DeepSeek-V3 671B achieved

5. 2026 domestic AI chip market landscape​

5.1 Market share (2026)​

5.2 Technology roadmap comparison​

5.3 Supply chain security comparison​

6. 2026 domestic AI chip technology breakthroughs​

6.1 Process breakthroughs​

6.2 Packaging breakthroughs​

6.3 Memory breakthroughs​

6.4 Interconnect breakthroughs​

7. 2026 domestic AI chip ecosystem building​

7.1 Software ecosystem comparison​

7.2 Developer community building​

7.3 Large-model adaptation capability​

8. 2026 domestic AI chip market trends​

8.1 Market drivers​

8.2 Market challenges​

8.3 Market forecast (2026-2030)​

9. Summary and outlook​

9.1 Core conclusions​

1. 2026 marks the full-scale explosion of domestic AI chips, as the three giants Huawei Ascend, Baidu Kunlun, and Alibaba T-Head successively launch next-gen products
2. Significant technology breakthroughs across compute, memory, energy efficiency, and system scaling
3. Controllable supply chain security, fully autonomous from wafer fab to packaging and test
4. Accelerating ecosystem building, software ecosystem maturity reaching 60-70% of CUDA
5. Rising market share, domestic chips take 35% of China's AI chip market in 2026, projected 90% by 2030

9.2 Future outlook​

Short term (2026-2027):

• Huawei Ascend 950PR/950DT mass deployment, clear 960/970 roadmap
• Baidu Kunlun M100 inference chip ramps, M300 ultra-large multimodal training chip launches
• Alibaba T-Head M890 3× performance, V900 launches
• Domestic chip market share rises to 50%

Medium term (2028-2029):

• Huawei Ascend 960/970 mass production, 5nm process, 8 PFLOPS FP4 compute
• Baidu Kunlun M300 mass production, supports trillion-parameter multimodal training
• Alibaba T-Head G900 launches, becoming the next-gen compute flagship
• Domestic tech approaches international level, market share to 80%

Long term (2030+):

• Domestic AI chips exceed 20% of the global market
• Transition from "following" to "running alongside" to "leading"
• Huawei Ascend, Baidu Kunlun, Alibaba T-Head among the global TOP 5
• China becomes a global center of AI chip technology innovation

References​

1. Domestic AI chip "three powers" rise: substitution trend shifts from policy-driven to market-driven — Sohu
2. 2026 domestic AI chip panorama: Huawei Ascend races Cambricon — ZPEDU
3. Huawei unveils three-year Ascend AI chip roadmap — Jiemian News
4. Ascend 950PR chip — Baidu Baike
5. Ascend 950 chip — Baidu Baike
6. Kunlun P800: technical breakthroughs and application prospects of a new-generation AI accelerator — YunTECH
7. Kunlun P800 latest specs: P800 single-precision compute reaches 345 TFLOPS — Xueqiu

Last updated: June 10, 2026

Huawei Ascend 910C (Ascend 910C), Huawei's third-generation Ascend AI chip, adopts innovative dual-die (Chiplet) packaging and began mass supply in May 2025, becoming the backbone of domestic AI compute.

This article comprehensively analyzes this domestic flagship AI chip across four dimensions: technical specs, deployment cases, performance comparison, and market positioning.

1. Core Technical Specifications​

1.1 Chip architecture and process​

Technology highlights:

• Dual-die Chiplet packaging integrates two 910B chips, breaking the single-die yield bottleneck
• Centerless I/O die design lets the two compute dies interconnect directly, reducing communication latency
• SMIC N+2 process delivers 7nm-class performance with a controllable, autonomous supply chain

1.2 Compute performance​

Performance characteristics:

• 800 TFLOPS at BF16, a new domestic AI chip compute benchmark
• ~2× compute over 910B (dual-die stacking + architecture optimization)
• No FP8 precision support (NVIDIA Blackwell's strength)

1.3 Memory and interconnect​

Memory advantages:

• 128GB capacity supports full-pipeline training of hundred-billion-parameter models
• 784 GB/s is a high-end configuration among HBM2E solutions
• In-house AscendLink protocol supports 384-chip all-optical interconnect

1.4 Power and energy efficiency​

Energy efficiency advantages:

• At equal compute, significantly lower power than NVIDIA H100 (700W)
• 7nm-class process, ~30% better energy efficiency than 910B
• Suited to large-scale cluster deployment, reducing data center PUE pressure

2. Key Deployment Cases​

2.1 CloudMatrix 384 SuperNode​

System specs:

Performance comparison:

• CloudMatrix 384's total BF16 compute exceeds NVIDIA GB200 NVL72 (72× B200)
• In large-model training, 384-chip 910C linear scaling efficiency reaches 85%+
• Supports smooth scaling to ten-thousand-card clusters for ultra-large training

Deployment progress:

• As of June 2026, over 500 CloudMatrix 384 SuperNodes deployed
• Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud, iFlytek
• Scenarios: large-model training, smart customer service, autonomous-driving simulation, scientific computing

2.2 DeepSeek-V4-Pro full-parameter post-training​

Breakthrough significance:

On June 5, 2026, the AI training platform of Shenzhen Hetao College — together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and Shenzhen Zhicheng AI Compute Platform — completed full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model on an Ascend 910C compute cluster.

Technical highlights:

• Among the world's first to run full-parameter post-training of a trillion-parameter model on a domestic compute platform
• Validates Ascend 910C maturity in ultra-large-model training
• Proves domestic AI chips now have the capability to replace imported chips

Performance data (official disclosure):

• Training throughput: ~60% of an H100 cluster (BF16 precision)
• Memory utilization: 92% (128GB HBM2E capacity advantage)
• Interconnect efficiency: 384-chip linear scaling efficiency 85%+
• Stability: 30 consecutive days of training with no failures

2.3 Commercial deployment cases​

Case 1: A provincial big-data center (300 P FLOPS compute center)​

• Scale: 300 P FLOPS AI compute (~1,000× 910C)
• Scenarios: government large model, city brain, smart transportation
• Deployment: September 2025
• Investment: ~¥200M (120 servers)

Case 2: Huawei Cloud AI training platform​

• Chips: over 10,000 Ascend 910C
• Customers served: over 500 enterprises
• Model support: Pangu large model, third-party open-source models (LLaMA, ChatGLM, etc.)
• Global deployment: China, Southeast Asia, Middle East, Latin America

Case 3: iFlytek smart education​

• Scale: 256 Ascend 910C
• Scenarios: smart-education large model, speech recognition, machine translation
• Performance: 90% faster training than 910B

3. Performance Comparison Analysis​

3.1 vs. NVIDIA H100​

Conclusion:

• In raw compute, 910C is ~60% of H100
• In memory capacity, 910C leads by 60%, suited to large-model training
• In energy efficiency, 910C clearly outperforms H100
• In supply chain security, 910C wins outright

3.2 vs. Ascend 910B​

Conclusion:

• 910C's dual-die packaging doubles compute and memory capacity
• Yield up from 910B's 30% to 40%, lowering manufacturing cost
• At equal power, 100% performance gain, significantly better energy efficiency

3.3 Inference performance (DeepSeek measured)​

Test environment:

• Model: DeepSeek-V3 (671B parameters)
• Hardware: Ascend 910C vs NVIDIA H100
• Precision: BF16
• Batch size: 64

Results:

Conclusion:

• 910C inference speed is 60% of H100, but power only 44%
• In cost-sensitive scenarios, 910C's cost-performance advantage is clear
• For China-market localization needs, 910C is the only option

4. Market Positioning and Competitive Advantages​

4.1 Target markets​

Core markets:

1. Chinese government and SOEs: localization, data security, autonomy
2. Large-model startups: cost-sensitive, high compute demand
3. Operators and cloud providers: large-scale deployment, high efficiency requirements
4. Research and education: ultra-large-scale computing, talent development

Edge markets:

1. Autonomous driving: end-to-end large-model training
2. Smart healthcare: medical imaging, drug discovery
3. Fintech: risk control, robo-advisory

4.2 Competitive advantages​

4.3 Weaknesses and improvement directions​

5. 2026 Shipment Plan and Market Forecast​

5.1 Shipment plan​

Capacity bottleneck:

• SMIC N+2 capacity ~100k wafers/month, Ascend 910C ~30% of that
• 2026 plan of 800k chips needs ~400k wafers, requiring 80%+ utilization
• Huawei prioritizes 910C capacity via deep SMIC cooperation

5.2 Market forecast​

China AI chip market (2026):

• Total: ~¥50B
• Domestic share: ~35% (¥17.5B)
• Ascend 910C share: ~60% (¥10.5B, ~800k chips)

Global AI chip market (2026):

• Total: ~$200B
• Huawei share: ~5% ($10B)
• Growth drivers: China-market localization + Belt and Road exports

6. Summary and Outlook​

6.1 Core conclusions​

1. Ascend 910C is a milestone domestic AI chip, with comprehensive breakthroughs in compute, memory, energy efficiency, and system scaling
2. CloudMatrix 384 SuperNode proves domestic chips can replace imported ones
3. DeepSeek-V4-Pro training success validates 910C maturity in ultra-large-model training
4. 800k chips shipped in 2026, projected 60% of China's AI chip market

6.2 Future outlook​

Short term (2026-2027):

• 910C continues ramping, shipments exceed 1,000k
• CloudMatrix 384 deployments over 1,000 units
• Software ecosystem (CANN + MindSpore) maturity approaches 70% of CUDA

Medium term (2028-2029):

• Next-gen 910D mass production, 3nm process, target 1.6 PFLOPS BF16
• 950 series (PR/DT) becomes inference-market mainstay, share over 30%
• 960/970 launch, N+3 process, supports trillion-parameter models

Long term (2030+):

• Huawei Ascend series becomes TOP 3 of the global AI chip market
• Domestic AI chips exceed 20% of the global market
• Transition from "following" to "running alongside" to "leading"

References​

1. Huawei Ascend 910C — Baidu Baike
2. Huawei Ascend series AI chip detailed parameter comparison (2025-2028) — EET-China
3. Huawei Ascend 910C compute cluster powers domestic chip's successful trillion-scale AI large-model training — QQ News
4. Huawei Ascend 910C completes DeepSeek V4 Pro training — Huxiu
5. Huawei Ascend 910C measured efficiency surpasses H100, AI Infra software-hardware co-optimization shines at ten-thousand-card cluster — CNBlogs

Last updated: June 10, 2026

Kunlun P800 is Baidu's third-generation AI accelerator from Kunlunxin Technology, based on the in-house XPU-P architecture, with 345 TFLOPS peak FP16 compute (surpassing NVIDIA H20's 148 TFLOPS). Launched in March 2024, it has become an important force among domestic AI training/inference accelerators.

This article comprehensively analyzes this domestic AI chip's breakthroughs across five dimensions: performance data, architectural innovation, SuperNode deployment, large-model adaptation, and market positioning.

1. Core Performance Data​

1.1 Compute performance​

Performance characteristics:

• 345 TFLOPS at FP16, a new domestic AI chip compute benchmark
• 2.3× compute over NVIDIA H20 (H20 only 148 TFLOPS)
• Native MoE support, 4.3× sparse-model inference efficiency (with specific optimization)

1.2 Memory and bandwidth​

Memory advantages:

• 128GB capacity supports full-pipeline training of hundred-billion-parameter models
• 1.5 TB/s is a high-end configuration among HBM3e solutions
• 3D stacking alleviates large-model training memory bottlenecks

1.3 Power and energy efficiency​

Energy efficiency characteristics:

• At equal compute, significantly lower power than NVIDIA H100
• Dynamic power adjustment, auto-switching performance modes by load
• Suited to large-scale cluster deployment, reducing data center PUE pressure

1.4 Process and architecture​

Architectural innovation:

• Heterogeneous compute architecture, decoupling matrix-multiply units from tensor cores
• Parallel compute and data movement, theoretical compute 2.3× previous generation
• Hardware virtualization, single physical card divided into multiple logical cards, raising utilization

2. Three Architectural Innovations​

2.1 Heterogeneous compute architecture optimization​

Technology innovations:

• Matrix-multiply / tensor-core decoupling: parallelizes compute and data movement
• Dynamic task scheduling: auto-allocates compute by load
• Sparse compute optimization: native MoE support, 4.3× sparse-model inference efficiency

Performance gains:

• Theoretical compute 2.3× previous generation (Kunlun 2nd gen)
• 1.8× training throughput at equal power

2.2 3D-stacked memory technology​

Technology innovations:

• HBM3e memory with 3D stacking
• Single-card 128GB capacity, 1.5 TB/s bandwidth
• End-to-end ECC for data reliability

Performance gains:

• Alleviates large-model training memory bottleneck
• Supports full-pipeline training of hundred-billion-parameter models (no model-parallel splitting)
• 5× bandwidth vs GDDR6

2.3 Adaptive interconnect protocol​

Technology innovations:

• Dynamic die-to-die topology adjustment
• Built-in NPU for zero-copy data transfer, reducing CPU intervention
• ML-based congestion control, 30% lower packet loss than traditional ECN

Performance gains:

• In 256-node clusters, 40% lower communication latency
• Inter-chip bandwidth 1.2 TB/s (Tianchi 256-node)
• Smooth scaling to ten-thousand-card clusters

3. Tianchi SuperNode Deployment​

3.1 Tianchi 256-node​

System specs:

Core technology breakthroughs:

1. Interconnect bandwidth engineering:

   • Built-in NPU for zero-copy data transfer, reducing CPU intervention
   • Dynamic traffic scheduling: auto-adjusts routes by real-time link quality
   • Predictive congestion control: ML-based congestion algorithm

2. Virtualization resource utilization:

3.2 Tianchi 512-node​

System specs:

Core technology breakthroughs:

1. Ultra-large-scale training support:

   • Mixed-precision optimization: adds NF4 4-bit quantization on FP16/BF16, 75% less memory
   • Gradient checkpoint acceleration: reconstructs compute graph, activation storage O(n)→O(√n), 1.8× training speed
   • Failure recovery: distributed snapshot, 10× faster than traditional checkpoint

2. Communication efficiency optimization:

   • 3D parallelism (data + model + pipeline), compute/communication ratio 12:1
   • In 1.75-trillion-parameter MoE training, communication overhead below 15%

3.3 Tianchi series performance comparison​

4. Large-Model Adaptation​

4.1 DeepSeek series adaptation​

Certification:

• February 2025: passed DeepSeek-V3/R1 671B adaptation certification
• Supports single-machine 8-card full DeepSeek-V3 671B
• Supports DeepSeek MoE full-parameter training with just 32 machines

Performance data (DeepSeek-V3 671B):

Conclusion:

• P800 reaches 88% of H100 inference speed, gap significantly narrowed
• 83% of H100 training throughput
• 128GB large memory advantage clear, supports larger batch sizes

4.2 Other large-model adaptation​

CUDA compatibility:

• Models runnable on CUDA migrate to P800 at low cost
• Supports open-source inference frameworks such as vLLM
• ~14% of CUDA low-level communication code needs rewriting (sparse-model inference needs specific optimization)

4.3 Ten-thousand-card cluster validation​

Cluster scale:

• Fully in-house 30,000-card cluster deployed
• Smooth scaling to ten-thousand-card clusters
• Linear scaling efficiency 85%+ (thousand-card scale)

Stability data:

• 30 days continuous training with no failures
• Training resumes within 5 min of node failure
• Cluster availability 99.9%

5. Performance Comparison Analysis​

5.1 vs. NVIDIA H20​

Conclusion:

• In FP16 compute, P800 leads H20 2.3×
• In memory capacity, P800 leads 100%
• In HBM bandwidth, H20 leads 2.67×
• In supply chain security, P800 wins outright

5.2 vs. NVIDIA H100​

Conclusion:

• In raw compute, H100 leads P800 3.77×
• In energy efficiency, P800 clearly outperforms H100 (0.86 vs 1.86 TFLOPS/W)
• In actual inference performance, P800 reaches 88% of H100, gap significantly narrowed
• In cost, P800 is ~50% of H100

5.3 vs. Ascend 910C​

Conclusion:

• In FP16 compute, 910C leads P800 2.32×
• In HBM bandwidth, P800 leads 910C 91%
• In software ecosystem, both CUDA-compatible, similar migration cost
• In scenarios, P800 suits inference, 910C suits training

6. Market Positioning and Competitive Advantages​

6.1 Target markets​

Core markets:

1. Baidu Smart Cloud: core compute base of the Baige platform
2. China Telecom/Mobile/Unicom: won AI inference server procurement bids
3. Large-model startups: cost-sensitive, high compute demand
4. Intelligent compute centers: ten-thousand-card clusters validated

Edge markets:

1. Autonomous driving: end-to-end large-model training
2. Smart finance: risk control, robo-advisory
3. Smart healthcare: medical imaging, drug discovery

6.2 Competitive advantages​

6.3 Weaknesses and improvement directions​

7. 2026 Shipment Plan and Market Forecast​

7.1 Shipment plan​

Capacity bottleneck:

• Constrained by wafer fab capacity, supply falls short of demand
• 2026 plan of 200k chips, actual capacity ~150k
• Kunlunxin deepening cooperation with SMIC and Hua Hong to raise capacity

7.2 Market forecast​

China AI chip market (2026):

• Total: ~¥50B
• Domestic share: ~35% (¥17.5B)
• Kunlun P800 share: ~20% (¥3.5B, ~200k chips)

Global AI chip market (2026):

• Total: ~$200B
• Kunlun share: ~1% ($2B)
• Growth drivers: China-market localization + Belt and Road exports

8. Summary and Outlook​

8.1 Core conclusions​

1. Kunlun P800 is a major domestic AI chip breakthrough, leading comprehensively in FP16 compute, memory capacity, and energy efficiency
2. Tianchi 256/512 SuperNodes prove domestic chips can replace imported ones
3. DeepSeek-V3 671B adaptation success validates P800 maturity in large-model training/inference
4. 200k chips shipped in 2026, projected 20% of China's AI chip market

8.2 Future outlook​

Short term (2026-2027):

• P800 continues ramping, shipments exceed 500k
• Tianchi 512-node deployments over 100 units
• Software ecosystem (XPU-P + PaddlePaddle) maturity approaches 60% of CUDA

Medium term (2028-2029):

• Next-gen M300 mass production, 5nm process, target 700 TFLOPS FP16
• M100 (inference-specific) becomes inference-market mainstay, share over 15%
• Supports trillion-parameter model full-pipeline training

Long term (2030+):

• Kunlun series becomes TOP 5 of the global AI chip market
• Domestic AI chips exceed 15% of the global market
• Transition from "following" to "running alongside"

References​

1. Kunlun P800 parameters — CSDN Library
2. Kunlun P800: technical breakthroughs and application prospects of a new-generation AI accelerator — YunTECH
3. Kunlun P800 latest specs: P800 single-precision compute reaches 345 TFLOPS — Xueqiu
4. Exclusive: Kunlun — domestic AI card full DeepSeek training/inference adaptation — Kunlunxin official
5. Kunlun P800 detailed specs — MirrorFrog: https://www.mirrorfrog.com/en/docs/cards/others/kunlun-p800

Last updated: June 10, 2026

In 2026, the AI hardware market is undergoing a fundamental shift from the "training race" to "deployment as king." As large models move from technology demos to large-scale commercial deployment, hardware form factors, technology roadmaps, and the competitive landscape are undergoing systematic change.

Publisher: CSHIA Research (中智盟咨询) Author: Zhou Jun

Five Core Trends​

Trend 1: Shift in compute demand structure — inference becomes the main engine of growth​

The biggest change in the 2026 AI hardware market is the shift in the center of gravity of compute demand from training to inference.

According to market data:

• In 2026, global AI inference compute demand is expected to grow over 60% year-over-year
• Inference compute will exceed training compute for the first time, becoming the dominant workload of AI infrastructure

This shift stems from AI applications moving from "model development" into the "large-scale deployment" stage — enterprises no longer train large models frequently, but instead transform AI capability into real business value through high-frequency inference calls.

Key manifestations​

1. Inference chip market explosion: Shipments of dedicated inference chips (ASICs) are expected to grow 129%, with their share of AI servers rising from under 20% in 2025 to 27.8%.

2. Cost structure optimization: NVIDIA's Rubin platform reduces inference token cost to 1/10 of the previous generation, pushing inference applications from "luxury" to "commodity."

3. Workload characteristics change: Inference tasks show "high-frequency, long-pipeline, low-latency" characteristics, demanding higher real-time responsiveness from hardware.

Latest GTC 2026 developments (June 1, Taipei)​

NVIDIA CEO Jensen Huang announced several major inference compute advances at GTC 2026 Taipei:

• Vera Rubin platform enters full production: The NVL72 rack system delivers agentic throughput 10× that of the previous-generation Grace Blackwell, designed for Agentic AI
• Vera CPU officially launched: 88-core Armv9.2 custom Olympus architecture, highest single-thread IPC in the world, 1.5TB LPDDR5X memory, 1.2 TB/s bandwidth, native FP8 support
• RTX Spark AI PC chip: Co-developed with MediaTek (codename N1X), Blackwell-architecture GPU with 1 PFLOP AI compute, 128GB unified memory, TSMC 3nm, reshaping the Windows PC ecosystem
• AI Factory platform DSX: Four components — DSX Sim (digital-twin simulation), DSX OS (resource orchestration), DSX MaxLPS (power optimization), DSX Flex (grid coordination)

This trend means the competitive focus for hardware vendors is no longer "peak single-card compute" but "inference energy efficiency" and "system-level optimization capability."

Trend 2: Edge and on-device AI — the scaled deployment of compute moving downstream​

2026 is the pivotal year for edge AI hardware moving from proof-of-concept to scaled deployment.

As cloud inference cost pressure rises and privacy compliance requirements tighten, compute is accelerating its migration toward data sources, spawning explosive growth in hardware form factors such as edge servers, AI terminals, and smart devices.

Three deployment scenarios​

Technology breakthroughs​

1. On-device model compression: Through quantization, distillation and other techniques, models with tens of billions of parameters are compressed to run on-device.

2. Heterogeneous compute architecture: CPU+NPU+GPU coordination maximizes performance under power constraints.

3. Memory bandwidth optimization: Application of HBM technology in edge chips alleviates the "memory wall" problem.

The edge AI explosion means hardware design must balance "performance density" with "power efficiency," and traditional general-purpose chips face specialization challenges.

Trend 3: Dedicated chips and heterogeneous computing — breaking the monopoly of a single architecture​

In 2026 the AI chip market will show a "one superpower, many strong players, a hundred flowers blooming" competitive landscape.

Although NVIDIA maintains its advantage in training, in segmented markets such as inference, edge, and specific scenarios, dedicated chips (ASICs) and heterogeneous computing solutions are rising rapidly.

Major technology roadmap comparison​

Market landscape changes​

1. Domestic substitution accelerates: China's AI chip vendors raise their share in inference, edge and other scenarios to over 30%.

2. Open-source ecosystem rises: Open-source frameworks such as ROCm and OpenML lower the barrier to dedicated-chip development.

3. Chiplet technology popularizes: Integrating chips of different process nodes through advanced packaging achieves a balance of performance and cost.

4. GTC 2026 new products accelerate deployment (June 1, Taipei):

   • Vera Rubin platform: NVL72 rack system, agentic throughput 10× Grace Blackwell
   • Vera CPU: 88-core Olympus custom architecture, designed for Agentic AI low latency
   • RTX Spark: In partnership with MediaTek and Microsoft, reshaping the Windows PC ecosystem, 1 PFLOP AI compute
   • Nemotron 3 Ultra: SSM+MoE hybrid architecture, 5× faster inference, 30% lower cost

The core logic of this trend is: no single chip can dominate all AI scenarios; scenario fragmentation spawns technology-roadmap diversification.

Trend 4: Energy efficiency and thermal management — from technical challenge to business bottleneck​

As AI chip power consumption breaks the kilowatt level (NVIDIA Rubin GPU reaches 2300W), energy efficiency and thermal management have been upgraded from "supporting technology" to "core bottleneck."

In 2026, single-cabinet power density will exceed 240kW, traditional air cooling completely fails, and liquid cooling changes from "optional" to "mandatory."

Key data​

• Power cost share: The share of power cost in AI data center operating cost rises from 15% to 35%
• Thermal value increases: A single GB300 server's liquid-cooling components are worth about $50,000, 15-20% of hardware cost
• PUE optimization: Liquid-cooled data centers can bring PUE down to under 1.1, but upfront investment rises 30%

Technology evolution directions​

1. Tiered liquid cooling: Cold-plate (mainstream), immersion (high density), two-phase cooling (frontier)

2. Power architecture upgrade: From 12V to 48V/800V high-voltage DC, reducing conversion losses

3. Intelligent thermal management: AI predictive cooling, dynamically adjusting cooling strategy based on load

This trend means a hardware vendor's competitiveness depends not only on chip performance but more on "system-level energy efficiency optimization capability"; the importance of supporting technologies such as thermal management, power delivery, and cabinet design rises substantially.

Trend 5: AI-native hardware ecosystem — from "compatibility" to "reconstruction"​

In 2026, AI hardware is undergoing a paradigm shift from "adapting to AI" to "built for AI."

Traditional general-purpose hardware architectures struggle to meet the unique demands of AI workloads, spurring the rise of AI-native hardware design philosophy.

Three reconstruction directions​

1. Compute architecture reconstruction​

• Memory hierarchy optimization: HBM4 memory bandwidth breaks 3TB/s, compute-in-memory architecture reduces data movement
• Interconnect upgrade: NVLink 6.0 reaches 1.8TB/s bandwidth, supporting direct GPU-to-GPU communication
• Heterogeneous integration: Through advanced packaging, CPU, GPU and memory are stacked to boost bandwidth and reduce latency

2. Software-defined hardware​

• Reconfigurable logic: FPGA and DPU support dynamic algorithm loading, adapting to different AI models
• Compiler optimization: AI compilers (e.g., MLIR) automatically optimize hardware resource allocation
• Hardware abstraction layer: Unified programming interfaces shield underlying hardware differences

3. Ecosystem co-evolution​

• Model-hardware co-design: Large-model architectures account for hardware constraints (e.g., sparsification, quantization)
• Open-source hardware design: Application of RISC-V in AI chips lowers the development barrier
• Vertical integration: Cloud vendors' self-developed chips (e.g., AWS Graviton, Google TPU), software-hardware co-optimization

The essence of this trend is: the characteristics of AI workloads (matrix operations, high parallelism, memory sensitivity) are redefining hardware design principles, and the universality advantage of traditional x86 architecture is weakened in AI scenarios.

Key Conclusions and Outlook​

1. The five trends are interconnected and mutually reinforcing​

The inference demand explosion drives edge deployment, edge scenarios spawn dedicated chips, high power consumption forces an energy-efficiency revolution, and all changes ultimately point to the reconstruction of the AI-native hardware ecosystem.

The core driver of this round of change is AI moving from "technology demo" to "commercial deployment"; hardware must satisfy the industry requirements of "scale, low cost, high reliability."

2. Opportunity windows for industry participants​

For industry participants, the opportunities in 2026 lie in:

• ✅ Capture the inference dividend: Deploy inference-specific chips and system optimization
• ✅ Deepen vertical scenarios: Customize hardware solutions for specific industries/applications
• ✅ Break the energy-efficiency bottleneck: Liquid cooling, high-voltage DC, AI thermal management and other technologies
• ✅ Build an open ecosystem: Open-source frameworks, open standards, cross-industry collaboration

Vendors that can provide "end-to-end solutions" rather than "single-point chips" will gain an advantageous position in this reshuffle.

3. Dynamic adjustment and continuous evolution​

The above analysis is based on early-2026 market data and industry forecasts; actual development may adjust dynamically due to factors such as technology breakthroughs, policy adjustments, and market demand changes.

Industry Implications​

2026 is a watershed year for the AI hardware industry:

• From "compute race" to "deployment as king"
• From "single-point breakthroughs" to "system optimization"
• From "general-purpose architecture" to "dedicated customization"
• From "performance first" to "energy efficiency balance"

Vendors that can keenly capture trends, rapidly adjust strategy, and sustain technological innovation will seize the initiative in the AI hardware "era of deployment."

References:

• CSHIA Research, "2026 AI Hardware: Five Transformations and the Rules for Survival"
• "AI Hardware Enters the 'Era of Deployment'," Sohu Tech, February 10, 2026

June 6, 2026 — COMPUTEX 2026 concluded yesterday in Taipei. Under the theme "AI Together," this year's event set records with 1,500+ exhibitors and 6,000 booths. The head-to-head battle between NVIDIA, Intel, and AMD in the AI PC space was the defining story of the show.

1. NVIDIA RTX Spark: June Launch at $1,399​

Less than a week after its COMPUTEX debut, the NVIDIA-MediaTek RTX Spark Superchip confirmed its commercial timeline:

Market Reaction: AMD, Intel, and Qualcomm shares fell following the announcement. Analysts believe RTX Spark will reshape the market across three fronts — Windows AI PCs, creator workstations, and edge inference nodes.

2. Intel 18A in Full Production: Clearwater Forest + Crescent Island​

Intel CEO Lip-Bu Tan delivered his first COMPUTEX keynote with two key updates:

Clearwater Forest (Xeon 6+)​

• 288 cores, Darkmont architecture
• First Intel 18A process node data center CPU
• Foveros Direct 3D packaging
• Now in full production

Crescent Island AI GPU​

• 480 GB LPDDR5x memory
• 350 W air-cooled PCIe form factor
• Native FP4 support, targeting agentic inference
• Shipping H2 2026

"As AI moves into the agentic era, the CPU returns to the center of modern AI infrastructure." — Lip-Bu Tan

3. AMD Ryzen AI 400 Series Now Shipping​

AMD showcased the Ryzen AI 400 series (Zen 5 + Zen 5C hybrid + XDNA2 NPU) at COMPUTEX:

• NPU performance: 60 TOPS, the highest in x86
• 7 consumer SKUs + commercial PRO series
• Multiple OEM models already available or launching soon
• Advancing AI 2026 summit set for July in San Francisco

4. Chinese Domestic Chips Gaining Momentum​

5. The AI PC Era: Three-Way Roadmap Comparison​

This Week in AI Compute (6/1 – 6/6)​

Sources: COMPUTEX Daily, Tencent News, Phoenix Technology, Xueqiu, The Silicon Review.

June 1-5, 2026, Taipei — Computex 2026 (Taipei International Information Technology Show) wrapped up successfully this week. With the theme "AI Together," industry giants including NVIDIA, Intel, AMD, and Qualcomm unveiled numerous AI compute products in rapid succession. Below, MirrorFrog brings you a roundup of the most noteworthy developments in the compute card space this week.

① NVIDIA DGX Station for Windows: A Desktop AI Supercomputer​

NVIDIA officially launched the DGX Station for Windows during its Computex 2026 keynote, calling it "the world's most powerful desktop AI supercomputer."

Core Specifications​

Significance: DGX Station compresses AI compute power (20 PFLOPS FP4) that previously required datacenter-class clusters into a single desktop workstation. 748GB of unified memory means developers can run models with hundreds of billions or even trillions of parameters locally, without cloud dependency.

② Intel Crescent Island: Inference-Specialized AI GPU​

At Computex, Intel disclosed detailed specifications for its next-generation datacenter AI inference GPU, Crescent Island.

Significance: Crescent Island represents Intel's key strategic move in the AI inference market. 480GB of massive LPDDR5x memory (non-HBM) means significantly lower cost compared to NVIDIA H200/B200 and other competing products, targeting enterprise inference deployment scenarios.

③ Intel Xeon 6+ (Clearwater Forest): First Intel 18A Datacenter CPU​

Intel also unveiled the new Xeon 6+ processor, codenamed Clearwater Forest, its first datacenter CPU built on the 18A process:

• 288 Darkmont architecture cores
• L2 288MB + L3 576MB cache
• 12-channel DDR5-8000 memory
• Foveros Direct 3D advanced packaging
• AI Agent Era: CPU returns to the center of infrastructure

④ NVIDIA RTX Spark Ecosystem Takes Shape​

This week, the RTX Spark super chip developed in collaboration between NVIDIA and MediaTek continued to generate buzz. Multiple OEMs showcased RTX Spark-based laptop and compact desktop prototypes:

• ASUS, Dell, HP, Lenovo, Microsoft Surface, MSI all confirmed as launch partners
• Equipped with 20-core Grace CPU + Blackwell GPU (6144 CUDA cores)
• AI compute 1 PFLOPS
• Retail availability Fall 2026

⑤ Intel × Foxconn AI Infrastructure Partnership​

Intel and Foxconn announced a joint AI infrastructure initiative, covering the complete chain from chip → server → rack-scale system, targeting the datacenter market opportunity driven by surging AI inference demand.

⑥ Domestic AI Chip Developments​

According to the IDC 2025 annual report, total AI accelerator card shipments in China reached approximately 4 million units, with domestic vendors shipping approximately 1.65 million units, capturing a market share exceeding 41%. Huawei's Ascend 950 series has entered mass production and delivery, while Cambricon's MLU690 has begun shipping to internet customers.

This Week's Compute Roundup​

Sources: NVIDIA GTC Taipei 2026 / Computex 2026 official announcements, Intel press releases, ifeng Tech, IT Home.

June 2026 — Huawei's Ascend 950 series (950PR / 950DT) has entered formal mass production and delivery, a landmark event for China's AI chip industry in 2026. Meanwhile, Cambricon's MLU690 has begun shipping and Moore Threads has announced MTT S5000 specifications, formally establishing China's tri-polar AI chip landscape.

Ascend 950 Series: A Historic Breakthrough with Self-Developed HBM​

Huawei HiSilicon's Ascend 950 series is the fourth-generation Ascend AI chip, first revealed at Huawei Connect 2025 in September and entering mass production in Q1 2026.

950PR (Prefill Inference Specialized)​

950DT (Decode + Training Specialized)​

Historical Significance​

Self-developed HBM (HiBL 1.0 / HiZQ 2.0) represents the most important technical breakthrough of Huawei Ascend 950 — this is the first time a Chinese enterprise has achieved self-developed mass production of HBM memory, completely eliminating dependence on SK Hynix / Samsung HBM supply. Combined with the domestic N+2 process, Ascend 950 has achieved full-chain domestic production from HBM → Compute Die → Packaging → System.

Cambricon MLU690: China's Only Native FP8 Support​

Cambricon's seventh-generation AI chip MLU 690 (Siyuan 690) began volume production and shipping in H1 2026. This is the first domestic AI chip with native FP8 precision support.

MLU 690's FP8 compute power (2 PFLOPS dense) is on paper comparable to NVIDIA Blackwell (B200 FP8 4.5 PFLOPS sparse). Leveraging its financing advantage as a STAR Market listed company, Cambricon targets 2026 revenue of ¥15-20B (2025: ¥7.2B).

Moore Threads MTT S5000: From Graphics to Training-Inference Unified​

Moore Threads publicly disclosed detailed specifications of the MTT S5000 in February 2026, featuring the fourth-generation MUSA "Pinghu" architecture, single-card AI compute of 1,000 TFLOPS, 80GB GDDR6X memory, 1.6 TB/s bandwidth.

Moore Threads pursues a full-function GPU path (graphics rendering + AI compute + general-purpose compute), closest to NVIDIA's strategy. The founding team comes from former NVIDIA China, and the MUSIFY toolchain helps auto-migrate CUDA code to the MUSA platform, lowering ecosystem migration costs.

China's Tri-Polar AI Chip Landscape​

Global Market Comparison (Q2 2026 Update)​

Note: NVIDIA uses sparse compute as standard, while AMD / Huawei / Cambricon use dense — not directly comparable.

Outlook for H2 2026​

• NVIDIA Rubin R200: Official shipment in H2 2026, 288GB HBM4, 6-chip CoWoS-L packaging
• Huawei Ascend 960: Roadmap H2 2027, expected FP8 compute doubled to 2 PFLOPS
• Cambricon MLU790: Expected 2027, 3nm, 384GB HBM4, 2.5 PFLOPS
• Moore Threads: Next-gen GPU expected with HBM3, 2× MTT S5000 compute

By 2026, China's AI chip industry has formed a complete product matrix from Training (Cambricon MLU690 / Ascend 950DT) → Inference (Ascend 950PR / Moore Threads S5000) → Systems (CloudMatrix / Distributed Clusters).

This article is based on public information from Huawei Connect 2025 (2025-09-18), industry analysis reports from April 2026, and the latest market data as of June 2026.

2026 H2 is the richest era for the AI compute market: NVIDIA Rubin R200, AMD MI400, Trainium 3, TPU 8t/8i, Ascend 920, and Groq 3 LPX are all in place. This article provides a complete selection tree to help you choose the most suitable product based on model size, training/inference, latency requirements, budget, and region.

On May 29, 2026, during the World Intelligence Expo 2026 in Tianjin, the China Intelligent Computing Industry Alliance, National Supercomputing Center in Tianjin, Tianjin Artificial Intelligence Society, Shenzhen Artificial Intelligence Industry Association,ZDNET, and ZDNET ThinkTank jointly released the "2026 Global AI Computing Development Research Report."

The report analyzes the current state and future trends of the global AI computing industry, revealing that the sector has entered a new stage of "intelligence-driven, system-reconstruction."

Core Viewpoints​

1. Computing power becomes a national strategic element​

The global computing industry is entering a new stage of "intelligence-driven, system-reconstruction." With the rise of the "token economy," computing power has become a key foundational element supporting national technological breakthroughs, industrial competition, and strategic positioning.

Computing is evolving from traditional IT support into a strategic bedrock driving scientific innovation and the industrial revolution.

2. AI computing development covers the full chain​

AI computing development must upgrade the full chain of chip, system, and compute cluster, while matching the differentiated computing needs of model training, inference, and data preparation.

• Training: pre-training of super-large models needs ten-thousand-card-scale compute
• Inference: super-large models need thousand-card-scale compute
• Data preparation: needs tens to hundreds of cards

Compute demand at both training and inference ends will keep growing.

3. Domestic AI chip industry's distinctive path​

The domestic AI chip industry follows a route of "autonomy + cluster breakthrough + hardware-software integration + cost-performance advantage," distinct from the foreign pursuit of absolute single-chip compute — better suited to large-scale deployment.

4. Energy challenges for computing centers and solutions​

Computing centers have become the fastest-growing source of global electricity demand. The future requires a diversified energy supply of "short-term wind-solar-storage integration, mid-term nuclear, long-term hydrogen."

Meanwhile, space computing will become a new direction to solve ground-based computing bottlenecks.

5. Compute-network convergence as a core direction​

Future computing will move toward "compute-network convergence," making compute as on-demand as water and electricity — a core part of the national modern infrastructure system.

The computing network has been included in the national "15th Five-Year Plan" major engineering projects, ranked alongside public infrastructure such as hydro power.

Key Data​

Compute performance evolution​

Global computing center capacity & energy forecast​

• Global computing center total capacity: expected to grow from 102GW (2026) to 220GW (2030)

  • AI load capacity from 62GW to 156GW, share rising to 71%

• U.S. computing center annual electricity: expected to grow from 292TWh to 606TWh, share of national demand rising to 11%

• China computing center total capacity: ~60GW by 2030, AI load share rising to 48%

• Global computing center electricity: per IEA base scenario, from ~415TWh (2024) to ~945TWh (2030), ~15% CAGR

Embodied intelligence compute support data​

• Cloud compute: can generate PB-scale interaction data daily; large-model training cycle shortened from months to weeks
• Edge compute: tens-to-hundreds of TOPS enables 10–50ms low-latency real-time perception & decision

Industry Trend Analysis​

Computing technology architecture trends​

1. Heterogeneous architecture upgrade​

From traditional CPU+GPU to a new GPU+LPU+CPU+DPU heterogeneous inference architecture.

CPU plays the core role of task scheduling, data pre-processing, serial tasks, and system interconnection in heterogeneous architectures. In 2010, "Tianhe-1A" pioneered large-scale CPU+GPU deployment, leading the global intelligent-computing underlying architecture direction.

2. Clear scale-up / scale-out paths​

• Scale Up: pursue extreme performance by raising single-node hardware config
• Scale Out: add nodes for load sharing and high availability

Together they form the core support of computing system capability.

3. Super-node servers become mainstream​

With ultra-high interconnect bandwidth and low communication latency, they shorten model training cycles.

Representative products:

• Huawei Ascend 384 super-node
• Sugon scaleX640 super-node
• Alibaba Cloud Panjiu AL128 super-node
• Inspur YuanNao SD200
• Kunlunxin super-node solution

4. Long-context processing optimization​

Through Compressed Sparse Attention (CSA), Heavy-Compressed Attention (HCA) and sliding-window mechanisms, build a "coarse + fine, sparse + dense" long-context modeling system to improve compute efficiency.

Representative application: DeepSeek-V4 attention architecture design.

AI computing key-domain trends​

AI chips​

International vendors:

• NVIDIA: leads high-end training/inference with Blackwell and Rubin architectures
  • GTC 2026 Taipei (June 1) major releases:
    • Vera Rubin platform in full mass production: NVL72 rack system, agent throughput 10x over Grace Blackwell
    • Vera CPU released: 88-core Olympus in-house Armv9.2, LPDDR5X 1.5TB, 1.2 TB/s, world's first CPU with native FP8
    • RTX Spark AI PC chip: co-developed with MediaTek and Microsoft (codename N1X), Blackwell GPU 1 PFLOP, 128GB unified memory, TSMC 3nm
    • Nemotron 3 Ultra open model: SSM+MoE hybrid, 5x inference speed, 30% lower cost
  • Expanding advantage via CUDA ecosystem
• Google: deepens vertical HW/SW integration via in-house TPU
• AWS: Trainium (training) + Inferentia (inference) for cost-effective cloud compute

Domestic vendors: a product matrix represented by Huawei Ascend 910C, Kunlunxin P800, Moore Threads MTT S5000, MetaX XiYun C600.

In 2026 Huawei proposed the "Tao (τ) Law," aiming to systematically reduce the time constant and raise transistor density via logic folding, driving domestic chip evolution.

AI workstations​

• Form factors: tower, mobile, mini — for different deployment scenarios
• Compute tiers: entry, professional, enterprise — covering personal dev to enterprise deployment

AI servers​

• By function: training AI servers and inference AI servers
• By deployment: cloud AI servers and edge AI servers

With high compute output, high memory bandwidth, and high-speed interconnect, suited to large-scale parallel tasks.

AI computing centers​

• Trending toward "high AI share, high power density, high electricity consumption"
• Ultra-large AI computing centers become the construction focus
• Energy supply moving toward diversified clean sources

Space computing is a new direction, leveraging space's continuous sunlight, extreme cold/vacuum, and interference-free environment to solve ground centers' energy, cooling, and interconnect bottlenecks. Starcloud and Guoxing Weiyu have begun exploration.

Computing application-scenario trends​

1. Scientific research paradigm shift​

The "dry-wet closed loop" research paradigm becomes mainstream, forming a loop between AI-driven "dry experiments" and automated "wet experiments" via data feedback — shifting science from experience-driven to model-driven.

2. Synthetic biology empowerment​

AI's multi-task learning and unknown-space exploration can decode biology's complex "sequence–structure–function" mapping, enabling breakthroughs in protein synthesis, gene editing, and nucleic-acid vaccines. E.g., the AlphaFold series revolutionized protein structure prediction.

3. Embodied intelligence support​

Efficient cloud-edge compute coordination provides full-stack support for embodied intelligence — covering massive data processing, high-fidelity simulation, model training, and edge real-time perception/decision in a closed loop.

Computing infrastructure trends​

Compute-network convergence is the core direction, evolving from "interconnect first, then network" toward a national integrated computing network. The three major telecom operators have begun interconnecting their own compute with dispersed social compute nationwide, promoting ubiquitous compute supply.

Industry ecosystem trends​

The domestic computing ecosystem keeps improving, with deeper government-industry-academia-research coordination. The China Intelligent Computing Industry Alliance, National Supercomputing Center in Tianjin, regional AI societies, industry associations, and service institutions jointly build exchange platforms — driving R&D, standard-setting, technology transfer, and talent cultivation for high-quality domestic computing development.

Conclusions & Outlook​

1. Computing power is a core element of national strategic competitiveness — major countries are increasing infrastructure investment to seize the AI-era high ground.
2. The domestic AI chip industry follows a distinctive path — via cluster breakthrough, HW/SW integration, and cost-performance, forming advantage in large-scale deployment.
3. Computing architecture keeps evolving — heterogeneous computing, super-node servers, and long-context processing are key directions.
4. Application scenarios keep expanding — from research paradigm shifts to synthetic biology and embodied intelligence, AI compute deeply empowers frontier fields.
5. Computing infrastructure evolves toward compute-network convergence — future compute will be ubiquitous public infrastructure, on-demand like water and electricity.

References:

• "2026 Global AI Computing Development Research Report" (China Intelligent Computing Industry Alliance et al.)
• World Intelligence Expo 2026 (Tianjin, May 29, 2026)