8 月底至 9 月初，国产 AI 芯片厂商半年报密集披露，加上燧原科技 9 月 2 日启动 IPO 申购，被称为"国产四小龙"的摩尔线程、沐曦、壁仞、燧原全部完成上市，加上早已在科创板的寒武纪——国产 AI 芯片的资本市场拼图就此补齐。更重要的是，财报数字第一次集体印证了一件事：国产算力正从"能用"跨向"好用"，商业化拐点已现。

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1. 半年报成绩单：增长是主旋律，盈利是分水岭​

厂商	2026H1 营收	同比	盈利状态	技术路线
寒武纪	59.96 亿元	+108.1%	归母净利 23.11 亿	自研 MLU 指令集（DSA）
摩尔线程	17.36 亿元	+147.4%	净亏 1156 万（收窄）	全功能 GPU（兼容 CUDA 路线）
壁仞科技	12.36 亿元	+1997.6%	未盈利	通用 GPU
沐曦	13.24 亿元	+44.7%	净利 6.12 亿（首次扭亏）	通用 GPU
燧原	11.20 亿元	+279.1%	未盈利	DSA 专用架构（TopsRider）

几个值得注意的细节：

• 沐曦率先跨过盈利线：8 月 31 日披露的半年报显示净利润 6.12 亿元、同比扭亏（上年同期亏损 1.86 亿）；不过扣非净利润仍为 -4900 万（亏损收窄 75.8%）——含金量仍在爬坡。
• 壁仞低基数暴增：近 20 倍的同比增速来自上年同期极低的收入基数，但 12.36 亿的绝对体量已与燧原、沐曦同量级，第二梯队座次重新洗牌。
• 研发强度惊人：沐曦研发费用占营收 39.7%、摩尔线程 44.3%、壁仞高达 65%——高研发投入是全员未完全盈利的根本原因，也是未来竞争力的来源。
• 摩尔线程毛利率承压：从 78% 降至 57%，成本增速（+245%）远超营收增速（+147%）——大规模量产期的品控与爬坡成本开始显现。

2. 燧原登板：四小龙资本拼图补齐​

燧原科技 9 月 2 日启动公开申购，发行 4303 万股新股（约占上市后总股本 10%），募资目标 60 亿元，采用 DSA 专用架构 + 自研 TopsRider 软件平台（不兼容 CUDA）。至此：

• 科创板：寒武纪（2020 年）、摩尔线程、沐曦、壁仞（2026 年）
• 燧原：2026 年 9 月完成上市

国产 AI 芯片第一梯队全部进入公开市场，融资通道打开后，研发投入的"军备竞赛"将进一步升级。

3. 需求端：百万卡缺口，订单排到三年后​

财报爆发的另一面，是需求端的极度饥渴：

• 产能缺口：行业调研显示，2026 年国产 AI 芯片需求规模约 400 万颗，实际交付约 300 万颗，存在百万级缺口；
• 订单周期：内蒙古乌兰察布远景星河基地（规划支撑百万卡级并行算力）表示"在手订单已排到三年后"；
• 供给创新：算力紧缺催生"集装箱式算力中心"——20/40 英尺标准集装箱为载体，插电接水即可在 24 小时内完成部署，把传统"一年工期"压缩到"一天上线"；
• 市场空间：IDC 数据显示 2025 年中国 AI 加速卡出货约 400 万片，国产占约 41%（165 万片）；CIC 预测中国 AI 加速器市场 2028 年将超万亿元，其中国产方案份额约 90%。

4. 两种路线的两种赌注​

市场研究机构预测 2026 年中国高端 AI 芯片市场中，国产方案份额将接近 90%，其中华为约 62%、寒武纪约 14%，剩余由摩尔线程、沐曦、壁仞等共同占据。而寒武纪与摩尔线程这对"双龙头"，正在押注两种截然不同的未来：

寒武纪：用现金买确定性。 半年报资产负债表上，存货 82.48 亿 + 预付款 29.14 亿，两项合计 111.6 亿、占总资产 61%——在实体清单限制下"产能即订单"，提前锁定未来 12-18 个月的晶圆产能，代价是经营现金流净额同比下滑 66%，且上半年已计提存货跌价损失 3.97 亿。底气来自订单确定性：57 亿元股权激励计划的考核目标是 2026 年营收不低于 135 亿、2026-2028 年累计不低于 1000 亿。

摩尔线程：用亏损买时间。 全功能 GPU 的"大而全"路线（AI 计算 + 图形渲染 + 物理仿真 + 视频编解码）前期投入巨大，需要在现金流耗尽之前跨过规模化的门槛。上半年亏损已收窄至千万级，IPO 募资到位后，时间窗口正在变宽。

5. 软件生态：被忽视的胜负手​

需求外溢（英伟达 H20 系列在中国市场遇冷）推动 DeepSeek、智谱 GLM、月之暗面 Kimi 等头部模型纷纷适配国产加速器（昇腾、沐曦、摩尔线程等），这给了国产芯片难得的"真实负载打磨机会"。但正如行业共识：芯片可以三年一代，生态需要十年之功。寒武纪自研指令集的封闭高效、摩尔线程 MUSA 对 CUDA 生态的兼容路线、燧原 DSA 的专用极致——哪条路能沉淀出真正的开发者生态，才是决定 2030 年格局的关键变量。

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相关链接​

• 寒武纪 MLU690 规格页
• 沐曦曦云 C600 规格页
• 壁仞 BR100 规格页
• 燧原 T21 规格页

参考资料​

• Pandaily：China's Four Domestic AI Chip Makers Near a Commercial Turning Point（2026-09）
• 央视财经 / 大湾区经济网：百万卡缺口，订单排到三年后！国产算力上演"抢芯大战"（2026-09-01）
• 钛媒体：国产芯片的两场豪赌——寒武纪买确定性，摩尔线程买时间（2026-09-03）

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本文基于上市公司半年报、Pandaily 与央视财经等公开报道整理。财务数据为公司披露口径，市场份额为研究机构预测，不构成任何投资建议。

9 月第一周，存储行业传来三组关键信号：SK 海力士面向英伟达 Vera Rubin 平台量产交付全球首款 12 层 HBM4；三星 Q2 HBM 份额飙升至 33%、直逼王座；美光宣布年底 HBM 月产能翻倍至约 10 万片晶圆。 HBM4 的竞争，已经从"谁能造出来"变成"谁能最快量产爬坡、谁绑定的客户最深"。

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1. 三巨头战报：领跑者、追赶者与搅局者​

维度	SK 海力士	三星电子	美光
HBM4 关键节点	2026 年中向 Vera Rubin 量产交付 12 层 HBM4（全球首款完整质量认证）	2026 年 2 月全球首家大规模量产出货	2026 Q2 量产 12 层 HBM4，批量出货
DRAM 核心裸片	1b（第五代 10nm 级）	1c（第六代）	—
Base Die 代工	台积电 12nm	自家 4nm	拟转台积电（1γ 工艺代）
2026 HBM4 份额预测	~54%	~28%	~18%
Q2 HBM 营收份额	50%（环比 -14pct）	33%（环比 +12pct）	18%
HBM 产能	~15–20 万片/月	~15–20 万片/月	年底冲刺 10 万片/月（现为 4–5 万）

三个关键读数：

• 三星的反扑是真的：从去年 Q2 份额低至 15%（落后美光 6 个百分点）到今年 Q2 的 33%，三星用一年时间把与 SK 海力士的差距缩小到 17 个百分点。三星预计 HBM4 将占其下半年 HBM 收入的 60% 以上，且现有 HBM4 产能已被客户预订售罄，2026 年 HBM 总产能计划提升约 50%；
• 美光的追赶也是真的：CEO 梅赫罗特拉透露 12 层 HBM4 爬坡速度约为 HBM3E 的两倍、累计收入已超 10 亿美元；年底若如期达成 10 万片月产能，与两强的差距将缩小一半；
• SK 海力士的护城河依然深：与英伟达签署多年期 HBM/DRAM 供应协议、率先完成 2027 年 HBM4 价格谈判，在英伟达 HBM4 采购中占比约 60%（乐观情形 70%）。

2. 变局核心：封装比 DRAM 制程更值钱​

HBM4 与 HBM3E 时代最大的不同，是胜负手从存储颗粒转向了封装与 Base Die：

• I/O 通道数从 1024 条翻倍至 2048 条，单颗 12 层封装吞吐超 2TB/s，能效较前代提升逾 40%；
• Base Die 首次引入晶圆代工厂先进逻辑工艺——SK 海力士用台积电 12nm，三星用自家 4nm，美光计划在 1γ（首次导入 EUV）世代转由台积电代工；
• 存储原厂与代工厂的协作深度，第一次成为决定出货速度的关键变量——这正是 Hot Chips 2026 上"三星 HBM Base Die 逻辑工艺化"议题的产业注脚。

SEMI 数据显示，2026 年全球 HBM 市场规模预计增长 58% 至 546 亿美元，约占 DRAM 市场四成。行业预计 HBM4 销售占比将在 2026 年 Q4 正式超越 HBM3E，成为市场主流。

3. 客户端信号：Rubin 加码，Rubin CPX 重生​

需求端同样在 9 月出现重要变化：

• Vera Rubin 全面量产（详见本站专文）：每颗 Rubin GPU 搭载 288GB HBM4、带宽 22TB/s，NVL72 整柜 75TB 快速内存——HBM4 供给直接决定 Rubin 出货上限，这也是英伟达把"先进晶圆与 HBM 供应"列为当前第一约束的原因；
• Rubin CPX 项目重启：据 CFM 闪存市场 9 月 2 日简讯，英伟达重启此前搁置的 Rubin CPX 机柜项目，内存规格由 128GB GDDR7 改为 168GB HBM4，机架改为独立 MGX ETL 设计，客户可选 64/128/192/256 颗 GPU 配置——推理专用卡也全面转向 HBM4，进一步放大了 HBM4 需求；
• 供给协议长期化：英伟达已与 SK 海力士、美光签署多年期 HBM 及 DRAM 供应协议，锁供给、锁价格、锁产能成为巨头标配动作。

4. 下半场：HBM4E 已经鸣枪​

下一代产品的竞争在 2026 年同步开启：

• SK 海力士：HBM4E 送样提前至 2026 年年中（原计划下半年），COMPUTEX 2026 已展出 12 层样品，单引脚速率最高 16Gbps、单堆栈带宽约 4TB/s，计划 2027 年量产；
• 三星：2026 年 Q2 起向头部客户交付业界首批 HBM4E 样品（48GB），目标 2027 年拿下 HBM4E 市场 50% 以上份额；
• 美光：HBM4E 预计 2027 年量产，首批样品采用 1γ 制程 DRAM。

5. 对采购方与投资观察者的启示​

• 供应商组合成为第一优先级采购变量：同样买 Rubin 平台，采用哪家 HBM 供应商的整机，交付周期可能相差数月；
• 国产链条的机会窗口：HBM 供不应求叠加出口管制，长鑫等国产存储玩家的 HBM 进展值得持续跟踪——国产 AI 芯片（昇腾 950 系列等）对 HBM 的需求同样在放量；
• 跟踪三个领先指标：头部云厂商 Rubin 机架采购量、HBM 设备供应商订单（美光已加大 PO）、HBM4E 送样→量产的时间差。

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相关链接​

• NVIDIA Rubin 规格页
• NVIDIA Rubin CPX 规格页
• NVIDIA Rubin Ultra 规格页

参考资料​

• Electronic Times：US Micron to Double HBM Capacity, Closing Gap with Samsung and SK（2026-09-04）
• Korea Herald / News18：Samsung narrows SK hynix HBM lead as HBM4 shipments accelerate（2026-09-04）
• CFM 闪存市场：HBM4 量产爬坡竞速与 Rubin CPX 重启简讯（2026-09-02/04）
• 快科技：美光吹响反击号角！HBM4 产能翻倍直追三星海力士（2026-09-04）

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本文基于 2026 年 9 月初 Counterpoint Research、CFM 闪存市场及韩媒报道整理。份额与产能数据均为研究机构/供应链预估口径，实际以各原厂财报为准。

2026 年 9 月初，供应链信息确认：英伟达 Vera Rubin 平台已于 8 月正式量产、9 月启动批量出货，无延期、无卡顿。与 Blackwell 迭代初期的产能波折不同，这次量产节奏异常平稳——谷歌云、微软 Azure、CoreWeave、甲骨文云等头部云厂商已启动机架部署。但真正值得产业记住的，不是"又一代 GPU 量产了"，而是 Rubin 把液冷从"可选配置"变成了"硬性前置条件"。

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1. 量产节奏：史上最平稳的一次平台切换​

根据产业链调研与券商跟踪信息：

• 2026 年 8 月：Vera Rubin 正式量产；
• 2026 年 9 月：批量出货启动；
• 2026 下半年：CoreWeave、谷歌云、微软 Azure、甲骨文云机架部署落地；
• 2026 年：上代 GB 架构机柜出货量有望达 6 万台（同比翻倍）；
• 2027 年：GB 与 Rubin 两代平台合计出货体量有望接近 10 万台，Rubin 新机柜远期产能目标为每天 1000 个 NVL72 机柜。

需求侧同样在加码：华尔街报告披露，英伟达管理层表示 FY28 同比增长 70% 的目标并非需求上限——若供应不受限，增速可能超过 100%。当前主要约束已从需求端转向先进晶圆与 HBM 供应。

2. 单卡 2300W：风冷时代的终结​

Rubin 平台与前代最根本的差异不在算力，而在功耗密度：

指标	H100	GB300	Rubin
单 GPU TDP	700W	~1400W	2300W
机柜功耗	~40kW	~140kW	190–230kW
散热方案	风冷为主	风液混合	100% 全液冷
供电架构	48V	48V	800V 高压直流

单芯片 TDP 从 700W 升至 2300W、单机柜功率密度突破风冷物理极限——这意味着 液冷不再是高端算力的选配升级，而是运行 Rubin 服务器的先决条件。英伟达官方将 Rubin 全液冷架构定义为"数据中心历史上最重要的能效突破之一"，并已写入 DSX AI 工厂参考设计：所有跟随英伟达技术路线的云厂商和数据中心运营商，都必须采用全面液冷方案。

三个关键架构变化：

1. 无风扇整机：GPU、CPU、交换机、DPU 全部器件强制采用直接冷板式液冷，45℃ 温水冷板成为出厂标配；
2. 液冷边界延伸：散热覆盖范围从 GPU 冷板延伸至 CPU、DPU、交换机乃至光模块（液冷 Cage/鼠笼开始从"可选"变"刚需"），整套液冷系统价值量较 GB300 提升约 40%；
3. 800VDC 供电：替代传统 48V 机架配电，整机电源 BOM 价值增长 30% 以上，PSU 电源模块从 5.5kW 向 18.3kW 迭代，固态变压器、高压直流 CDU 成为数据中心新增核心设备。

3. 对产业链的三重传导​

第一重：液冷从"配套"变"主角"。 2026 下半年以小规模部署验证为主，真正的放量窗口在 2027 年——Rubin 机架大规模铺货后，冷板、快速接头、CDU、液冷泵进入业绩兑现期。台系供应链 7 月数据已率先验证：AVC 奇鋐 7 月营收 185.9 亿新台币创历史新高（同比 +57.4%），双鸿、健策 7 月同比分别 +116.7%、+91.0%。

第二重：国产液冷供应链进入核心 BOM。 国内厂商由外围冷源和代工环节逐步进入芯片平台、服务器 ODM 和海外云厂商供应体系，替代路径从 Manifold、管路推进至高可靠快接头和冷板。英维克 26H1 海外收入占比 71.4%，飞龙股份液冷泵小功率平台订单超 5 万台——液冷全核心零部件自主可控正在成为现实。

第三重：供电与散热边界融合。 800VDC 架构下，电源模块、PDB 配电单元、高速交换芯片自身发热也达到很高水平，部分电源组件同样需要液冷辅助散热——电源与温控两条产业链正在合并成一条。

4. 需求矩阵扩容：云厂商之外，太空算力入场​

Rubin 的客户矩阵已从传统云厂商扩展至三个层次：

• 全球云厂商：谷歌云、Azure、甲骨文云、CoreWeave；
• AI 科技巨头：马斯克公开披露 2027 年 8GW 超大规模 IDC 建设规划；SpaceX 将 Vera Rubin 架构定义为"最优 AI 计算架构"，计划地面与太空双向部署，支撑 "Starmind" 卫星算力项目；
• 主权与边缘：远期 Rubin Ultra 及 2027 年后更高功耗机型单机柜有望冲击 600kW+。

普华永道预计全球数据中心累计投资到 2035 年将达 31.6 万亿美元。AI 基础设施建设的确定性，已经从"是否建设"变成"多快建设"。

5. 对采购方的启示​

• 机房规划前置：2027 年起采购 Rubin 级算力，液冷改造（单千瓦改造成本较高）或按全液冷标准新建，必须在预算周期一开始就纳入；
• 看 PUE 也看水温：45℃ 温水直冷允许更高进水温度，可利用自然冷源压低 PUE——选址时人工冷源依赖度成为新的评估维度；
• 供应商组合即风险对冲：HBM 与先进封装供应是当前核心瓶颈（详见本站 HBM4 竞速分析），供应链多元化比单点性能更重要。

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相关链接​

• NVIDIA Rubin 规格页
• NVIDIA Rubin Ultra 规格页
• NVIDIA Rubin CPX 规格页

参考资料​

• 英伟达官方博客：Rubin 全液冷架构解析
• 财联社：Rubin 全面量产，看好液冷二次侧放量（2026-09-04）
• 东方财富研报：Vera Rubin 开启量产周期，AI 算力硬件环节迎来量价齐升（2026-08-27）
• 雪球：Vera Rubin 量产交付落地，全液冷 800V 高压架构重构（2026-09-03）

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本文基于 2026 年 9 月初供应链调研、券商研报与英伟达官方披露整理。出货量与功耗数据为产业链预估口径，实际以英伟达及客户正式披露为准。

August 23-25, 2026, the 38th Hot Chips (HC38) was held at Stanford's Memorial Auditorium. As the bellwether of global high-performance chip architecture, this conference landed exactly at the most intense moment of the AI compute arms race — the official agenda had 48 entries, including 7 AI accelerators, 6 memory tutorials, 6 CPUs, and 4 each of GPUs and networking. Putting the vendor talks together, one consensus emerged: the unit of AI compute competition has shifted from "single chip" to "whole rack / entire system."

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1. Overview: Three Days of Agenda, Almost a Preview of the 2027 AI Rack Market​

Monday (8/24) afternoon's GPU session was the focus, with four talks nearly colliding as the 2027 AI rack market:

• NVIDIA Rubin GPU ("Driving the Era of Agentic AI"): First chiplet-architecture GPU, 288GB HBM4, ~50 PFLOPS FP4, paired with 88-core Arm-architecture Vera CPU into NVL72 / NVL144 racks, mass production in H2 2026.
• AMD Instinct MI400 (two talks: architecture + system architecture): Told the "rack-scale" story thoroughly.
• Intel Crescent Island: A 350W air-cooled card designed for Agentic AI inference.

Tuesday (8/25) afternoon's AI session was almost a parade of "hyperscalers de-NVIDIA-izing": Google's 8th-gen TPU, OpenAI's first custom chip, Microsoft Maia 200, Meta MTIA, and Cerebras wafer-scale rack all appeared together.

Every vendor on stage used the term "Agentic AI" within the first two PPT slides — not a coincidence, but the collective shift in 2026 AI workload design goals.

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2. NVIDIA Rubin: One Rack Is a Supercomputer​

What NVIDIA featured at Hot Chips was not a single GPU but the Vera Rubin NVL72 whole cabinet — 72 Rubin GPUs + 36 Vera CPUs, 18 compute trays + 9 NVLink switch trays, about 1.3 million components, nearly 1,300 chips, weighing about 4,000 pounds (~1.8 tons).

The single Rubin GPU specs are equally stunning:

Metric	Rubin GPU	vs Blackwell
Transistors	336 billion (TSMC 3nm dual-die)	208 billion (+61.5%)
Memory	288GB HBM4	—
Bandwidth	22 TB/s	2.8× Blackwell
NVFP4 inference	50 PFLOPS	5× GB200
Training compute	35 PFLOPS	3.5×

The most disruptive design is in the compute tray: no cables, no hoses, no fans, all interconnected via the PCB backplane. NVIDIA says assembly time dropped from nearly 2 hours to 5 minutes (20× faster) while improving maintainability.

This time NVIDIA is selling not FLOPS but tokens per megawatt. Citing a SemiAnalysis benchmark based on DeepSeek-v4-PRO (140K+ context, AgentX workload), it claims: versus GB300 NVL72, Vera Rubin NVL72 delivers 10× to up to 30× tokens/MW as interaction intensity rises. A single cabinet provides 3.6 EFLOPS inference compute, whole-cabinet power 190-230kW; long-term capacity target is 1,000 NVL72 cabinets per day.

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3. AMD MI455X + Helios: Bigger Memory and Open Interconnect​

AMD's answer is the MI455X + Helios rack going head-to-head with NVIDIA. MI455X uses CDNA 5 architecture, 8 N2-process accelerator dies + N3P-process interconnect die, 256 workgroup processors, 192MB global L2.

Metric	MI455X	vs Rubin
Memory	432GB HBM4 (12-layer stack)	50% higher than Rubin's 288GB
Bandwidth	23.3 TB/s	Slightly ahead
MXFP4 compute	40.26 PFLOPS	—
System (Helios 72 cards)	2.9 ExaFLOPS FP4 inference	—
Price	~$5.25M per cabinet	—

At the system level, AMD bets on the UALoE (Ultra Accelerator Link over Ethernet) open standard: each GPU provides 3.6 TB/s bidirectional interconnect bandwidth; two 512-port 200G UALoE switch chips in the switch tray total 10.8 TB/s — opening the interconnect protocol to the whole industry while targeting NVLink.

Production cadence: AMD plans to deliver engineering samples and small-batch systems in H2 2026, with large-scale ramp in Q2 2027. Earlier rumors of Helios delay due to cooling issues were not confirmed by AMD.

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4. Intel Crescent Island: The Air-Cooled, Large-Memory "Cost-Effective Oddball"​

Intel offers a completely different path: Crescent Island — a 350W, air-cooled, standard-PCIe-slot inference GPU designed for Agentic AI, with the key metric being tokens per watt.

Metric	Crescent Island	Note
Architecture	Xe3P, 32 Xe cores, 32MB unified L2	Disclosed at Hot Chips
Memory	Intel branded card 160GB / ODM up to 480GB LPDDR5X	More than Rubin's 288GB HBM4
Form factor	350W air-cooled PCIe	Plugs into standard racks, no liquid-cooling retrofit
RAS	ECC, dynamic page offline, hard-package repair, PCIe advanced error reporting	Addresses "silent data corruption"

Intel's logic is clear: inference scenarios need far more memory capacity than bandwidth; using low-cost LPDDR5X for capacity and air cooling to skip liquid-cooling infrastructure drives down per-token cost. Combined with Diamond Rapids Xeon (256 performance cores, 1.28GB cache, 128 PCIe Gen6 lanes), Intel tries to surround from edge to datacenter with "CPU + inference GPU + open software stack."

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5. Custom ASIC Parade: Google, OpenAI, Microsoft, Meta Together​

Tuesday afternoon's AI session was the most historic of the conference — a parade of "hyperscalers de-NVIDIA-izing":

Chip	Vendor / Partner	Positioning	Key Specs / Progress
TPU 8t (Sunfish)	Google × Broadcom	Training	9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM
TPU 8i (Zebrafish)	Google × MediaTek	Inference	288GB HBM, 384MB on-chip SRAM (3× prev gen), ICI 19.2 Tb/s
Jalapeño	OpenAI × Broadcom	Inference	9-month end-to-end design, target ~50% token cost cut, commercial end of 2026
Maia 200	Microsoft (TSMC 3nm)	Inference	140B+ transistors, 10+ PFLOPS FP4, 216GB HBM3E, serving GPT-5.2 at Des Moines datacenter
MTIA 300-500	Meta (RISC-V) × Broadcom	Training + inference	Up to 25× compute gain, one model every 6 months before 2027

Google split TPU into training (8t) and inference (8i) dedicated architectures for the first time — its biggest architectural shift in a decade. Norm Jouppi personally took the stage to present TPU v8.

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6. Two Hidden Threads — Memory and Networking: HBM4 Year 1 + AI Factory OS​

Beyond GPUs/ASICs, two hidden threads mattered equally:

• Memory: Samsung's HBM Base Die (logic-process base die) and SK hynix's advanced packaging appeared together; the HBM4-era "base-die foundry" industry shift begins; HBF (high-bandwidth flash), LPDDR5X-PIM, 3D DRAM, and CXL compute-storage showcased "compute-in-memory" moving from papers to products.
• Networking: NVIDIA BlueField-4 (DPU) and Spectrum-X Multiplane architecture (presented by Gilad Shainer) — networking is becoming the decisive architecture for gigascale AI, scaling from hundreds of thousands to a million cards; Broadcom Thor Ultra Ethernet NIC keeps pressing; Mojo Vision showed chip-level optical I/O.

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7. Three Routes, One Consensus​

At the same conference, three vendors offered three distinctly different AI compute delivery philosophies:

1. NVIDIA: Full-stack closed integration — GPU, CPU, DPU, and switch chips all self-designed, pushing system performance to the extreme via ultimate software-hardware co-design, at the cost of deep customer lock-in.
2. AMD: Open-standard catch-up — Uses larger HBM4 capacity + UALoE open interconnect for a "cost-effective + open" play, tearing open the inference gap with Meta and OpenAI's 12GW-class orders.
3. Intel: Air-cooled cost-effectiveness — Abandons liquid cooling and HBM, uses LPDDR5X large memory + standard PCIe, betting that "most inference doesn't need a 200kW rack."

But all three agree: the unit of competition is no longer the chip, but the co-designed system (rack / system). For buyers, 2027 compute planning should compare not "single-card PFLOPS" but "tokens per megawatt, latency, availability, and full-lifecycle cost."

Related Links​

• NVIDIA Rubin spec page
• AMD MI455X spec page
• Intel Crescent Island spec page
• Google TPU 8t spec page
• Google TPU 8i spec page

References​

• Hot Chips 2026 Three Giants Together: Rubin 336B Transistors, MI455X 432GB, Crescent Island 480GB - IC Chip Industry Watch
• Hot Chips Day 2: Rubin, MI400 and Diamond Rapids Go Head-to-Head - AI2Work
• NVIDIA Vera Rubin NVL72 Rack at Hot Chips 2026 - ServeTheHome
• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim

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This article is compiled from Hot Chips 2026 (Aug 23-25) official presentations and on-site reports from ServeTheHome, SemiAnalysis, TechPowerUp, etc. Performance data are vendor-disclosed figures; actual performance subject to mass-produced products.

The Tuesday-afternoon AI session at Hot Chips 2026 this August was the most historically significant of the conference — not because any single chip was so powerful, but because almost everything on stage was a "hyperscaler de-NVIDIA-ization" custom ASIC: Google's 8th-gen TPU, OpenAI's first self-designed chip, Microsoft Maia, Meta MTIA, and Cerebras wafer-scale racks, all on one stage. When the world's largest AI compute buyers start treating GPUs as "one of the options," the power structure of AI hardware is loosening.

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1. OpenAI Jalapeno: Building a Chip in 9 Months​

On June 24, 2026, OpenAI, together with Broadcom, unveiled its first self-designed inference ASIC, Jalapeno — the fifth member of the "custom inference chip club."

Dimension	Jalapeno
Partner	Broadcom + TSMC manufacturing
Positioning	Inference-specific ASIC
Design cycle	9 months end-to-end (Greg Brockman says aided by OpenAI's own models)
Cost target	~50% lower token cost vs general-purpose GPU stack
Commercial timing	First deployments by end-2026; long-term goal 10GW of self-designed chips
Deal scale	Up to $10B strategic partnership with Broadcom (accelerators + networking by 2029)

The talk title "You Can Just Build Things … Chips" is itself a signal: the largest AI compute buyer no longer defaults to GPU as the only path.

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2. Google TPU v8: The Biggest Architectural Pivot in a Decade — Train/Infer Split​

Google has the longest custom-chip history (2016 to now), and its 8th-gen TPU for the first time splits the product line in two:

Model	Codename	Partner	Positioning	Key Specs
TPU 8t	Sunfish	Broadcom	Training	9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM, 2× ICI bandwidth
TPU 8i	Zebrafish	MediaTek	Inference	288GB HBM, 384MB on-chip SRAM (3× prior gen), 19.2 Tb/s ICI

On capacity, Morgan Stanley estimates based on supply-chain interviews that Google TPU production in 2026 may exceed 3 million units (a brokerage estimate, not an official target). Google is also the only vendor to achieve large-scale custom-chip deployment and sell compute externally (Gemini runs on TPUs).

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3. Meta MTIA: From Recommendation Systems to a GenAI Dual Mission​

Meta's custom journey has the clearest starting point — MTIA was originally built for recommendation ranking hardware and is being pulled toward a dual mission by generative AI.

• MTIA 300 is deployed; 400 / 450 / 500 are planned at roughly one new model every 6 months through 2027;
• Based on RISC-V, Meta claims up to 25× compute gain;
• Node evolves with industry cadence: 100 (7nm) → 200 (5nm) → 300 series (3nm + CoWoS);
• In partnership with Broadcom; another chip codenamed Iris reportedly passed testing in July 2026;
• Meta plans to start volume production of one of them in September 2026, doubling its overall compute.

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4. Microsoft Maia 200/300: Most Advanced Deployment​

Microsoft's Maia 200, released January 26, 2026, is the most advanced in deployment among the four:

Dimension	Maia 200
Process	TSMC 3nm, 140B+ transistors
Compute	10+ PFLOPS FP4 / 5 PFLOPS FP8
Memory	216GB HBM3E, 7 TB/s
Power	750W
Deployment	Already running in Des Moines data center, serving OpenAI GPT-5.2 and Microsoft 365 Copilot

Microsoft claims roughly 3× the performance of Amazon's Trainium on specific benchmarks. The short-term strategy is a dual track of "self-designed Maia + purchased NVIDIA" in parallel — self-designed chips need time from design to mass production, and NVIDIA's mature ecosystem cannot be replaced in the short term.

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5. Amazon Trainium 3 and Anthropic's In-House Team​

• Amazon: The Trainium series is already commercial, with 1.4 million units cumulatively deployed (officially disclosed) — a multi-billion-dollar business; its strength is the AWS customer base, letting enterprises choose between NVIDIA GPUs and self-designed chips. Trainium 3 continues this path.
• Anthropic: In August 2026 announced the formation of an in-house chip team, with no tape-out or mass-production timeline yet; initially positioned as a complement (not a replacement) to existing partnerships with NVIDIA/AMD/AWS/Google Cloud, aiming to tailor-build for the Claude architecture and shed reliance on a single GPU.

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6. NVIDIA's Answer: Not a Faster GPU, But Full-Stack​

It's easy to simplify the narrative to "four companies build chips, NVIDIA defends GPU." But NVIDIA took 6 slots at Hot Chips: a RISC-V tutorial, the Vera CPU, the Rubin GPU, the BlueField-4 DPU, the Spectrum-X multi-plane network, and an LPU accelerator.

A hyperscaler ASIC replaces only one of those five pillars. If the CPU, NIC, switching fabric, and software all come from the same vendor, what you save by swapping out the accelerator is far less than the accelerator line item on the bill suggests. Rubin's play is a full-stack AI factory platform spanning seven chips and five racks — the competitive answer is "full-stack positioning," not "a faster single chip."

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7. Trend Judgment: Inference De-GPU-izes, Training Still GPU-Led​

• Inference side: The CUDA moat visibly shallows. Inference is parallelizable and replaceable at the endpoint; custom ASICs trade away the generality tax (implementing only the operations LLMs actually execute) for lower cost/token. Groq LPU, Cerebras, and various TPU/ASIC players all compete on the same metric.
• Training side: Foundation models are still trained on GPUs, with no serious challenger in the short term. NVIDIA's three training moats (fastest silicon + NVLink + CUDA) remain firm.
• Conclusion: Custom chips are not "replacing NVIDIA," but giving buyers a credible external negotiation option in the largest and fastest-growing battlefield — inference. That alone is enough to reshape the economics of AI infrastructure.

Related Links​

• Inference Accelerator Market 2026
• Hot Chips 2026 Full Recap
• Google TPU 8t Spec Page
• Google TPU 8i Spec Page

References​

• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim
• Custom AI inference silicon: why OpenAI built Jalapeno - nexi.fund
• Anthropic Builds Custom AI Chips for Claude - Studio Global AI
• 所有大厂都在做同一件事：自己造芯片，少买英伟达的 - Toutiao

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This article is compiled from August 2026 Hot Chips on-site reports, corporate announcements, and industry analysis. Some capacity and performance figures are brokerage estimates or vendor-disclosed figures; actual results are subject to mass-produced products.

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.

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1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

Timeline	Samsung HBM4 Yield	Notes
Feb 2026 (mass production start)	Under 60%	Line ramp-up period
Early Aug 2026	~80%	Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.

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2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor	2026 Rubin HBM4 Allocation (est.)	Notes
SK Hynix	60%–70%	Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung	25%–30%	Rapid share gains after yield leap
Micron	Remainder	Limited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.

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3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

• Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
• HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
• Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

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4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

Spec	HBM4 (12-Hi / 16-Hi)	HBM4E
Per-stack capacity	36 GB / 48 GB	—
Pin rate	11.7–13.0 Gbps	16 Gbps
Per-stack bandwidth	up to 3.3 TB/s	up to 3.6 TB/s
Bus width	2048-bit	—
Energy efficiency	+40% vs HBM3E	—
Thermal resistance / cooling	+10% improvement / +30%	—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.

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5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

• 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
• The industry already anticipates significant price increases;
• For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.

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6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

Related Links​

• NVIDIA Rubin Spec Page
• AMD MI455X Spec Page
• Hot Chips 2026 Full Recap

References​

• Samsung's HBM4 Yield Hits 80% as HBM Race Heats Up - TrendForce
• Samsung HBM4 Yield Hits 80%, Boosting AI Memory Supply - PC Central
• Samsung Weighs Shipping Legacy Memory Backend to Vietnam to Unlock HBM Capacity - TechTimes
• 芯闻|六个月良率跃迁：三星HBM4突破80%黄金门槛 - Toutiao

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This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

In 2026, China's AI chip market landscape has shifted from "NVIDIA unipolar dominance" to "overseas vendors leading, domestic multi-route catch-up." According to industry research, China's overall AI accelerator market was ~4M units in 2025, of which 1.65M were domestic, with share first breaking 40%; as products iterate and fabs follow up, the localization rate is expected to rise to 60%-70% by 2027. This article focuses on the latest H2 2026 progress of Huawei Ascend, Cambricon, and Moore Threads — the domestic "Big Three."

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1. Huawei Ascend: 950 Capacity Fully Booked, 960 Roadmap Unveiled​

Ascend's core advantage is "architecture + full-stack ecosystem synergy," with ~800K units shipped in 2025, capturing 50% of the total domestic vendor share. The product iteration cadence is clear:

Time	Product	Note
2025 Q1	Ascend 910C	Main transitional model
2026 Q1	Ascend 950PR	Inference flagship
2026 Q4 (planned)	Ascend 950DT	Training flagship, drives domestic HBM iteration
2027-2028	Ascend 960 / 970	Roadmap products

950 series capacity has entered a "fully booked" state: 950PR entered mass production in April 2026; June monthly capacity jumped to 500K-600K units (nearly 10x MoM), with a full-year target of 1.2M units at 100% certainty; ByteDance locked in 350K units for $5.6B, while Tencent / Alibaba / Baidu combined locked in 400K units.

Ascend 960 roadmap specs (per roadmap disclosure):

Metric	Ascend 960
Architecture	Ascend 6th gen (Da Vinci v6)
FP8 compute	~4 PFLOPS
Memory	288GB
Memory bandwidth	9.6 TB/s
Super-node	Atlas 960 SuperPoD, 15,488 cards, Lingqu optical-electrical converged bus
Debut	2027 Q4 (roadmap)

The previous-gen Ascend 384 super-node has cumulatively shipped over 750 sets, deployed across 20+ industries including internet, operators, finance, education, and healthcare — Huawei calls it "the only domestic super-node that has trained a SOTA model."

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2. Cambricon MLU690: H2 Mass Production, Entering ByteDance Bidding Window​

Cambricon is the core domestic compute leader in the absence of an Ascend IPO, with the technology gap continuously narrowing:

• Siyuan 590 (7nm): Performance equivalent to 80% of A100, already supports DeepSeek, continuously adapting to mainstream large models like Qwen 3 and GLM
• Siyuan 690 series: Will enter mass production in H2 2026, expected to achieve order scale-up during ByteDance's H2 bidding window
• Revenue certainty: Equity incentive targets show >100% revenue growth for the next 3 years: 2026 revenue target 13.5B RMB, 2027 27B RMB, 2028 60B RMB

Cambricon fully benefits from the industry dividend of "domestic CSP capex + full adaptation of domestic large models and domestic chips," making it the most direct elasticity play on rising localization rate.

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3. Moore Threads MTT S5000: Full-Function GPU + Ecosystem Breakthrough​

Moore Threads takes a differentiated "full-function GPU" route, with the flagship MTT S5000 based on the 4th-gen "Pinghu" MUSA architecture:

Metric	MTT S5000
Dense AI compute	1000 TFLOPS
Memory	80GB
Memory bandwidth	1.6 TB/s
Inter-card interconnect	784 GB/s
Precision	FP8 to FP64 full precision (training + inference)
Security	First batch to pass national "Safe and Reliable Evaluation" (Level I)

Its engineering capability is verified: the Kuae (KUAE) intelligent computing cluster based on S5000 achieves 95% training linear scaling efficiency, with compute efficiency loss within 5% at ten-thousand-card scale; supports checkpoint-resume training with effective training time ratio >90%; and has trained a MoE-236B base model with >25 trillion tokens of corpus from scratch.

The ecosystem is Moore Threads' deepest moat: MUSA has achieved 100% core math library compatibility, 3000+ PyTorch operator compatibility, covers 55 categories of core AI operators, has official vLLM and SGLang support, Day-0 adaptation of mainstream models, and 800K+ developers. Its PD heterogeneous-disaggregation solution achieves equivalent replacement of international high-end GPUs at a 2:1 ratio with S5000, significantly reducing inference cost.

The 5th-gen "Huagang" architecture (released 2025-12) supports FP4 to FP64 full precision, with 50% higher compute density and 10x better energy efficiency than the previous gen, supporting 100K+ card clusters; cumulative R&D investment in the "Huashan" (train-infer integrated) and "Lushan" (graphics rendering) new chips based on this architecture exceeds 900M RMB.

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4. Software Ecosystem Decides: Day-0 Adaptation Becomes Routine​

Beyond hardware, software ecosystem realization is the watershed for domestic compute in 2026:

• Huawei's CANN heterogeneous computing architecture and MindSeries suite are fully open-sourced, with the community incubating 67 projects, 12.44M+ lines of code, and 3,500+ monthly active developers
• The "release-and-adapt" closed loop between domestic large models and domestic chips has basically formed: Tencent Hunyuan T3 (295B), DeepSeek-V4, and GLM-5.2 all completed Day-0 adaptation
• 2026 is regarded as the "first year of domestic super-nodes"; Huatai Securities estimates China's super-node architecture market will reach 341.4B RMB by 2028, with a 2026-2028 CAGR of 194%

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5. Industry Judgment: From "Can It Be Built" to "Can It Be Used Well"​

The domestic Big Three are converging along three paths:

1. Huawei: Locks government/enterprise and internet big customers with super-node system-level capability + full-stack software
2. Cambricon: Impacts the revenue inflection point by narrowing the training-side gap + scaling up via big-customer bidding
3. Moore Threads: Covers cloud-edge-end full scenarios with full-function GPU generality + mature CUDA-compatible ecosystem

The common shortcoming of all three remains advanced process and HBM supply — precisely the core link of overseas controls. But as domestic HBM iterates and fabs follow up, a realistic path to 60%-70% localization by 2027 exists.

Related Links​

• Huawei Ascend 960 spec page
• Huawei Ascend 950DT spec page
• Cambricon MLU690 spec page
• Moore Threads MTT S5000 spec page

References​

• Domestic AI Chip Industry View Update - Robo Datayes
• Moore Threads, Two Positives in One Day - Eastmoney
• Moore Threads × SiliconFlow: PD Disaggregation Heterogeneous Compute Co-location Whitepaper - EE Focus
• After Approaching Break-even, Moore Threads Faces Hong Kong "Big Exam" Again - Top News

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This article is compiled from public industry research, broker views, and corporate announcements as of August 2026. Some shipment and market-share figures are third-party estimates, not officially confirmed data.

For the past three years, the entire AI hardware story was "training": who had the most H100s, who could connect a hundred thousand GPUs into a cluster. That race is essentially settled — NVIDIA won. But the next battlefield, "inference," is being fought under completely different rules: the measure is no longer peak FLOPS, but cost-per-token, latency, and power. In 2026, inference chips overtake training in scale for the first time, becoming the main battlefield of AI accelerators.

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1. Inference Becomes the Main Battlefield: 80%–90% of Compute Spent on Inference​

Training a large model costs hundreds of millions of dollars — once. But once the model goes live, it must answer billions of queries day after day. A popular consumer model may need tens of thousands of accelerators running 7×24 to keep up with demand. Therefore:

• Inference accounts for roughly 80%–90% of a model's lifecycle compute;
• Inference chips will make up about 60%–70% of the ~$400B AI accelerator market in 2026, up from only ~40% in 2023;
• Inference chip growth (estimated +52.7% YoY) significantly outpaces training chips (+28.4%); the share of inference-side compute demand exceeded training-side for the first time in 2026, reaching 54% (~$1010B).

The economics of inference are straightforward: training cost is amortized to near-zero, while inference cost becomes the entire bill. Every 1% cut in inference cost flows directly to profit — for a company whose inference traffic reaches hyperscale like OpenAI, the half of the bill is a number followed by a string of zeros.

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2. Market Size: Structural Growth Inflection Point Has Arrived​

Market	2026 Size	Growth	Notes
Global dedicated inference chips	$412.7B	+38.4%	14.2 pct higher growth than training chips
China dedicated inference chips	$118.6B (28.7% of global)	+44.1%	Strongest single market in APAC by growth
Global AI training/inference chips (incl. GPU/NPU)	exceeds $1850B	+40.2%	GPU ~62%

China's domestic substitution is accelerating, with domestic inference chips reaching 34.6% of shipments, up 9.8 pct from 2025.

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3. Technology-Axis Share Inverts: GPU Slows, ASIC Soars​

Axis	2026 Shipment Share	Trend
GPU	52.6%	Still leads, but growth slows to 22.7%
ASIC custom chips	41.3%	Up sharply from 17.8% in 2022
FPGA	Stable	Specific low-latency scenarios

Thanks to ecosystem maturity, GPU remains the mainstay, but NPU/ASIC already holds a 1.8× advantage over same-generation GPUs in energy efficiency, driving rapid adoption at the edge and on-device. Shipments of inference-optimized ASICs are expected to reach 11.5 million units, with unit cost about 35% lower than GPUs.

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4. Five Schools Clash​

School	Representative Products	Core Strength	Use Cases
General-purpose GPU	NVIDIA Rubin / B200 / H200	Mature ecosystem, train+infer unified	Frontier training + highly interactive inference
LPU (Language Processing Unit)	Groq LPU	Ultra-low latency, deterministic throughput	Real-time dialogue, high-concurrency inference
TPU (inference-specific)	Google TPU 8i (Zebrafish)	288GB HBM, 384MB on-chip SRAM, 19.2 Tb/s ICI	Google's scaled inference
Custom ASIC	OpenAI Jalapeno, Microsoft Maia 200, Meta MTIA	Strip generality tax for own models, ~50% lower cost/token	Hyperscaler's own workloads
Air-cooled inference card	Intel Crescent Island	350W air-cooled, 480GB LPDDR5X, tokens/watt	Cost-sensitive mid/long-tail inference

OpenAI's Jalapeno, co-developed with Broadcom, aims to cut inference token cost by roughly 50% versus a general-purpose GPU stack — the fifth member to join the "custom inference chip club" (after Google TPU, Amazon Inferentia/Trainium, Microsoft Maia, and Meta MTIA).

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5. Core Metric Shifts: cost-per-token and tokens/watt​

The fundamental difference between the inference race and the training race is the low switching cost:

• Training requires a 100k-GPU cluster + NVLink + CUDA, with extremely high migration cost;
• Inference is "embarrassingly parallel" at the endpoint level — no million-GPU cluster needed; a node that produces tokens fast and cheaply suffices, and is replaceable per endpoint.

This means NVIDIA's three moats (fastest silicon, NVLink scale-out, CUDA) are no longer absolute on the inference side. When the largest AI buyer (OpenAI) starts treating GPUs as "one of the options," the GPU premium begins to erode — pricing power relies on scarcity, and custom chips attack that scarcity from two directions at once: both reducing merchant-chip demand and giving buyers a credible external negotiation option.

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6. Edge and On-Device Explosion: Long-Tail Signal​

Demand shows significant long-tail and fragmentation:

Scenario	2026 Demand Size	Growth
Cloud inference	$198.2B (48%)	+24.5% (slowing)
Edge inference	$126.5B (30.7%)	+52.3%
On-device inference	$88.0B (21.3%)	+68.9%
Autonomous-driving inference	$67.3B	+58.2%
Industrial QA / robotics inference	$42.1B	+63.7%

The latency sensitivity and power constraints of inference workloads are reshaping chip architecture design priorities — which also explains why "air-cooled, large-memory" solutions like Crescent Island can find a niche.

Related Links​

• Hot Chips 2026 Full Recap
• Hyperscaler Custom Silicon Wave 2026
• NVIDIA Rubin Spec Page
• Intel Crescent Island Spec Page

References​

• Inference Chips vs Training Chips - ValueAdd VC
• Global and China Dedicated Inference Chip Industry In-Depth Research Report (2026) - IIM
• 2026 Global AI Training/Inference Chip Market and Trend Report - IIM
• Custom AI inference silicon: why OpenAI built Jalapeno - nexi.fund

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This article is compiled from publicly available 2026 market research, brokerage reports, and industry analysis. Market sizes and shares are third-party estimates with inconsistent methodologies and are for reference only.

The 2026 World Artificial Intelligence Conference (WAIC) was held July 17-20, 2026 at the Shanghai World Expo Center, themed "Intelligent Partners, Creating the Future Together." Over 1,100 companies showcased 3,000+ exhibits, with 300+ products debuting globally. For the compute-card industry, this concentrated review of domestic compute sent a clear signal: the competitive main line is shifting from "single-chip peak compute" to "SuperNode system-level effective compute."

1. Huawei Atlas 950 SuperPoD: live debut, wins SAIL grand award​

Huawei's Atlas 950 SuperPoD live hardware made its first public appearance at WAIC 2026, on-site carrying 16 compute cabinets with 1,024 Ascend cards total. With three system-level innovations — "ultra-wide bandwidth, ultra-low latency, unified memory addressing" — it stood out from hundreds of domestic and international entries to win the conference's top honor, the SAIL (Super AI Leader) Award.

Core parameters (confirmed on-site at WAIC)​

Metric	Atlas 950 SuperPoD
Exhibited scale	16 compute cabinets / 1,024 Ascend cards
Max interconnect scale	8,192 Ascend NPU cards fully interconnected (full config)
Interconnect protocol	Huawei in-house "Lingqu" (UnifiedBus) 2.0
Total compute	1 EFLOPS FP8 / 2 EFLOPS FP4 (1,024 cards); full 8,192-card ~8 EFLOPS FP8
Unified memory	256 TB globally unified memory address space
Interconnect latency	3 μs ultra-low RTT; TB-level NPU interconnect bandwidth
Full config	128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡, carrying 8,192 Ascend 950DT
Launch	Full config planned for Q4 2026
Cooling	Fully liquid-cooled blind-plug architecture

Huawei disclosed for the first time: the previous-gen Ascend 384 SuperNode has cumulatively shipped 750+ units commercially, deployed across 20+ industries including internet, operators, finance, education, healthcare, transportation, and manufacturing, calling it "the only domestic SuperNode that has trained SOTA models."

2. Software ecosystem: CANN fully open-sourced, developers at scale​

Beyond hardware, Huawei highlighted open-source software ecosystem progress:

• CANN heterogeneous compute architecture and MindSeries base software suite were fully open-sourced end of 2025;
• The CANN open-source community has incubated 67 projects, 12.44M+ lines of code, with 3,500+ monthly active developers;
• Huawei has co-developed 7,000+ solutions with 3,000+ industry partners, serving 2,000+ core government/enterprise customers;
• WAIC showcased 60+ real business scenarios, 20+ benchmark cases, covering the full chain from technology breakthrough to scaled commercial deployment.

3. Domestic chips' Day-0 adaptation becomes routine​

On July 6, 2026, Tencent released the MoE model Hunyuan T3 (295B parameters, 256K context); domestic chips rapidly completed Day-0 adaptation:

Vendor	Chip	Adaptation status
Moore Threads	MTT S5000	Completed rapid Hunyuan T3 adaptation (previously adapted DeepSeek-V4, GLM-5.2)
MetaX	Xiyun C series	In-house MXMACA stack first to full-chain Day-0 adaptation, zero-code deployment

Moore Threads also showcased the MTT C256 SuperNode (first-of-its-kind single-layer Scale-up 256-card full interconnect, sub-microsecond latency) and three AI-factory solutions — "model training factory / token production factory / agent production factory."

4. More domestic compute debut highlights​

Vendor / product	Highlight
Orient AlphaChip DF1000	World's first "software-defined + near-memory computing" 3D chip, interconnect pitch compressed to sub-micron
ZhongHao XinYing "Xuyu"	Fully in-house next-gen TPU-architecture AI-specific chip, with Taize 2.0 server
Enflame × Iluvatar	Domestic high-performance Matrix SuperNode based on OEX+dOCS architecture, shortlisted for the conference "Excellent AI Leader Award"
Rongming Microelectronics	Advancing next-gen VPU, evolving from video processing to "visual-agent compute base"

The domestic AI chip lineup also included Moore Threads, MetaX, Enflame, Houmo, Cixiong, Suaneng, SemiDrive, Phytium, Aixin, Iluvatar, and others.

Industry interpretation: from "can it be built" to "is it used well"​

WAIC 2026 reflects a fundamental shift in the competitive stage of domestic AI chips:

1. SuperNode becomes the main battlefield: beyond single-chip performance, system-level capabilities — "inter-chip interconnect + cluster scale + cooling" — become the breakthrough key. Huawei Lingqu and Enflame/Iluvatar OEX are both pushing here. Huatai Securities defines 2026 as the "first year of domestic SuperNodes," estimating China's SuperNode architecture market could reach ¥341.4B by 2028, with 2026-2028 CAGR of 194%.
2. Software ecosystem delivers: Day-0 adaptation has gone from slogan to routine; the "launch-and-adapt" closed loop between domestic large models (DeepSeek-V4, GLM-5.2, Hunyuan T3) and domestic chips is essentially formed.
3. Demand-side endorsement: China Mobile earlier released its 2026-2027 AI SuperNode centralized procurement announcement — about 6,208 cards, over ¥2B — accelerating domestic SuperNode scaled commercialization.

Related links​

• Huawei Ascend 950DT specs
• Huawei Ascend 950PR specs
• Moore Threads MTT S5000 specs

References​

• Ascend 950 SuperNode live at WAIC 2026, wins SAIL top award - Global Times
• 2026 WAIC compute competition enters "system-level" battlefield, Ascend 950 SuperNode debuts - Tencent News
• Huawei unveils advanced Atlas 950 SuperPoD - China Daily
• Huawei Ascend 950 wins WAIC 2026 SAIL top honor - Huxiu
• Compute heavyweights at WAIC: Huawei Ascend 950 SuperNode live - 21st Century Business Herald

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This article is compiled from WAIC 2026 (July 17-20) on-site and official disclosures, and will continuously track the 950 SuperNode Q4 launch.

AMD has confirmed its flagship AI event Advancing AI 2026 will be held July 22-23, 2026 at the Moscone Center in San Francisco, with the keynote on July 23 hosted by Chair and CEO Lisa Su. The event will complete the Instinct MI400 series availability timeline, pricing, and independent benchmark data.

1. Instinct MI400 family: three CDNA 5 accelerators​

AMD fully revealed the MI400 matrix at CES 2026; all three accelerators use CDNA 5 architecture, TSMC 2nm process, differentiated by precision and scenario:

Model	Positioning	Key specs
MI455X (flagship)	Large-scale train/inference (rack-scale)	320B transistors, 12 chiplets, 432 GB HBM4 (12×36GB), 19.6 TB/s, FP4 40 PFLOPS / FP8 20 PFLOPS
MI440X (enterprise)	Local enterprise AI (8-card node)	Low-precision AI (FP4/FP8/BF16), direct MI300/MI350 replacement, compatible with existing power/cooling
MI430X (HPC/sovereign AI)	High-precision scientific computing + AI	Full FP32/FP64, already deployed at Oak Ridge Discovery and France's first exascale Alice Recoque

MI455X and MI440X target low-precision AI (FP4/FP8/BF16); MI430X fills traditional HPC high-precision needs — improving energy efficiency and cost-performance by "trimming execution units by precision." All three support UALink (among the first accelerators compatible with the standard) and Infinity Fabric die-to-die interconnect; rack scaling uses Ultra Ethernet.

Lisa Su confirmed on the Q1 2026 earnings call: MI455X samples have been sent to core customers, with demand "exceeding the company's internal expectations for 2027."

2. Helios rack: 3 exaFLOPS per cabinet​

AMD enters the hyperscale market with the Helios rack-scale platform:

Metric	Helios rack
Accelerators	72 × MI455X
Aggregate HBM4	31 TB
Total memory bandwidth	1.4 PB/s
Per-cabinet compute	Up to 3 AI exaFLOPS (Q3 delivery target)
Target customers	Hyperscale train/inference clusters

Helios uses AMD's in-house Zen 6 EPYC Venice CPU (18 per rack) + Pensando Vulcano 800G NIC, integrated via the open ROCm software stack; AMD also plans a double-width 128-card Helios variant, pushing per-cabinet compute to the 3 AI exaFLOPS ceiling. Further out, the MI500 series (CDNA 6, 2nm, HBM4E) is planned for 2027, with official claims of up to 1000× AI performance vs MI300X.

3. 12GW deal: OpenAI + Meta dual endorsement​

AMD holds two historic-scale compute agreements totaling about 12 GW, with lifetime potential revenue possibly reaching $100B:

Customer	Scale	First deployment	Structure
OpenAI	6 GW (multi-gen products)	First 1 GW, H2 2026 on MI450	"compute-for-upside": up to 160M warrants, vesting by milestone and stock-price targets
Meta	6 GW	Custom MI450 chips, from H2 2026	Deployed in next-gen data centers

Financial expectations​

Metric	2026 forecast
MI400 series revenue	~$7.2B (about 25% of data-center sales)
Data-center GPU revenue	~$15B (up +114% YoY)
Total data-center revenue	Possibly $28.7B (up +73% YoY)

⚠️ Execution risk: AMD has flagged that MI450's Q3 mass production will weigh on gross margin (new products below company average); advanced process and advanced packaging (TSMC CoWoS) capacity remain the main constraint.

Industry interpretation​

1. CUDA moat being pried open: when companies building the world's largest training clusters — Meta, OpenAI — bet on AMD silicon, AMD's long-standing 5-7% GPU share ceiling is being broken.
2. Memory advantage as differentiation: 432 GB HBM4 / 19.6 TB/s vs NVIDIA Rubin's 288 GB offers capacity advantage, critical for large-model inference (KV Cache-constrained scenarios).
3. Tight benchmarking pace: MI450 and NVIDIA Vera Rubin both ramp in H2 2026, with the two giants competing head-on over HBM4 supply and CoWoS capacity.

Related links​

• AMD Instinct MI455X specs
• AMD Instinct MI400 specs
• AMD Instinct MI350 specs

References​

• AMD sets July date to detail its Instinct MI400 AI accelerators - IT Magazine
• Lisa Su: AMD has sent MI450 GPU samples to core customers - AGI.Space
• AMD and OpenAI announce strategic partnership to deploy 6GW AMD GPU - AMD press release
• AMD's 12-Gigawatt AI Contract Haul - StocksToday

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This article was written on the eve of Advancing AI 2026 (July 22-23, opening tomorrow); the keynote is July 23 hosted by Lisa Su, where MI400's final availability, pricing, and independent benchmarks will be revealed — we will update in sync.