4 posts tagged with "AI Chip"

Huawei Ascend 910C (Ascend 910C), Huawei's third-generation Ascend AI chip, adopts innovative dual-die (Chiplet) packaging and began mass supply in May 2025, becoming the backbone of domestic AI compute.

This article comprehensively analyzes this domestic flagship AI chip across four dimensions: technical specs, deployment cases, performance comparison, and market positioning.

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1. Core Technical Specifications​

1.1 Chip architecture and process​

Item	Parameter
Architecture	Da Vinci (dual-die packaging)
Process	SMIC N+2 (7nm-class)
Packaging	Chiplet (2× Ascend 910B compute dies)
Transistors	~53 billion
Die size	~800mm² (estimated)

Technology highlights:

• Dual-die Chiplet packaging integrates two 910B chips, breaking the single-die yield bottleneck
• Centerless I/O die design lets the two compute dies interconnect directly, reducing communication latency
• SMIC N+2 process delivers 7nm-class performance with a controllable, autonomous supply chain

1.2 Compute performance​

Precision	Compute	Reference
BF16	800 TFLOPS	~60% of NVIDIA H100
FP16	~800 TFLOPS	Close to H100 at same precision
INT8	~1600 TOPS	Clear inference advantage
FP32	Not disclosed	Training mainly uses BF16/FP16

Performance characteristics:

• 800 TFLOPS at BF16, a new domestic AI chip compute benchmark
• ~2× compute over 910B (dual-die stacking + architecture optimization)
• No FP8 precision support (NVIDIA Blackwell's strength)

1.3 Memory and interconnect​

Item	Parameter
HBM type	HBM2E (8 stacks)
Memory capacity	~128 GB (combined dual-die)
Memory bandwidth	784 GB/s
Interconnect protocol	Huawei AscendLink (in-house)
Interconnect bandwidth	400 GB/s unidirectional (800 GB/s bidirectional)

Memory advantages:

• 128GB capacity supports full-pipeline training of hundred-billion-parameter models
• 784 GB/s is a high-end configuration among HBM2E solutions
• In-house AscendLink protocol supports 384-chip all-optical interconnect

1.4 Power and energy efficiency​

Item	Parameter
TDP (dual-die)	~310 W
Energy efficiency (BF16)	~2.58 TFLOPS/W
vs. H100	~45% of H100's power, comparable energy efficiency

Energy efficiency advantages:

• At equal compute, significantly lower power than NVIDIA H100 (700W)
• 7nm-class process, ~30% better energy efficiency than 910B
• Suited to large-scale cluster deployment, reducing data center PUE pressure

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2. Key Deployment Cases​

2.1 CloudMatrix 384 SuperNode​

System specs:

Item	Configuration
Chip count	384 Ascend 910C
Cabinets	16 (12 compute + 4 network)
Total HBM	~49 TB (128GB × 384)
Interconnect	All-optical mesh network
Optical modules	6,912 LPO optical modules
System BF16 compute	~300 PFLOPS

Performance comparison:

• CloudMatrix 384's total BF16 compute exceeds NVIDIA GB200 NVL72 (72× B200)
• In large-model training, 384-chip 910C linear scaling efficiency reaches 85%+
• Supports smooth scaling to ten-thousand-card clusters for ultra-large training

Deployment progress:

• As of June 2026, over 500 CloudMatrix 384 SuperNodes deployed
• Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud, iFlytek
• Scenarios: large-model training, smart customer service, autonomous-driving simulation, scientific computing

2.2 DeepSeek-V4-Pro full-parameter post-training​

Breakthrough significance:

On June 5, 2026, the AI training platform of Shenzhen Hetao College — together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and Shenzhen Zhicheng AI Compute Platform — completed full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model on an Ascend 910C compute cluster.

Technical highlights:

• Among the world's first to run full-parameter post-training of a trillion-parameter model on a domestic compute platform
• Validates Ascend 910C maturity in ultra-large-model training
• Proves domestic AI chips now have the capability to replace imported chips

Performance data (official disclosure):

• Training throughput: ~60% of an H100 cluster (BF16 precision)
• Memory utilization: 92% (128GB HBM2E capacity advantage)
• Interconnect efficiency: 384-chip linear scaling efficiency 85%+
• Stability: 30 consecutive days of training with no failures

2.3 Commercial deployment cases​

Case 1: A provincial big-data center (300 P FLOPS compute center)​

• Scale: 300 P FLOPS AI compute (~1,000× 910C)
• Scenarios: government large model, city brain, smart transportation
• Deployment: September 2025
• Investment: ~¥200M (120 servers)

Case 2: Huawei Cloud AI training platform​

• Chips: over 10,000 Ascend 910C
• Customers served: over 500 enterprises
• Model support: Pangu large model, third-party open-source models (LLaMA, ChatGLM, etc.)
• Global deployment: China, Southeast Asia, Middle East, Latin America

Case 3: iFlytek smart education​

• Scale: 256 Ascend 910C
• Scenarios: smart-education large model, speech recognition, machine translation
• Performance: 90% faster training than 910B

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3. Performance Comparison Analysis​

3.1 vs. NVIDIA H100​

Item	Ascend 910C	NVIDIA H100	Notes
BF16 compute	800 TFLOPS	~1,300 TFLOPS	910C ~60% of H100
HBM capacity	128 GB	80 GB	910C +60%
HBM bandwidth	784 GB/s	3.35 TB/s	H100 clear bandwidth lead
TDP	310 W	700 W	910C only 45% of H100 power
Process	7nm (SMIC N+2)	4nm (TSMC)	H100 more advanced
Software ecosystem	CANN (CUDA-compatible)	CUDA	H100 more mature
Supply	China autonomous	Export-controlled	910C no supply-chain risk

Conclusion:

• In raw compute, 910C is ~60% of H100
• In memory capacity, 910C leads by 60%, suited to large-model training
• In energy efficiency, 910C clearly outperforms H100
• In supply chain security, 910C wins outright

3.2 vs. Ascend 910B​

Item	Ascend 910C	Ascend 910B	Improvement
Architecture	Dual-die Chiplet	Single die	—
BF16 compute	800 TFLOPS	~400 TFLOPS	+100%
HBM capacity	128 GB	64 GB	+100%
TDP	310 W	310 W	Flat (single-die power)
Process	SMIC N+2	SMIC N+2	Same
Yield	~40%	~30%	+33%

Conclusion:

• 910C's dual-die packaging doubles compute and memory capacity
• Yield up from 910B's 30% to 40%, lowering manufacturing cost
• At equal power, 100% performance gain, significantly better energy efficiency

3.3 Inference performance (DeepSeek measured)​

Test environment:

• Model: DeepSeek-V3 (671B parameters)
• Hardware: Ascend 910C vs NVIDIA H100
• Precision: BF16
• Batch size: 64

Results:

Metric	Ascend 910C	NVIDIA H100	Ratio
Inference speed (tokens/s)	8,500	14,200	60%
First-token latency (ms)	120	85	141%
Power (W)	310	700	44%
Cost (¥10k/card)	~10	~18	56%

Conclusion:

• 910C inference speed is 60% of H100, but power only 44%
• In cost-sensitive scenarios, 910C's cost-performance advantage is clear
• For China-market localization needs, 910C is the only option

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4. Market Positioning and Competitive Advantages​

4.1 Target markets​

Core markets:

1. Chinese government and SOEs: localization, data security, autonomy
2. Large-model startups: cost-sensitive, high compute demand
3. Operators and cloud providers: large-scale deployment, high efficiency requirements
4. Research and education: ultra-large-scale computing, talent development

Edge markets:

1. Autonomous driving: end-to-end large-model training
2. Smart healthcare: medical imaging, drug discovery
3. Fintech: risk control, robo-advisory

4.2 Competitive advantages​

Advantage	Description
Autonomy	SMIC N+2 process + Huawei in-house architecture, no supply-chain risk
Large memory	128GB HBM2E, full-pipeline training of hundred-billion-parameter models
High energy efficiency	310W TDP delivers 800 TFLOPS, close to H100 efficiency
System scaling	CloudMatrix 384 SuperNode, total compute exceeds GB200 NVL72
Software ecosystem	CANN CUDA-compatible, lower migration cost
Cost advantage	~¥100k/card, ~44% cheaper than H100

4.3 Weaknesses and improvement directions​

Weakness	Improvement direction
Single-chip compute	Next-gen 910D to adopt 3nm, target doubling
HBM bandwidth	950 series to adopt in-house HBM (HiBL 1.0), bandwidth to 4 TB/s
Software ecosystem	Continued CANN + MindSpore investment, expand developer community
Process	Deep cooperation with SMIC to ramp N+3 (5nm-class)

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5. 2026 Shipment Plan and Market Forecast​

5.1 Shipment plan​

Period	Shipments	Cumulative	Key customers
2025 Q2-Q4	200k	200k	Huawei Cloud, China Telecom
2026 Q1-Q2	300k	500k	China Mobile, China Unicom, iFlytek
2026 Q3-Q4	300k	800k	Government projects, large-model startups
2027	1,000k	1,800k	Global market (Southeast Asia, Middle East, Latin America)

Capacity bottleneck:

• SMIC N+2 capacity ~100k wafers/month, Ascend 910C ~30% of that
• 2026 plan of 800k chips needs ~400k wafers, requiring 80%+ utilization
• Huawei prioritizes 910C capacity via deep SMIC cooperation

5.2 Market forecast​

China AI chip market (2026):

• Total: ~¥50B
• Domestic share: ~35% (¥17.5B)
• Ascend 910C share: ~60% (¥10.5B, ~800k chips)

Global AI chip market (2026):

• Total: ~$200B
• Huawei share: ~5% ($10B)
• Growth drivers: China-market localization + Belt and Road exports

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6. Summary and Outlook​

6.1 Core conclusions​

1. Ascend 910C is a milestone domestic AI chip, with comprehensive breakthroughs in compute, memory, energy efficiency, and system scaling
2. CloudMatrix 384 SuperNode proves domestic chips can replace imported ones
3. DeepSeek-V4-Pro training success validates 910C maturity in ultra-large-model training
4. 800k chips shipped in 2026, projected 60% of China's AI chip market

6.2 Future outlook​

Short term (2026-2027):

• 910C continues ramping, shipments exceed 1,000k
• CloudMatrix 384 deployments over 1,000 units
• Software ecosystem (CANN + MindSpore) maturity approaches 70% of CUDA

Medium term (2028-2029):

• Next-gen 910D mass production, 3nm process, target 1.6 PFLOPS BF16
• 950 series (PR/DT) becomes inference-market mainstay, share over 30%
• 960/970 launch, N+3 process, supports trillion-parameter models

Long term (2030+):

• Huawei Ascend series becomes TOP 3 of the global AI chip market
• Domestic AI chips exceed 20% of the global market
• Transition from "following" to "running alongside" to "leading"

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References​

1. Huawei Ascend 910C — Baidu Baike
2. Huawei Ascend series AI chip detailed parameter comparison (2025-2028) — EET-China
3. Huawei Ascend 910C compute cluster powers domestic chip's successful trillion-scale AI large-model training — QQ News
4. Huawei Ascend 910C completes DeepSeek V4 Pro training — Huxiu
5. Huawei Ascend 910C measured efficiency surpasses H100, AI Infra software-hardware co-optimization shines at ten-thousand-card cluster — CNBlogs

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Last updated: June 10, 2026

June 1-5, 2026, Taipei — Computex 2026 (Taipei International Information Technology Show) wrapped up successfully this week. With the theme "AI Together," industry giants including NVIDIA, Intel, AMD, and Qualcomm unveiled numerous AI compute products in rapid succession. Below, MirrorFrog brings you a roundup of the most noteworthy developments in the compute card space this week.

① NVIDIA DGX Station for Windows: A Desktop AI Supercomputer​

NVIDIA officially launched the DGX Station for Windows during its Computex 2026 keynote, calling it "the world's most powerful desktop AI supercomputer."

Core Specifications​

Item	Specification
Chip	GB300 Grace Blackwell Ultra Desktop Superchip
GPU Memory	252 GB HBM3e (7.1 TB/s)
CPU Memory	496 GB LPDDR5X (396 GB/s)
Unified Memory	748 GB (NVLink-C2C interconnect)
FP4 Compute	20 PFLOPS (sparse)
FP8 Compute	10 PFLOPS (sparse)
Network	ConnectX-8 SuperNIC, up to 800 Gb/s
Model Capacity	Can run 1 trillion parameter models
System Power	1,600 W
Operating System	Microsoft Windows
Shipping	Q4 2026

Significance: DGX Station compresses AI compute power (20 PFLOPS FP4) that previously required datacenter-class clusters into a single desktop workstation. 748GB of unified memory means developers can run models with hundreds of billions or even trillions of parameters locally, without cloud dependency.

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② Intel Crescent Island: Inference-Specialized AI GPU​

At Computex, Intel disclosed detailed specifications for its next-generation datacenter AI inference GPU, Crescent Island.

Item	Specification
Memory	Up to 480 GB LPDDR5x
Power	350 W (PCIe form factor)
Precision Support	FP4/MXFP4 → FP64 (full precision coverage)
Target	AI inference workloads (Agentic Inference)
Positioning	Better price-performance than HBM solutions
Shipping	H2 2026

Significance: Crescent Island represents Intel's key strategic move in the AI inference market. 480GB of massive LPDDR5x memory (non-HBM) means significantly lower cost compared to NVIDIA H200/B200 and other competing products, targeting enterprise inference deployment scenarios.

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③ Intel Xeon 6+ (Clearwater Forest): First Intel 18A Datacenter CPU​

Intel also unveiled the new Xeon 6+ processor, codenamed Clearwater Forest, its first datacenter CPU built on the 18A process:

• 288 Darkmont architecture cores
• L2 288MB + L3 576MB cache
• 12-channel DDR5-8000 memory
• Foveros Direct 3D advanced packaging
• AI Agent Era: CPU returns to the center of infrastructure

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④ NVIDIA RTX Spark Ecosystem Takes Shape​

This week, the RTX Spark super chip developed in collaboration between NVIDIA and MediaTek continued to generate buzz. Multiple OEMs showcased RTX Spark-based laptop and compact desktop prototypes:

• ASUS, Dell, HP, Lenovo, Microsoft Surface, MSI all confirmed as launch partners
• Equipped with 20-core Grace CPU + Blackwell GPU (6144 CUDA cores)
• AI compute 1 PFLOPS
• Retail availability Fall 2026

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⑤ Intel × Foxconn AI Infrastructure Partnership​

Intel and Foxconn announced a joint AI infrastructure initiative, covering the complete chain from chip → server → rack-scale system, targeting the datacenter market opportunity driven by surging AI inference demand.

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⑥ Domestic AI Chip Developments​

According to the IDC 2025 annual report, total AI accelerator card shipments in China reached approximately 4 million units, with domestic vendors shipping approximately 1.65 million units, capturing a market share exceeding 41%. Huawei's Ascend 950 series has entered mass production and delivery, while Cambricon's MLU690 has begun shipping to internet customers.

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This Week's Compute Roundup​

Vendor	Product	Highlight	Timeline
NVIDIA	DGX Station for Windows	20 PFLOPS, 748GB unified memory	Q4 2026
NVIDIA	RTX Spark	1 PFLOPS AI PC chip	Fall 2026
Intel	Crescent Island GPU	480GB LPDDR5x, 350W	H2 2026
Intel	Xeon 6+ (Clearwater Forest)	288 cores, Intel 18A	H2 2026
Intel + Foxconn	AI infrastructure partnership	Chip→rack full chain	Strategic partnership
Huawei	Ascend 950PR/DT	1 PFLOPS FP8, self-developed HBM	In mass production
Cambricon	MLU690	2 PFLOPS FP8, 192GB HBM3E	Shipping

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Sources: NVIDIA GTC Taipei 2026 / Computex 2026 official announcements, Intel press releases, ifeng Tech, IT Home.

June 2026 — Huawei's Ascend 950 series (950PR / 950DT) has entered formal mass production and delivery, a landmark event for China's AI chip industry in 2026. Meanwhile, Cambricon's MLU690 has begun shipping and Moore Threads has announced MTT S5000 specifications, formally establishing China's tri-polar AI chip landscape.

Ascend 950 Series: A Historic Breakthrough with Self-Developed HBM​

Huawei HiSilicon's Ascend 950 series is the fourth-generation Ascend AI chip, first revealed at Huawei Connect 2025 in September and entering mass production in Q1 2026.

950PR (Prefill Inference Specialized)​

Item	Specification
Architecture	Da Vinci v5 (SIMD + SIMT dual-model)
Process	N+2 (SMIC domestic)
HBM	HiBL 1.0 (Huawei self-developed) , 128 GB
FP8 Compute	1 PFLOPS (HiF8 format)
TDP	~400 W
Target	Inference Prefill (video recommendation, real-time interaction)

950DT (Decode + Training Specialized)​

Item	Specification
Architecture	Da Vinci v5 (SIMD + SIMT dual-model)
Process	N+2 (SMIC domestic)
HBM	HiZQ 2.0 (Huawei self-developed) , 144 GB, 4 TB/s
FP8 Compute	1 PFLOPS (HiF8 format)
TDP	~500 W
Target	Inference Decode + Model Training

Historical Significance​

Self-developed HBM (HiBL 1.0 / HiZQ 2.0) represents the most important technical breakthrough of Huawei Ascend 950 — this is the first time a Chinese enterprise has achieved self-developed mass production of HBM memory, completely eliminating dependence on SK Hynix / Samsung HBM supply. Combined with the domestic N+2 process, Ascend 950 has achieved full-chain domestic production from HBM → Compute Die → Packaging → System.

Cambricon MLU690: China's Only Native FP8 Support​

Cambricon's seventh-generation AI chip MLU 690 (Siyuan 690) began volume production and shipping in H1 2026. This is the first domestic AI chip with native FP8 precision support.

Item	MLU 690
Process	5nm (TSMC / SMIC)
FP8 dense	2 PFLOPS
HBM	192GB HBM3E, 5 TB/s
TDP	~500 W
Unit Price (OAM)	~$8,000-12,000

MLU 690's FP8 compute power (2 PFLOPS dense) is on paper comparable to NVIDIA Blackwell (B200 FP8 4.5 PFLOPS sparse). Leveraging its financing advantage as a STAR Market listed company, Cambricon targets 2026 revenue of ¥15-20B (2025: ¥7.2B).

Moore Threads MTT S5000: From Graphics to Training-Inference Unified​

Moore Threads publicly disclosed detailed specifications of the MTT S5000 in February 2026, featuring the fourth-generation MUSA "Pinghu" architecture, single-card AI compute of 1,000 TFLOPS, 80GB GDDR6X memory, 1.6 TB/s bandwidth.

Moore Threads pursues a full-function GPU path (graphics rendering + AI compute + general-purpose compute), closest to NVIDIA's strategy. The founding team comes from former NVIDIA China, and the MUSIFY toolchain helps auto-migrate CUDA code to the MUSA platform, lowering ecosystem migration costs.

China's Tri-Polar AI Chip Landscape​

Dimension	Huawei Ascend	Cambricon	Moore Threads
Core Architecture	Da Vinci v5	MLUv07	MUSA 4th Gen
Process	N+2 domestic	5nm	6nm
FP8 Compute	~1 PFLOPS	2 PFLOPS	0.5 PFLOPS (estimated)
HBM Self-Sufficiency	✅ Self-developed HiBL/HiZQ	❌ Purchased	❌ Purchased
Ecosystem	CANN + MindSpore	NeuWare + MindSpore	MUSA + MUSIFY
Advantage	Full-chain domestic	Highest FP8 compute	Full-function + CUDA migration
2025 Revenue	(Huawei internal)	¥7.2B	¥2.2B

Global Market Comparison (Q2 2026 Update)​

Tier	Vendor	Flagship Chip	FP8/PFLOPS	HBM	Mass Production
Tier 1	NVIDIA	Rubin R200	25 PF (sparse)	288GB HBM4	2026 H2
Tier 2	AMD	MI400	20 PF (dense)	432GB HBM4	2026
	Huawei	Ascend 950DT	1 PF (dense)	144GB self-developed HBM	2026 Q1
	Cambricon	MLU690	2 PF (dense)	192GB HBM3E	2026 H1
	AWS	Trainium 3	5.7 PF (dense)	144GB HBM	2025 Q4 GA
Tier 3	Intel	Gaudi 3	1.8 PF	128GB HBM2e	In production
	Google	TPU v7	4.6 PF(TFLOPS)	192GB HBM	2025
	Moore Threads	MTT S5000	1 PF	80GB GDDR6X	2025 Q1

Note: NVIDIA uses sparse compute as standard, while AMD / Huawei / Cambricon use dense — not directly comparable.

Outlook for H2 2026​

• NVIDIA Rubin R200: Official shipment in H2 2026, 288GB HBM4, 6-chip CoWoS-L packaging
• Huawei Ascend 960: Roadmap H2 2027, expected FP8 compute doubled to 2 PFLOPS
• Cambricon MLU790: Expected 2027, 3nm, 384GB HBM4, 2.5 PFLOPS
• Moore Threads: Next-gen GPU expected with HBM3, 2× MTT S5000 compute

By 2026, China's AI chip industry has formed a complete product matrix from Training (Cambricon MLU690 / Ascend 950DT) → Inference (Ascend 950PR / Moore Threads S5000) → Systems (CloudMatrix / Distributed Clusters).

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This article is based on public information from Huawei Connect 2025 (2025-09-18), industry analysis reports from April 2026, and the latest market data as of June 2026.

June 1, 2026, Taipei — During the Computex 2026 opening keynote, NVIDIA CEO Jensen Huang officially unveiled the RTX Spark super chip, marking NVIDIA's formal entry into the personal computer processor market dominated by Intel, AMD, Qualcomm, and Apple.

RTX Spark: The "Heart" of the Personal AI Computer​

RTX Spark was developed in collaboration between NVIDIA and MediaTek, featuring a heterogeneous package with a 20-core Grace CPU + Blackwell RTX GPU, equipped with 6144 CUDA cores. AI compute reaches 1 PFLOPS (one quadrillion floating-point operations per second), meaning personal computers now possess computing power comparable to a datacenter-class H100 GPU for the first time.

Specification	RTX Spark
CPU	20-core Grace (MediaTek collaboration, Arm architecture)
GPU	Blackwell RTX (6144 CUDA cores)
AI Compute	1 PFLOPS
Target	Personal AI Agent, local LLM inference
Launch OEMs	ASUS, Dell, HP, Lenovo, Microsoft Surface, MSI
Availability	Fall 2026
Form Factor	Laptop SoC + compact desktop workstation

Jensen Huang's "Full-Stack AI" Strategy​

The launch of RTX Spark is a key step in NVIDIA's "full-stack AI" strategy. Jensen Huang stated during the keynote: "AI should not only run in the cloud. Everyone's computer should have the ability to run AI agents."

RTX Spark transforms NVIDIA from a datacenter GPU monopolist into a full competitor in the personal computing market. Following the announcement, shares of AMD, Intel, and Qualcomm fell accordingly.

Market Impact​

• Intel: Personal computer AI processor business faces direct threat
• AMD: Ryzen AI series must compete at the same level
• Qualcomm: Snapdragon X Elite's Copilot+ PC positioning challenged
• Apple: M-series chips are no longer the only high-performance AI PC option

Vera Rubin Platform Enters Full Mass Production​

During the same keynote, Jensen Huang also announced that the NVIDIA Vera Rubin platform has entered full mass production. Rubin R200 features a 6-chip CoWoS-L package (1× Vera CPU + 2× Rubin GPU die + I/O/HBM die), equipped with 288GB HBM4, 22 TB/s bandwidth, and 50 PFLOPS FP4 compute (sparse).

The Rubin NVL72 rack (72 Rubin GPUs + 36 Vera CPUs) will begin shipping in H2 2026.

Other Highlights from Computex 2026​

• AMD: Showcased the MI350 series (192GB HBM3e, 5 PFLOPS FP8 dense), officially launching in June
• Intel: Jaguar Shores publicly unveiled for the first time
• Qualcomm: AI 200 / 300 series inference card roadmap updated
• Domestic AI Chip Zone: Huawei, Cambricon, Moore Threads, and others showcased their latest products

Industry Significance​

The launch of RTX Spark means AI compute is no longer confined to datacenters. Individual developers, designers, and researchers will be able to run large model tasks locally that previously required cloud GPUs, potentially redefining the market landscape for personal AI computing.

The mass production of Vera Rubin further consolidates NVIDIA's absolute leadership in datacenter AI training. Together, both product lines form NVIDIA's full-stack AI computing landscape of "cloud training + personal inference."

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This report is based on official NVIDIA announcements from Computex 2026 / GTC Taipei on June 1, 2026.