32 posts tagged with "AI Compute"

当所有人盯着 Rubin R200 的 50 PFLOPS FP4 时，真正决定这台机器推理经济性的，可能是一颗 CPU。Vera——NVIDIA 首次全面自研核心的数据中心 CPU，用 88 个 Olympus 核心、第二代 SCF 一致性结构和 1.5TB LPDDR5X，重新定义了"AI 工厂的主机处理器"。本文依据站内芯片数据库与智能体基准实测，拆解 NVIDIA 从外购 Arm 核到自研 SCF 的演进逻辑。

从 Grace 到 Vera：自研之路的三级跳​

NVIDIA 的 CPU 战略经历了三个阶段：GH200/GB200 时代的 Grace CPU 基于 72 核 Neoverse V2 公版 Arm 核心，本质是"外购核心 + 自研互联"；GB300 延续了这一代 Grace；而 2026 年 GTC 发布的 Vera 则完成质变——核心、片上互连、内存子系统全部自研。据站内芯片数据库，Vera 的核心规格如下：

规格	参数
CPU 架构	ARM 架构（自研 Olympus 核心）
指令集	ARMv9.2（完全兼容）
核心数量	88 个 Olympus 核心
线程数量	176 个线程（空间多线程）
单核性能	前代产品的 2 倍
最大内存容量	1.5 TB（LPDDR5X）
内存带宽	1.2 TB/s
互联技术	NVLink-C2C（1.8 TB/s）
片上互连	第二代 SCF（3.4 TB/s 对分带宽）
发布时间	2026 年 3 月 17 日
量产时间	2026 年下半年

SCF：88 核无延迟扩展的底座​

SCF（Scalable Coherency Fabric，可扩展一致性结构）是 Vera 最值得细看的技术。第二代 SCF 提供 3.4 TB/s 对分带宽，采用片上网格 + 统一缓存设计，可无延迟扩展 88 个核心。

对分带宽（bisection bandwidth）是衡量片上互连质量的关键指标：它表示把芯片切成两半时，两半之间的总通信带宽。88 核的大芯片如果对分带宽不足，核心越多内耗越大。第二代 SCF 用网格拓扑让任意核心间的通信路径趋于均匀，配合统一缓存避免一致性流量的长距离穿梭——这正是 Vera 敢于采用单体计算芯片设计（而非多小芯片拼接）的底气：避免跨小芯片通信延迟，在所有核心满载时保持稳定延迟和吞吐量，性能可预测性强。

1.5TB LPDDR5X：把内存子系统当主武器​

Vera 将 SCF 与高达 1.5TB 的 LPDDR5X 内存子系统结合。对比上一代 Grace 的规格变化一目了然：

指标	Grace（GB200/GB300）	Vera	提升
内存容量	480GB LPDDR5X	最高 1.5TB LPDDR5X	约 3 倍
内存带宽	512 GB/s	1.2 TB/s	约 2.3 倍
CPU-GPU 互联	NV-HBI 900 GB/s	NVLink-C2C 1.8 TB/s	2 倍
核心数	72 核 Neoverse V2	88 核 Olympus	+22%

更关键的是系统级设计：LPDDR5X 与 GPU 的 HBM4 可视为单一一致性内存池。这意味着数据不再需要在"CPU 内存"和"显存"之间显式搬运，两个物理上分离的内存子系统在软件视角下是一体的。对推理业务，这带来两个直接收益：KV 缓存卸载——不常用的注意力上下文可以下沉到 LPDDR5X 侧，把昂贵的 HBM4 带宽留给热点数据；多模型高效执行——多个模型实例共享同一内存池，切换与加载开销大幅降低。

Daytona 实测：智能体时代的 CPU 门槛​

2026 年 10 月 10 日公布的 Daytona 智能体基准测试，给 Vera 的实际能力提供了量化注脚。智能体负载的特点是海量并发沙盒的创建与销毁——恰恰考验 CPU 的内存容量、一致性与调度效率：

测试项	Vera	AMD EPYC 9755	差距
1000 沙盒上线	10.8 秒	88.4 秒	约 8 倍
峰值智能体任务吞吐	13.3 任务/秒	—	—
2000 沙盒上线	27.4 秒	—	—

8 倍的沙盒上线速度差距说明：智能体负载对 CPU 的要求已与通用计算分道扬镳——容量大（1.5TB 装下海量沙盒状态）、带宽高（1.2TB/s 喂饱并发）、一致性结构强（88 核高效协作）。站内芯片数据库同时记录，Vera 的软件环境运行速度相比传统架构 CPU 提升最高 50%，满负载下强化学习评估周期可缩短 50%。

与 Groq 3 LPX 的异构分工​

Vera 所在的 Rubin 平台还有一位非常规队友：NVIDIA 收购 Groq 后推出的 Groq 3 LPX。据站内芯片数据库，LPX 机架集成 256 颗 LPU，聚合 128GB 片上 SRAM，聚合带宽高达 40 PB/s，官方口径的能效优势显著（35× perf/W vs H100 推理）。在 Rubin 平台的分工中，GPU 承担训练与 prefill，Groq 3 LPX 专攻智能体解码阶段的低延迟输出——而 Vera 则是这一切的调度中枢。prefill 吃算力、decode 吃带宽、调度吃一致性与容量，三种负载由三种架构分别消化，这正是"每 token 经济学"推导出的异构架构必然性。

Vera vs EPYC Venice：服务器 CPU 的新战场​

Vera 的出现让 NVIDIA 与 AMD 在服务器 CPU 领域正面相遇。据站内芯片数据库，AMD EPYC Venice（2026 CES 发布）是全球首款 2nm 数据中心 CPU：

指标	NVIDIA Vera	AMD EPYC Venice（Zen 6C）
核心	88 个自研 Olympus	最多 256 个 Zen 6C
制程	未公开	台积电 2nm（N2）
内存	1.5TB LPDDR5X	16 通道 DDR5
单路带宽	1.2 TB/s	1.6 TB/s
L3 缓存	—	1GB
卖点	NVLink-C2C、CPU-GPU 一致性	通用性、x86 生态

两者的定位差异明显：EPYC Venice 是通用数据中心 CPU 的极致（256 核、x86 生态、Helios 机架中与 MI455X 组队），而 Vera 是 AI 专用 CPU——它不做通用服务器生意，只为 AI 工厂的主机负载优化。Vera 甚至支持硬件级 FP8 计算，是全球首款支持 FP8 精度的 CPU，并支持全机密计算的硬件级安全隔离。竞争的天平取决于一个问题：AI 工厂的 CPU 采购，会不会整体从通用服务器预算中剥离？如果会，Vera 绑定 Rubin GPU 的销售模式将是护城河；如果不会，EPYC 的生态广度仍难撼动。

小结​

Vera CPU 标志着 NVIDIA 完成了从"用别人的核心攒超级芯片"到"自研全套主机平台"的跃迁：SCF 的 3.4TB/s 对分带宽解决了 88 核扩展难题，1.5TB LPDDR5X 与 HBM4 构成的一致性内存池重构了推理数据流，Daytona 实测的 8 倍沙盒优势则证明智能体负载确实需要一颗不一样的 CPU。它的野心不在挑战 x86 的通用服务器王座，而是重新划定一条边界——AI 基础设施中，CPU 是 GPU 子系统的一部分，而不是独立采购的商品。这条边界能否成立，将决定未来五年服务器市场的版图。

文本生成的算力曲线尚未见顶，视频生成已经带着二次方的注意力复杂度闯入算力市场。当世界模型开始学习物理规律并支持实时交互，推理算力的需求边界将被重新定义——下一个算力黑洞，正在视野中成形。

单秒成本背后的算力真相​

2026 年，视频生成已形成清晰的商业化定价梯度。据公开资料整理：

模型	定价（每秒生成视频）	主要特性
Sora 2	约 0.10 至 0.15 美元	1080p、原生音频
Sora 2 Pro	0.30 至 0.50 美元	更长时长、更高分辨率
Veo 3.1	约 0.40 美元	原生音频、4K 上采样
可灵 3.0	0.10 至 0.75 美元	国产梯队代表，长时长可扩展
开源自托管（Wan 2.6 等）	硬件摊销后显著更低	需自行承担 GPU 与运维成本

低价表象之下是沉重的算力账单。按每秒 24 帧计算，一段 10 秒 1080p 视频意味着 240 帧高度关联的图像，时序注意力机制使显存需求随时长呈二次方增长——30 秒片段要处理的帧间关联对数以十万计。业界分析普遍估计，训练一个 Sora 2、Veo 3 级别的视频模型，仅算力投入就普遍在 5000 万美元以上，叠加数据授权、标注与安全评审，整体项目投入据估可达 1.5 亿至 4 亿美元。算一笔直观的账：一个每月生成百万秒级视频的消费级应用，即便采用较低价位档，月度 API 账单也能轻松超过 10 万美元。

自托管与开源的博弈​

开源模型正在改变成本结构。阿里的 Wan 系列与腾讯的 HunyuanVideo 已把"自己搭"变为可行选项：Wan 系列的 14B 生产级版本约需 48GB 到 80GB 显存才能流畅批量推理，HunyuanVideo 13B 版本官方推荐 H100 80GB 级别配置。对月产数十万条短视频的应用而言，API 计费与自建集群的成本平衡点，正成为技术路线的核心决策。而中国厂商在国产加速器与低电价环境下的成本优势，使国产视频模型在单位经济学上占据独特位置——可灵、海螺等产品的低价正是这一优势的直接体现。

世界模型：从生成到模拟​

比视频生成更重的，是世界模型。当模型不仅生成画面，还要内化物理规律、支持交互式探索时，算力需求呈台阶式跃迁：实时交互要求生成延迟低到毫秒级；世界一致性要求超长时序记忆与状态追踪；具身智能训练要求大规模仿真并行运行。视频生成考验的是"把序列算对"，世界模型考验的是"把世界算懂"——后者的状态空间与计算密度高出一个量级。业界普遍预期，一旦世界模型成为智能体与机器人训练的基础设施，其推理负载将远超今天的文本推理。

结语：为黑洞做好电力与芯片准备​

视频生成与世界模型对算力产业的意义，在于它们同时吃掉带宽、显存、互连这三样最贵的资源——这恰好解释了 HBM 扩产、超节点与液冷在 2026 年同步爆发的产业节奏。对芯片厂商而言，谁能把每瓦 tokens 产出做到极致、把视频推理流水线优化到物理极限，谁就能在下一个算力黑洞周围占据最有利的位置。而对整个行业，唯一确定的是：生成一秒钟的智能，永远比生成一个字贵得多，而且这个差距还会继续拉大。

在旧金山举行的微软 Windows AI 与 Surface 活动上，NVIDIA 一手开启 RTX Spark 笔记本预订，一手预览 DGX Station for Windows——从 1 PFLOP FP4 的笔记本到 20 PFLOPS FP4 的桌面工作站，AI 算力正在从数据中心一路铺到办公桌。

RTX Spark 笔记本正式开订​

在微软于旧金山举行的 Windows AI 与 Surface 活动上，NVIDIA 宣布 RTX Spark 笔记本正式开启预订，首批产品将于 10 月 16 日（周五）发货；紧凑型桌面产品则计划在 11 月跟进上市。

OEM 阵容覆盖了几乎所有主流 PC 品牌：Acer、ASUS、Dell、HP、Lenovo、Microsoft（Surface Laptop Ultra）、MSI、Gigabyte 全部在列。从发布即有如此完整的品牌背书来看，RTX Spark 显然不是一款演示性产品，而是要成长为一个完整的终端新品类。

Blackwell RTX + Grace CPU：数据中心架构下沉终端​

RTX Spark 的硬件方案可以概括为"把 Grace Blackwell 的思路压缩进 PC"：

• GPU：基于 Blackwell 架构的 RTX GPU，最高 6144 个 CUDA 核心；
• CPU：最多 20 核的 Grace CPU；
• 互联：CPU 与 GPU 之间提供 600 GB/s 高速链路；
• 算力：最高 1 PFLOP FP4；
• 内存：最高 128GB 统一内存，CPU 与 GPU 共享同一内存池；
• 软件：运行完整 CUDA 栈。

其中"统一内存 + 完整 CUDA 栈"是两个关键点：前者决定了本地能装下多大的模型，后者决定了云端训练的代码可以低成本迁移到本地调试，开发者不必为桌面场景另学一套工具链。

DGX Station for Windows 首次预览​

如果说 RTX Spark 面向个人开发者，那么同场预览的 DGX Station for Windows 则瞄准了更高一层的需求。它基于 GB300 Grace Blackwell Ultra Desktop Superchip，拥有 748GB 一致性内存，算力最高可达 20 PFLOPS FP4，目标是让用户在本地运行约 1 万亿参数的模型。

对 Linux 生态的兼容也给出了务实答案：Linux 工具链可以通过 WSL（Windows Subsystem for Linux）访问。DGX Station for Windows 将于 Q4 上市，由 ASUS、Dell、HP、Lenovo 四家推出。

Surface Laptop Ultra 与内存挤压隐忧​

作为活动的另一主角，Surface Laptop Ultra 已于 10 月 7 日开启预订，最高配备 128GB 统一内存——这个容量已经接近入门级推理服务器的水平。

但 DIGITIMES 提出了一个不容忽视的问题：AI PC 的内存供给正在被服务器需求挤压。在内存厂商的优先级排序中，服务器 DRAM 需求被放在首位，AI PC 依赖的 LPDDR5X 供给承压。在存储供应紧张的背景下，128GB 统一内存的 AI PC 能否稳定供货，本身就是一个变数。

从云端到桌面的算力分层​

把 NVIDIA 目前的桌面产品线摆在一起，可以清晰看到一条算力分层路线：

产品	形态	关键规格	定位
DGX Spark	桌面 AI 超算	64GB 统一内存、1 PFLOP FP4	4,999 美元，个人与小团队原型验证
RTX Spark 笔记本	笔记本	最高 6144 CUDA 核心 + 最多 20 核 Grace CPU、最高 128GB 统一内存	随身开发与调试
DGX Station for Windows	桌面工作站	GB300 Grace Blackwell Ultra Desktop Superchip、748GB 一致性内存、最高 20 PFLOPS FP4	本地运行约 1 万亿参数模型

这条路线的逻辑是：云端负责大规模训练与生产推理，桌面负责原型验证、微调与敏感数据场景，笔记本负责日常开发与演示。当模型越做越大、数据合规要求越来越严，"把算力放在身边"的价值正在上升。

Windows CUDA 原生化与 WSL 的务实路线​

过去十几年，CUDA 的主战场在 Linux 服务器上，Windows 开发者在工具链上长期处于跟随位置。RTX Spark 与 DGX Station for Windows 意味着完整 CUDA 栈第一次以原生姿态大规模进入 Windows 桌面场景。

而 WSL 桥接 Linux 工具链的安排，则是一种典型的务实路线：既照顾 Windows 用户的使用习惯，又不要求现有 Linux 工作流推倒重来。对于在 Windows 环境中做模型开发和内部工具的企业开发者来说，迁移成本被明显降低；对 NVIDIA 而言，这等于把整个 CUDA 开发者生态延伸到了全球存量最大的桌面操作系统上。

小结​

RTX Spark 笔记本开订与 DGX Station for Windows 预览，标志着 NVIDIA 把 AI 算力的故事延伸到了最后一米：从数据中心，到桌面工作站，再到背包里的笔记本。1 PFLOP FP4 到 20 PFLOPS FP4 的分层算力、128GB 到 748GB 的统一内存、WSL 桥接的 Linux 工具链，共同构成了一条完整的桌面 AI 开发路径。剩下的悬念有两个：一是 LPDDR5X 供给紧张会不会卡住 AI PC 的出货节奏，二是 11 月的紧凑型桌面和 Q4 上市的 DGX Station 能否如期落地。

2026年第41周（9月28日—10月6日前后），AI芯片行业密集事件爆发：NVIDIA N1X冲击PC市场、Intel年内第三次涨价、AMD Helios量产、MLPerf新纪录、存储新范式、国产涨价与上市潮。本篇按国际、国产、存储与系统、资本与市场四节汇总。

国际动态​

NVIDIA N1X发布（10-04）：NVIDIA发布N1X PC处理器，直接竞争Intel与AMD的PC处理器市场，当日两家股价各下跌4.2%。N1X基于RTX Spark芯片、与微软合作打造，2026年秋季上市。

Intel CPU涨价10%（10-05生效）：这是Intel自2025年以来的第三次涨价，受AI需求和产能紧张驱动。

AMD Helios量产（9-18报道）：MI455X首批出货目标Q3末，OpenAI 6GW、Meta 6GW、Anthropic合作兑现中，微软为首批客户之一。

MLPerf Inference v6.1（9-16）：Vera Rubin NVL72首秀，跑Qwen3-VL较GB300最高提升3.7倍；AMD MI350以512卡创下575万tokens/秒的纪录。

事件	时间	要点
N1X发布	10-04	Intel/AMD股价各跌4.2%，2026秋季上市
Intel涨价10%	10-05生效	年内第三次涨价
Helios量产	9-18报道	MI455X首批Q3末出货
MLPerf v6.1	9-16	Rubin NVL72较GB300最高3.7倍

国产动态​

华为昇腾950：智算集群云服务9月30日国内商用，11月30日全球商用；昇腾960超节点引入NPO技术、支持4096卡、提供8E FP8算力。

平头哥真武V900（9-22云栖大会）：216GB显存、1200GB/s带宽，2027年Q1量产；同期发布倚天720/730 CPU路线图。

国产芯片涨价（路透）：寒武纪690与昇腾950DT涨价20%-50%，HBM成本上涨是主要驱动。

燧原科创板上市（9-11）：开盘上涨188.37%，市值达1764亿元。

摩尔线程"庐山"：年底亮相，3A渲染性能提升15倍、光追50倍、AI 64倍。

存储与系统​

SK海力士：9月17日发布HBF/PIM/eSSD/SALT-KV组合，9月18日成立SK hynix Ventures投资生态；美光9月15日发布超密度服务器内存模组；AWS Annapurna×NVIDIA推进NVHBM定制内存；长鑫存储据路透报道筹备进军NAND。

电网与能效：Emerald AI、Google、NVIDIA于9月16日成立AEMA（先进能源与算力联盟）；NVIDIA DSX MaxLPS助力Lambda实现同功率下token吞吐+24%、每瓦性能+23%。

存储玩家	动作
SK海力士	HBF/PIM/eSSD/SALT-KV + 设立Ventures
美光	超密度服务器内存模组
AWS×NVIDIA	NVHBM定制内存
长鑫存储	筹备进军NAND

资本与市场​

份额格局：据Counterpoint口径，国产AI芯片从2022年的近乎零份额，到2025年已达41%；其中华为昇腾约占国产市场的62%。

股价与估值：同期美股芯片板块上涨，NVIDIA收涨2.54%、AMD涨超6%。

下周关注​

1. 昇腾950云服务全球商用倒计时：11月30日全球商用节点临近，海外部署进展值得跟踪；
2. Helios首批交付：MI455X能否兑现Q3末首批出货目标；
3. Q4国产新卡发布窗口：年底前后国产厂商新品密集期，摩尔线程"庐山"亮相在即。

小结​

第41周的主线是"三重加速"：算力侧（N1X、Helios、MLPerf新纪录）节奏空前，存储侧（HBF、NVHBM、SALT-KV）范式更新，供给侧（Intel涨价、国产涨价20%-50%）紧张加剧。国产份额41%的数据说明格局重塑已在发生，Q4将是验证兑现能力的关键窗口。

当算力的计量单位从"多少张卡"变成"多少吉瓦"，AI竞争的本质已经改变：大模型公司正在变成"能源公司+基建公司+模型公司"的三位一体。

5GW与10GW：新计量单位的诞生​

2026年9月的行业报道显示，AI算力竞赛进入了一个全新的量级：Anthropic的目标是在今年年底拥有约5GW的可用算力，而OpenAI明年的规划则是约10GW。

这两个数字意味着什么？5GW大致相当于数百万张高性能GPU同时满负荷运转所需的电力，而10GW已经接近一座大型核电站的装机容量。就在一年前，行业讨论的还是"十万卡集群"；如今，头部玩家谈论的是吉瓦级园区。算力竞赛的计量单位，已经从GPU的数量彻底转向了电力的功率。

从"买卡"到"买电厂"​

这种变迁背后，是AI产业价值链的整体上移：

• 能源成为第一约束。先进AI芯片供应在改善，但变电站、输电线路和发电容量的建设周期以年计。谁拿到电力指标，谁就拿到训练下一代模型的入场券。
• 基建能力成为核心竞争力。数据中心不再是租用IDC机房那么简单，而是涉及选址、并网、冷却系统乃至自有发电能力的系统工程。
• 模型公司与芯片公司深度绑定。OpenAI与博通合作开发Jalapeño自研芯片，并规划多吉瓦级部署，这已经不是"采购算力"，而是"定制算力供应链"。

20-30MW小数据中心为何成为抢手货​

一个耐人寻味的细节是：Anthropic和OpenAI两家还在争抢20-30MW级别的小型数据中心，Anthropic甚至向SpaceX租用算力。

原因很直接——大容量数据中心从规划到投运周期太长，而模型训练和推理需求等不起。20-30MW的小站点虽然容量有限，但胜在可快速拿容量：现有楼宇改造、电力接口现成、数月内即可上线。对于急需算力缺口的大模型公司，这批"小快灵"资源成了战略物资，甚至在二级市场上被反复转租、溢价争夺。向SpaceX租算力则更为激进——当地面电力不够快时，头部玩家已经开始评估包括星载算力在内的非常规选项。

算力军备竞赛的经济账​

这场竞赛的规模有多大？根据Bain 2026技术报告的口径，AI硬件市场2025年约为312.1亿美元，2026年预计达到384.9亿美元。而吉瓦级算力园区背后，是单笔动辄数十亿美元级别的芯片采购与多年期电力合约。

算力的本质正在从"IT设备"变成"重资产基础设施"——它的融资方式（项目融资、长期租约）、回报模型（算力利用率、每token成本）都越来越像电厂和通信网络，而不是服务器机房。

对AI芯片厂商意味着什么​

吉瓦级竞赛重塑了芯片厂商的客户结构，谁绑定大客户谁受益的格局愈发清晰：

厂商	核心绑定关系	算力绑定规模
NVIDIA	微软 / OpenAI	深度绑定OpenAI，吉瓦级部署主力供应商
AMD	OpenAI / Meta / Anthropic	OpenAI 6GW、Meta 6GW、Anthropic（多年期协议）
OpenAI（自研）	博通合作Jalapeño	多吉瓦级部署规划
云厂商自研	AWS Trainium、Google TPU等	服务自有平台负载

对芯片厂商而言，这带来两个深远影响：其一，订单变得极度集中，一张吉瓦级订单足以改变一家芯片公司的营收曲线，NVIDIA与AMD过去一年股价的分化某种程度上就是绑定关系的映射；其二，芯片设计开始围绕客户的电力预算优化，每瓦性能取代峰值算力成为核心指标——因为客户的稀缺资源不是芯片，而是那几吉瓦的电。

小结​

5GW和10GW不只是两个数字，它们标志着AI竞争进入了"基建时代"：电力取代芯片成为第一约束，20-30MW小数据中心成为快速补位的战略资源，大模型公司集能源、基建、模型三重身份于一身。对AI芯片产业来说，这意味着订单向深度绑定大客户的产品集中、设计向每瓦性能倾斜。算力军备竞赛的下半场，比的不是谁的芯片跑分更高，而是谁能先把电厂建起来、把电接进来。

This article is based on NVIDIA official product pages, the March 2026 GTC architecture blog, and third-party benchmark data; performance figures are vendor architecture comparisons, and actual gains should be verified with your own tests.

NVIDIA has confirmed that Groq 3 LPX — the "seventh chip" of the Vera Rubin platform — has entered full mass production, manufactured at Samsung's Pyeongtaek campus. This is the first time the deal has landed in the form of production silicon since December 2025, when NVIDIA spent roughly $20 billion to obtain a non-exclusive IP license to Groq plus its core engineering team.

For the inference hardware landscape, this is a paradigm-level event: for the first time, NVIDIA has incorporated a "specialized inference architecture defined by someone else" into its own flagship platform — and not as an add-on sale, but as deep co-design.

1. The Groq 3 LPU Chip and the LPX Rack: Specs at a Glance​

Single Groq 3 LPU (4nm, Samsung foundry):

Item	Value
Compiler-managed on-chip SRAM	500 MB
SRAM bandwidth	150 TB/s
Chip-to-chip scale-up bandwidth	2.5 TB/s (96 chip-to-chip links, 112 Gbps each)

A single LPX rack (32 1U liquid-cooled trays, 8 LPUs per tray):

Item	Value
Total LPUs	256
FP8 compute	315 PFLOPS
Total on-chip SRAM	128 GB
Aggregate SRAM bandwidth	40 PB/s
In-rack scale-up bandwidth	640 TB/s
DDR5 memory	12 TB (hosting large model weights)

The 500 MB of SRAM per LPU may not look like much, but multiplied by 256 LPUs and stacked with 40 PB/s of aggregate bandwidth, it forms the physical foundation of "deterministic low-latency decoding" — the LPU's design philosophy is precisely to use compiler static scheduling of on-chip SRAM to completely eliminate memory-fetch stalls during the inference decoding phase, which is exactly the most typical bottleneck of GPU inference.

2. AFD: Attention and FFN Split Up, GPU and LPU Each Do Their Own Job​

LPX does not replace the GPU; instead, it forms a heterogeneous system with Vera Rubin NVL72, centered on AFD (Attention-FFN Disaggregation):

1. Rubin GPUs handle prefill and attention — building the KV cache over large contexts and executing attention layers, consuming HBM capacity and high throughput;
2. Groq 3 LPUs handle FFN / MoE expert-layer decoding — latency-sensitive and pattern-predictable, exactly the home turf of deterministic SRAM scheduling;
3. Intermediate activations are exchanged between the two engines token by token, orchestrated and routed by NVIDIA Dynamo: the GPU computes every attention layer, the LPU computes every feed-forward layer, jointly producing each output token.

The logic of this division of labor is clear: agentic AI applications can consume 15x the tokens of traditional AI applications, and the bottleneck shifts from "can it finish computing" to "can it keep emitting tokens at stable low latency." Let the big HBM container run attention, and let the deterministic SRAM engine run decode — each plays to its strengths.

3. Measured Results and Official Figures​

• Third-party benchmarks (Artificial Analysis): with Gemma 4 31B at a 100K token context, LPX output reaches roughly 3400 tokens/s — inter-token intervals below 1 millisecond, a qualitative leap in interactivity for long-context agentic scenarios
• Official architecture comparisons: with LPX added, Vera Rubin NVL72 achieves up to 35x higher throughput per megawatt on trillion-parameter models; up to 10x more revenue opportunity per watt in "high-value token" scenarios
• Launch customers: Nebius is the first to deploy LPX racks to expand its token capacity; CoreWeave already connects Vera Rubin racks in production with Spectrum-X Multiplane

It must be emphasized: the 35x/10x figures are architecture comparisons at specific high-interaction operating points, not universal conclusions. For training, high-throughput batch inference, and workloads that need CUDA ecosystem flexibility, the GPU remains the right answer; LPX's home turf is scenarios where "single-user interactive latency is the product" — agent loops, real-time coding assistants, long-context conversations.

4. Three Industry Signals​

1. Specialized inference chips get absorbed, not opposed. The old narrative of the LPU as a "GPU challenger" has become part of Vera Rubin. The endgame for inference hardware may not be one architecture winning, but the heterogeneous combination of "GPU + specialized decoding engines" becoming the standard. For other inference chip startups (Cerebras, Etched, etc.), this is both proof that the ceiling has risen and a warning: get integrated or find differentiation.

2. Samsung foundry lands a high-end AI order. Against the backdrop of TSMC's near-monopoly on AI main chips, Samsung 4nm taking on LPX mass production is highly significant — combined with Tesla's earlier AI6 2nm order, Samsung foundry has a shot at returning to full-year profitability in 2027.

3. Inference economics enters the "priced per MW" era. When vendors start telling their story with tokens/MW and revenue per watt, the core KPI of compute selection has completely shifted from peak compute (TFLOPS) to token output per unit of energy. This is consistent with the power-and-electricity cost model built into our TCO Calculator: the chip with the best-looking peak specs is not necessarily the chip with the lowest cost per token.

Summary​

Groq 3 LPX mass production marks the arrival of a heterogeneous era for inference hardware: "GPUs manage throughput, LPUs manage latency." For teams currently selecting inference clusters, the recommendation is to evaluate workloads separately: keep batch offline inference on GPUs, and separately calculate the unit cost of LPX-class solutions for interactive long-context agents. If in doubt, run the 3-year total cost of ownership of both architectures through the TCO Calculator before deciding.

(Performance data in this article comes from NVIDIA official architecture comparisons and Artificial Analysis third-party benchmarks; for actual deployments, please rely on your own testing.)

According to ZhiXun (media) reporting in late September, Nebius announced that on-demand rates for H100 / H200 / B200 will rise by an average of about 20% starting October 1. The same month, Cailian Press reported that as of August 11 CoreWeave's contracted power had grown to 4.2 GW and that it would "keep signing new compute at higher prices". This is the Nth consecutive price increase in the rental market this AI cycle — and for buyers, the TCO balance between building and renting is shifting. This article works through the math using the site's TCO calculator methodology.

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1. Three Forces Behind the Price Hikes​

• Exploding agentic inference demand: from MLPerf v6.1 to SemiAnalysis AgentX, agentic workloads have become the main engine of inference growth — token consumption is orders of magnitude beyond chat scenarios, and inference compute has gone from "enough" to "never enough";
• Supply premium on the new platform generation: Vera Rubin NVL72 has debuted on CoreWeave, and early-ramp pricing on new platforms is naturally elevated — which also raises the anchor for renewal prices on the previous generation (H100/H200/B200);
• Power has become a hard constraint: CoreWeave's 4.2GW of contracted power shows the data center supply bottleneck has shifted from GPUs to power and racks; enterprises holding power contracts have no reason to cut prices.

2. What a 20% Rent Increase Means for TCO​

The site's TCO calculator splits total cost of ownership into five parts: purchase + energy + operations + network + discounting. Rent increases don't enter that model directly, but they change the "rental baseline" — the opportunity cost a build option must beat:

Scenario	Before 20% Rent Hike	After 20% Hike
Short-term elastic workloads (under 1 year)	Renting wins	Renting still wins (build deployment lead times can't catch up)
Steady inference workloads (2-3 years)	Crossover zone	Build starts to win (opportunity cost rises)
Training clusters (3 years+)	Build wins	Build's advantage widens

Rules of thumb:

• For workloads running 24/7 at full load for 2 years or more, a 20% rent increase is usually enough for building (even at a 1.5x purchase premium and with a PUE 1.3 energy model) to overtake renting within 30 months;
• Tidal workloads (daytime peaks, idle nights) should still rent — under the assumption that a build pays a continuous 15% idle power draw, building almost never breaks even below roughly 50% utilization;
• A hybrid strategy (owned baseline + rented peaks) is least sensitive to rent increases and is the robust play in the current interest-rate and power-price environment.

You can re-derive these conclusions in the TCO calculator: enter the "cloud rental unit price" at +20% and compare scenarios across purchase price, electricity price, and PUE. The default discount rate is 8%; purchase costs are not discounted, and annual electricity is discounted by 1.08^-y.

3. Pricing Implications for Domestic Compute​

Rent increases have a layer of impact on domestic AI chip purchasing decisions that is easy to overlook:

• The rental market for domestic chips is not yet mature: compute from Ascend / Cambricon / Moore Threads is delivered mostly as appliances, full racks, and intelligent computing center allocations; public on-demand rental prices are scarce — so procurement comparisons naturally lean toward "build / full-system" models;
• Relative TCO shift: a 20% NVIDIA rent increase raises the "relative attractiveness" of every domestic alternative, especially for inference workloads (actual market transaction prices for 910C / 950PR / P800 on the primary market are not public, but the full-system price gap versus dollar-priced cards is widening);
• Supply cadence: DeepSeek betting on Ascend training and rumors of 160,000-unit 950DT purchases — top demand eats capacity first, and queue times for later buyers are lengthening. Deciding early has value in itself.

4. Takeaways​

• Nebius raises H100/H200/B200 on-demand rates +20% from October; CoreWeave's contracted power at 4.2GW keeps locking in volume at high prices — rental market supply and demand remain tight;
• Agentic inference + Rubin supply premium + power constraints: three forces pushing rents up, with no near-term reversal in sight;
• Decision framework: steady workloads 2 years+ → the build window opens; tidal workloads → keep renting; hybrid strategies are most price-hike resistant;
• What to watch: whether other clouds follow with price moves, formal Rubin rental pricing, and whether a public rental market for domestic compute emerges.

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Further Reading​

• TCO Calculator (this site's interactive tool, full parameters for purchase / energy / discounting)
• Vera Rubin NVL72 MLPerf v6.1 Debut
• DeepSeek Confirms Bet on Huawei Chips for Large-Model Training

References​

• ZhiXun (media): Nebius raises AI chip rental prices; from October 1, H100/H200/B200 on-demand rates rise about 20% on average (2026-09-21)
• Cailian Press / East Money: CoreWeave deploys multi-rack Vera Rubin NVL72 cluster, contracted power grows to 4.2 GW (2026-09)

This article is compiled from public reports; TCO conclusions depend on assumptions such as utilization, electricity price, and discount rate. Please re-compute with your own parameters using the TCO calculator.

This article is based on official announcements from the 2026 JD Global Technology Explorer Conference (September 9) and public market information; order values and revenue forecasts are brokerage/media estimates, not company announcements.

On September 9, at the 2026 JD Global Technology Explorer Conference, JD Cloud announced a milestone decision: partnering with Moore Threads to build a 100,000-card full-function GPU cluster, creating hyperscale domestic intelligent computing infrastructure.

Two keywords in this sentence deserve amplification: "full-function GPU" and "100,000-card-class core cluster." The former means it must run not just inference but the front lines of large model training, inference, and embodied AI; the latter means a domestic GPU has, for the first time, been placed at the core of a top AI cloud provider's compute base — not a pilot, not an adaptation, not an all-in-one appliance, but 100,000 cards.

1. Partnership Details: From 10,000 to 100,000 Cards — How Big Is the Order?​

• Prior foundation: JD Cloud has already built a domestic 10,000-card cluster with Moore Threads and other partners; this move is a magnitude leap from 10,000 to 100,000 cards
• Order scale: According to market and brokerage information, GPU modules are supplied exclusively by Moore Threads, with a total order value of about RMB 20-30 billion; revenue can be recognized as early as next year according to delivery cadence. Some brokerages have raised Moore Threads' revenue expectation for next year to RMB 15-20 billion (this estimate is not a company announcement; refer to official disclosures)
• Partnership depth: Full-stack coordination from chips and cloud platform to model training, supporting the iteration of JD's JoyAI model family and forming a closed loop of "data, training, simulation, deployment"
• Openness: Compute is open to all industries, focused on large model training, inference, and embodied AI

Moore Threads founder Zhang Jianzhong was direct on stage: "The Scaling Law still holds — 100,000-card clusters are an inevitable trend." JD Cloud President Cao Peng positioned domestic compute as a core pillar of JD's physical AI strategy.

2. Why Moore Threads? Three Calculations Behind the Procurement Logic​

Tech companies buy cards with no sentiment involved. JD's choice of Moore Threads comes down to three calculations that all add up:

1. The stability calculation: Moore Threads has commercially deployed thousand-card and 10,000-card large clusters under a single network, and has achieved breakthroughs in core training scenarios such as foundation models, embodied brains, and world models — the engineering validation of a 10,000-card cluster is the prerequisite for 100,000 cards; this is not a cold start.

2. The integration calculation: Full-function GPUs can plug into existing IT systems and cloud platform scheduling, and the MUSA software stack's adaptation to large model frameworks has already passed training-grade workloads.

3. The ROI calculation: This is the most critical shift. Buyers of domestic GPUs used to be mostly "policy-friendly" projects; JD writing a 100,000-card cluster into its capital expenditure means the product's return on investment can now stand up to investor scrutiny — the buyer structure shifting from "daring to use" to "rushing to use" is the hallmark of commercial maturity for domestic GPUs.

3. S6000: Next-Gen Chip Taped Out and Back, with a Dual-Supply Safeguard​

According to market information, Moore Threads' next-generation chip, the S6000, has successfully come back from the fab and been distributed to vendors for testing, with ample FAB and memory supply guarantees. Note that the S6000 has not been officially released and its specifications are not public; this article makes no speculation. The on-sale flagship MTT S5000 has on-site data of 400 TFLOPS FP16 and 80GB of memory (the 1.6TB/s bandwidth is HBM-class).

Regarding HBM supply constraints, Moore Threads' response strategy is reportedly "next-generation product iteration + multi-source supply chain safeguards" — until domestic HBM capacity ramp-up is complete, this is the same problem every domestic GPU vendor must solve.

4. "100,000 Cards" Is Not One Company's Game: The Domestic GPU Cluster Landscape​

It is worth widening the view — 100,000 cards is now a collective goal for domestic compute:

Player	100,000-Card Move	Compute Base
JD Cloud	Announced co-built 100,000-card cluster on September 9	Moore Threads full-function GPU
Sugon 8000	Released at WAIC in July, completed in Zhengzhou; a fully domestic 100,000-card AI compute cluster	Hygon DCU (of the Shensuan BW1000 family)
Huawei	Atlas 950 SuperPoD super node (8,192 cards); 100,000-card super node in 2027	Ascend 950/960

Two chip routes (full-function GPU vs DCU vs NPU) and two paths (commercial cloud vs national supercomputing) point to the same validation question: can domestic compute reliably run real training workloads at 100,000-card scale. It is worth emphasizing that there is currently no public third-party benchmark comparison for the Moore Threads x JD cluster, and no completion timetable — going from "usable" to "running well" at 100,000 cards still requires engineering validation.

5. The Capital Markets Perspective​

Moore Threads listed on the STAR Market in December 2025: an IPO price of RMB 114.28, closing at RMB 600.5 on the first day; 2025 revenue of RMB 1.505 billion (up 243.37% year over year), with a net loss of about RMB 1.001 billion. If the brokerage-raised revenue expectation of RMB 15-20 billion materializes, 2027 will be the key inflection point from "high-growth loss-making" to "profitable at scale" — which would also become the first complete answer sheet for the domestic GPU business model.

Summary​

From debuting with DeepSeek all-in-one appliances in 2025 to entering a 100,000-card core cluster in 2026, domestic GPUs completed the cognitive leap from "usable" to "commercially viable at scale" in under two years. The value of JD Cloud's order lies not in its amount but in its significance as a sample: when top internet buyers begin procuring domestic GPUs on ROI logic, substitution is no longer a policy narrative but a commercial fact.

(Order values, revenue forecasts, and supply chain status come from public market information and brokerage research estimates; refer to company announcements; chip specification data is available in the on-site full comparison table.)

2026 年 9 月初，供应链信息确认：英伟达 Vera Rubin 平台已于 8 月正式量产、9 月启动批量出货，无延期、无卡顿。与 Blackwell 迭代初期的产能波折不同，这次量产节奏异常平稳——谷歌云、微软 Azure、CoreWeave、甲骨文云等头部云厂商已启动机架部署。但真正值得产业记住的，不是"又一代 GPU 量产了"，而是 Rubin 把液冷从"可选配置"变成了"硬性前置条件"。

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1. 量产节奏：史上最平稳的一次平台切换​

根据产业链调研与券商跟踪信息：

• 2026 年 8 月：Vera Rubin 正式量产；
• 2026 年 9 月：批量出货启动；
• 2026 下半年：CoreWeave、谷歌云、微软 Azure、甲骨文云机架部署落地；
• 2026 年：上代 GB 架构机柜出货量有望达 6 万台（同比翻倍）；
• 2027 年：GB 与 Rubin 两代平台合计出货体量有望接近 10 万台，Rubin 新机柜远期产能目标为每天 1000 个 NVL72 机柜。

需求侧同样在加码：华尔街报告披露，英伟达管理层表示 FY28 同比增长 70% 的目标并非需求上限——若供应不受限，增速可能超过 100%。当前主要约束已从需求端转向先进晶圆与 HBM 供应。

2. 单卡 2300W：风冷时代的终结​

Rubin 平台与前代最根本的差异不在算力，而在功耗密度：

指标	H100	GB300	Rubin
单 GPU TDP	700W	~1400W	2300W
机柜功耗	~40kW	~140kW	190–230kW
散热方案	风冷为主	风液混合	100% 全液冷
供电架构	48V	48V	800V 高压直流

单芯片 TDP 从 700W 升至 2300W、单机柜功率密度突破风冷物理极限——这意味着 液冷不再是高端算力的选配升级，而是运行 Rubin 服务器的先决条件。英伟达官方将 Rubin 全液冷架构定义为"数据中心历史上最重要的能效突破之一"，并已写入 DSX AI 工厂参考设计：所有跟随英伟达技术路线的云厂商和数据中心运营商，都必须采用全面液冷方案。

三个关键架构变化：

1. 无风扇整机：GPU、CPU、交换机、DPU 全部器件强制采用直接冷板式液冷，45℃ 温水冷板成为出厂标配；
2. 液冷边界延伸：散热覆盖范围从 GPU 冷板延伸至 CPU、DPU、交换机乃至光模块（液冷 Cage/鼠笼开始从"可选"变"刚需"），整套液冷系统价值量较 GB300 提升约 40%；
3. 800VDC 供电：替代传统 48V 机架配电，整机电源 BOM 价值增长 30% 以上，PSU 电源模块从 5.5kW 向 18.3kW 迭代，固态变压器、高压直流 CDU 成为数据中心新增核心设备。

3. 对产业链的三重传导​

第一重：液冷从"配套"变"主角"。 2026 下半年以小规模部署验证为主，真正的放量窗口在 2027 年——Rubin 机架大规模铺货后，冷板、快速接头、CDU、液冷泵进入业绩兑现期。台系供应链 7 月数据已率先验证：AVC 奇鋐 7 月营收 185.9 亿新台币创历史新高（同比 +57.4%），双鸿、健策 7 月同比分别 +116.7%、+91.0%。

第二重：国产液冷供应链进入核心 BOM。 国内厂商由外围冷源和代工环节逐步进入芯片平台、服务器 ODM 和海外云厂商供应体系，替代路径从 Manifold、管路推进至高可靠快接头和冷板。英维克 26H1 海外收入占比 71.4%，飞龙股份液冷泵小功率平台订单超 5 万台——液冷全核心零部件自主可控正在成为现实。

第三重：供电与散热边界融合。 800VDC 架构下，电源模块、PDB 配电单元、高速交换芯片自身发热也达到很高水平，部分电源组件同样需要液冷辅助散热——电源与温控两条产业链正在合并成一条。

4. 需求矩阵扩容：云厂商之外，太空算力入场​

Rubin 的客户矩阵已从传统云厂商扩展至三个层次：

• 全球云厂商：谷歌云、Azure、甲骨文云、CoreWeave；
• AI 科技巨头：马斯克公开披露 2027 年 8GW 超大规模 IDC 建设规划；SpaceX 将 Vera Rubin 架构定义为"最优 AI 计算架构"，计划地面与太空双向部署，支撑 "Starmind" 卫星算力项目；
• 主权与边缘：远期 Rubin Ultra 及 2027 年后更高功耗机型单机柜有望冲击 600kW+。

普华永道预计全球数据中心累计投资到 2035 年将达 31.6 万亿美元。AI 基础设施建设的确定性，已经从"是否建设"变成"多快建设"。

5. 对采购方的启示​

• 机房规划前置：2027 年起采购 Rubin 级算力，液冷改造（单千瓦改造成本较高）或按全液冷标准新建，必须在预算周期一开始就纳入；
• 看 PUE 也看水温：45℃ 温水直冷允许更高进水温度，可利用自然冷源压低 PUE——选址时人工冷源依赖度成为新的评估维度；
• 供应商组合即风险对冲：HBM 与先进封装供应是当前核心瓶颈（详见本站 HBM4 竞速分析），供应链多元化比单点性能更重要。

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相关链接​

• NVIDIA Rubin 规格页
• NVIDIA Rubin Ultra 规格页
• NVIDIA Rubin CPX 规格页

参考资料​

• 英伟达官方博客：Rubin 全液冷架构解析
• 财联社：Rubin 全面量产，看好液冷二次侧放量（2026-09-04）
• 东方财富研报：Vera Rubin 开启量产周期，AI 算力硬件环节迎来量价齐升（2026-08-27）
• 雪球：Vera Rubin 量产交付落地，全液冷 800V 高压架构重构（2026-09-03）

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本文基于 2026 年 9 月初供应链调研、券商研报与英伟达官方披露整理。出货量与功耗数据为产业链预估口径，实际以英伟达及客户正式披露为准。

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.

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1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

Timeline	Samsung HBM4 Yield	Notes
Feb 2026 (mass production start)	Under 60%	Line ramp-up period
Early Aug 2026	~80%	Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.

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2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor	2026 Rubin HBM4 Allocation (est.)	Notes
SK Hynix	60%–70%	Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung	25%–30%	Rapid share gains after yield leap
Micron	Remainder	Limited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.

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3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

• Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
• HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
• Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

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4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

Spec	HBM4 (12-Hi / 16-Hi)	HBM4E
Per-stack capacity	36 GB / 48 GB	—
Pin rate	11.7–13.0 Gbps	16 Gbps
Per-stack bandwidth	up to 3.3 TB/s	up to 3.6 TB/s
Bus width	2048-bit	—
Energy efficiency	+40% vs HBM3E	—
Thermal resistance / cooling	+10% improvement / +30%	—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.

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5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

• 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
• The industry already anticipates significant price increases;
• For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.

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6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

Related Links​

• NVIDIA Rubin Spec Page
• AMD MI455X Spec Page
• Hot Chips 2026 Full Recap

References​

• Samsung's HBM4 Yield Hits 80% as HBM Race Heats Up - TrendForce
• Samsung HBM4 Yield Hits 80%, Boosting AI Memory Supply - PC Central
• Samsung Weighs Shipping Legacy Memory Backend to Vietnam to Unlock HBM Capacity - TechTimes
• 芯闻|六个月良率跃迁：三星HBM4突破80%黄金门槛 - Toutiao

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This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.