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65 posts tagged with "AI Infrastructure"

Data center, power and networking infrastructure for AI

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AMD Helios进入量产:MI455X首批Q3末出货,OpenAI/Meta/Anthropic 12GW承诺兑现中

· 4 min read
Industry Research Team

从7月23日"Advancing AI"发布会官宣,到9月18日确认进入量产、首批出货瞄准Q3末——AMD Helios只用约2个月就完成了从PPT到产线的跨越。多吉瓦级的客户承诺,正在变成真金白银的硬件收入。

量产落地:约2个月的执行速度​

据2026年9月18日报道,AMD MI455X / Helios机架系统已进入生产阶段,首批出货目标为2026年第三季度末。回顾时间线:2026年7月23日Advancing AI大会上正式发布,到9月确认量产,间隔仅约2个月。对于机架级AI系统的量产节奏而言,这是相当激进的执行速度——NVIDIA当年GB200 NVL72的量产爬坡曾因供应链问题拖延数个季度,Helios显然吸取了教训。

客户版图:多吉瓦承诺正在兑现​

AMD在AI基础设施领域的客户合作已形成一张密集的网络:

客户/伙伴合作内容
OpenAI宣布6GW部署合作
Meta扩大合作,再部署6GW
Anthropic战略合作
微软Helios首批客户之一,2026年下半年交付
Oracle扩大合作
TCS将Helios架构带到印度
HPE扩大开放机架合作
美国主权AI助力超算建设

其中最重磅的是OpenAI的6GW与Meta的6GW——合计12GW的多吉瓦承诺,正通过MI455X/Helios的量产转化为近期硬件收入。这意味着AMD的Instinct业务线将从"技术验证"阶段正式进入"规模收入"阶段。

Helios机架:72卡MI455X的机架级算力​

Helios机架系统的核心构成如下:

组件规格
GPU72 × MI455X(CDNA 5架构)
单卡显存432GB HBM4
显存带宽23.3TB/s
CPUEPYC "Venice"(Zen 6,最高256核)
网络Pensando Vulcano NIC
互联UALink
机架算力2.9 EF FP4
机架显存总量31TB HBM4

几个关键点值得关注:

  • CDNA 5 + HBM4:MI455X单卡432GB HBM4、23.3TB/s带宽,在显存容量与带宽两个维度上都给出了激进规格;
  • EPYC Venice:Zen 6架构、最高256核的服务器CPU与GPU同机架部署,形成完整的"CPU+GPU+NIC"平台;
  • UALink互联:机架内GPU互联采用开放标准UALink,而非封闭私有方案。

此外,MI430X将驱动欧洲LUMI-AI超算,进一步扩展MI400系列在科学计算与AI融合场景的存在感。

开放标准生态:对NVIDIA垂直整合的制衡​

Helios的战略意义不止于产品本身。AMD正在联合产业伙伴推动UALink、UEC(超以太网联盟)、OCP等开放标准,与NVIDIA的NVLink/InfiniBand垂直整合体系形成制衡:

  • UALink:开放GPU互联标准,让多家厂商的加速器可以在统一协议下组网;
  • UEC:开放网络标准,降低用户被单一厂商网络方案锁定的风险;
  • OCP开放机架:与HPE扩大合作,推动机架级设计的开放化。

对超大规模云厂商和AI实验室而言,开放标准意味着议价能力与供应链多元化。OpenAI与Meta同时押注AMD,本身就是对NVIDIA一家独大格局的对冲。

小结​

Helios进入量产,标志着AMD完成了从"发布即承诺"到"交付即收入"的关键一跃:约2个月的发布到量产周期、12GW的客户承诺、72卡MI455X的2.9 EF FP4机架算力,以及UALink/UEC/OCP开放标准生态的持续推进,共同构成了AMD在2026年AI基础设施竞争中的核心筹码。MI430X驱动LUMI-AI超算的落地,则说明这套体系在学术与主权计算场景同样具备竞争力。

机架即计算机:NVL72、Helios、昇腾超节点的系统级战争

· 6 min read
Industry Research Team

当GPU单卡性能提升越来越难,NVIDIA、AMD与华为不约而同地把战场转向了机架。Bain 2026报告指出,竞争优势正从芯片规格转向系统级整合——compute、memory、networking、power与software的整体协同,才是AI算力下半场的胜负手。

三方系统规格对照​

先看三家旗舰机架级系统的硬规格:

维度NVIDIA Vera Rubin NVL72AMD Helios华为昇腾960超节点
计算单元Rubin GPU + Vera CPU72× MI455X + EPYC "Venice"(Zen 6,最高256核)昇腾960
互联NVLinkUALink over Ethernet超节点互联 + Hi-ONE光引擎
内存/带宽HBM4;AMD官方对比口径单卡288GB HBM4、22TB/s带宽31TB HBM4,每GPU 23.3TB/s1PB HBM
算力—整机架2.9 EF FP4、1.4 EF FP88 EFLOPS FP8(FP4为16 EFLOPS)
规模72卡72卡4096卡,集群可扩至51.2万卡
出货时间2026年下半年Hot Chips 2026公布规格—
性能提升Qwen3-VL吞吐较GB300最高3.7倍;推理token成本降低最高10倍scale-out 43TB/s(较竞品多50%以上)全球首个NPO超节点

注:表中"—"为素材未公开项,不作估算。三家口径与测试条件不同,数值仅供方向性参考。

NVIDIA NVL72:垂直整合与生态开放并行​

NVIDIA Vera Rubin NVL72延续"机架即计算机"的路线:Rubin GPU搭配自研Vera CPU,通过NVLink将72颗GPU熔铸成一个计算整体。MLPerf v6.1中,其Qwen3-VL吞吐较GB300 NVL72最高提升3.7倍,NVIDIA更宣称推理token成本最高降低10倍。

但NVIDIA也在调整姿态:NVLink Fusion向合作伙伴开放,允许集成自定义CPU与芯片;同时推进NVHBM定制内存控制器计划(与亚马逊Annapurna Labs合作)。这是垂直整合帝国的"有限开放"——互联与内存标准仍然是NVIDIA掌控的枢纽,但入口已经打开。

AMD Helios:开放标准路线的全面出击​

AMD Helios选择了另一条路:基于OCP开放标准构建,与Meta共同研发ORW(Open Rack Wide)设计。整机构成包括:

  • 计算:72颗MI455X,整机架2.9 EF FP4、1.4 EF FP8;
  • CPU:EPYC "Venice"(Zen 6架构,最高256核);
  • 网络:Pensando Vulcano 800G AI NIC,UALink over Ethernet互联;
  • 内存:31TB HBM4,每GPU 23.3TB/s,scale-up总带宽260TB/s,scale-out带宽43TB/s——较竞品多50%以上;
  • 机架:44OU ORW双宽机架,18个计算托盘加6个交换托盘,液冷快速接头,50V直流母线,整机重超7000磅(Hot Chips 2026口径)。

Helios的意义在于证明:不依赖专有互联协议,开放标准同样能撑起机架级系统。对担心NVIDIA锁定的云厂商与主权AI项目而言,UALink over Ethernet提供了真正的第二选择。

华为昇腾960超节点:换道超车的超大规模​

华为给出了截然不同的设计哲学——直接跳过"机架"这个尺度,以4096卡的超节点为单位构建系统:

  • 全球首个NPO超节点,算力达8 EFLOPS FP8(FP4精度16 EFLOPS);
  • 1PB HBM,内存容量以"PB"计;
  • 5500个Hi-ONE光引擎(单引擎7.2T)替代4.8万颗800G光模块,节省550kW功耗;
  • 可用度99.8%;
  • 集群可扩展至51.2万卡,多轨道拓扑支持100万卡。

4096卡 vs 72卡,不只是数字差异,而是设计哲学的分歧:NVIDIA与AMD把一个机架做成一台"计算机",华为则把半个数据中心机房做成一个"计算节点"——用光互联(NPO)解决跨机架带宽衰减问题,用超节点内部的高速交换换取更大规模的统一调度域。

Bain的判断:从芯片规格到系统级整合​

Bain 2026报告给出了理解这场战争的钥匙:竞争优势正从芯片规格转向系统级整合。compute、memory、networking、power与software五个维度的协同设计能力,取代单卡FLOPS成为竞争的决定性因素。

与之相伴的是评价体系的迁移:"每瓦token数"(tokens per watt)正在成为新的北极星指标。当电力成为第一约束,每消耗一瓦电力能产出多少token,直接决定了AI工厂的经济性——这比"峰值算力"诚实得多,因为前者同时反映了芯片效率、互联损耗、内存带宽与软件调度的综合水平。

两条路线:开放标准 vs 垂直整合​

机架级战争背后是两条路线的对抗:

路线代表互联标准优势风险
垂直整合NVIDIA(NVLink/灵衢UnifiedBus)、华为专有协议端到端协同优化,性能上限高生态锁定,客户议价力弱
开放标准AMD Helios(UALink/UEC/OCP)开放协议供应链多元,无锁定优化深度依赖联盟执行力

值得注意的是,NVIDIA的NVLink Fusion开放与华为的灵衢UnifiedBus生态,都在尝试"专有内核+开放外围"的中间态——完全的封闭或完全的开放可能都不是终局,机架级时代的第一性原理是:谁能定义互联标准,谁就掌握议价权。

小结​

NVL72、Helios与昇腾960超节点的三方对垒,宣告AI算力竞争进入"机架即计算机"的系统级时代:NVIDIA以Rubin GPU+Vera CPU+NVLink延续垂直整合,Qwen3-VL吞吐最高3.7倍、token成本最高降低10倍;AMD Helios以UALink over Ethernet与OCP开放标准证明第二条路可行,2.9 EF FP4、260TB/s scale-up带宽毫不逊色;华为昇腾960则以4096卡NPO超节点、1PB HBM的极端规格换道超车。Bain 2026报告说得透彻——竞争优势已从芯片规格转向系统级整合,"每瓦token数"成为新的北极星指标。72卡与4096卡的设计哲学差异,本质上是开放与整合两条路线对未来AI基础设施形态的不同押注。这场战争没有旁观者,采购方、云厂商与主权AI项目的每一次选择,都在为两条路线投票。

长鑫存储进军NAND:国产存储原厂格局生变

· 5 min read
Industry Research Team

国产DRAM龙头长鑫存储向NAND闪存伸出触角,不只是多一条产品线——在AI重构存储需求的当下,这意味着国产存储原厂格局正在发生结构性变化。

长鑫筹备进军NAND​

据路透社2026年9月中下旬报道,长鑫存储(CXMT)正筹备进入NAND闪存市场:公司已在北京设立NAND研发线,并开始接触AI系统与超算存储领域的客户。

在此之前,长鑫的定位是国产DRAM龙头,专注DRAM存储器的研发与量产。若此次进军NAND落地,长鑫将成为国内少有的同时覆盖DRAM与NAND两大存储品类的原厂。选择在此时点切入,时机耐人寻味:NAND市场长期由三星、铠侠、西部数据、美光、SK海力士等国际大厂主导,但AI对存储需求的剧变,正在为新进入者打开一扇窗。

AI正在改写存储的需求逻辑​

长鑫选择这个时点进军NAND,必须放在AI基础设施变革的大背景下理解。2026年9月,存储行业密集释放出"AI重构存储"的信号:

厂商时间动作关键点
SK海力士9月17日(AI Infra Summit 2026)发布"New Spectrum"组合HBF高带宽闪存、PIM存内计算、eSSD、SALT-KV
美光9月15日全球首款超密度服务器内存模组面向AI服务器内存扩容
华为9月OceanStor M900上下文内存存储集群PB级KV Cache,SSD读写寿命延长16倍

这些动作指向同一个事实:AI负载,特别是大模型推理,对存储提出了全新的要求——海量上下文、频繁随机读写、极低延迟。传统"DRAM管热数据、SSD管冷数据"的分层逻辑正在被改写。

KV Cache与上下文存储:新战场​

最值得关注的是华为OceanStor M900所代表的上下文内存存储方向。大模型推理中,KV Cache用于缓存对话与推理过程中的中间状态,随上下文长度增长而膨胀,成为制约推理吞吐和成本的关键瓶颈。PB级KV Cache集群的思路,是把KV Cache从GPU显存下沉到专用存储层,用SSD阵列承接上下文状态。

代价是SSD写入寿命——KV Cache的写放大远超传统负载。华为宣称通过技术手段将SSD读写寿命延长16倍,正是为了让SSD扛得住这种"内存化"使用强度。SK海力士的HBF(高带宽闪存)和SALT-KV则从介质层面给出了另一种答案。

对长鑫而言,这恰恰是机会所在:AI上下文存储需要海量的高性价比NAND容量,且这一细分市场尚无固化格局。用NAND切入AI基础设施供应链,比在消费级SSD市场硬碰硬更有想象力。

国产存储自给的第二曲线​

从国产替代的视角看,长鑫进军NAND的意义在于打开"第二曲线":

  • 第一曲线(DRAM):长鑫已在国产DRAM市场站稳,产能与技术持续爬坡,解决了国产存储"有没有"的问题。
  • 第二曲线(NAND+AI存储):NAND研发线与AI/超算客户触达,意味着长鑫瞄准的不是简单复制国际大厂的产品矩阵,而是直连AI基础设施这个增量市场。

结合AI对存储的重新定义——部件正在变成平台,长鑫若能借NAND切入KV Cache、上下文存储等AI存储场景,将实现从"存储部件供应商"向"AI基础设施玩家"的跃迁,这条路径的上升空间远大于传统NAND替代。

存储公司的身份转变​

SK海力士在AI Infra Summit 2026上发布的"New Spectrum"组合(HBF、PIM、eSSD、SALT-KV),以及随后在硅谷成立风险投资部门拓展AI生态投资,都说明头部存储厂商已经完成了自我定位的刷新:存储公司不再是被动跟随CPU、GPU规格的部件商,而是主动定义AI数据架构的平台方。长鑫的NAND布局,正是这股浪潮中的国产注脚。

小结​

长鑫存储筹备进军NAND,表面上是一次品类扩张,实质上是AI时代存储价值重估的缩影:SK海力士、美光、华为密集发布面向AI的存储创新,KV Cache与上下文存储成为新战场,存储公司正从部件供应商转型为AI基础设施平台玩家。对国产存储而言,DRAM之外的NAND第二曲线若能与AI需求红利叠加,国产存储自给将进入新阶段。格局生变,好戏才刚开始。

定制HBM军备赛:AWS联手NVIDIA开发NVHBM,超大规模厂商开始"造内存"

· 5 min read
Industry Research Team

当芯片厂商开始"造内存"、云厂商开始"造芯片",AI基础设施的分工边界正在瓦解——存储不再是采购来的标准件,而是与加速器协同设计的战略资产。

NVHBM:AWS与NVIDIA的定制内存联姻​

AI Infra Summit 2026(9月17日)上爆出的消息显示:亚马逊旗下Annapurna Labs正与NVIDIA合作开发NVHBM定制高带宽内存技术。

这个组合本身就足以说明问题。Annapurna Labs是AWS自研芯片体系的核心(Graviton CPU、Trainium/Inferentia加速器都出自该团队),而NVIDIA则是AI加速器绝对主导者。两家联手开发定制HBM,意味着最强势的云厂商与最强势的芯片厂商决定共同绕开标准内存路线,为AI负载打造私有化的内存方案。

存储协同设计:行业范式转移​

NVHBM并非孤立事件。AI Infra Summit 2026前后,存储行业的密集动作勾勒出一幅"存储深度嵌入AI"的图景:

厂商时间动作关键内容
亚马逊+NVIDIA9月17日报道合作开发NVHBM定制高带宽内存
SK海力士9月17日发布"New Spectrum"组合HBF高带宽闪存、PIM存内计算、eSSD、SALT-KV
SK海力士9月18日成立SK hynix Ventures(硅谷)拓展全球AI生态投资
美光9月15日超密度服务器内存模组全球首款

2026年9月21日的半导体周报对这一趋势给出了精辟概括:"Memory is being co-designed with AI accelerators rather than treated as a commodity"——内存正在与AI加速器协同设计,而不再被视为大宗商品。

这句话宣告了一个时代的结束:过去几十年,内存是标准化的商品,JEDEC规范统一接口,谁家买都一样。而在AI时代,内存的带宽、容量、拓扑直接决定集群效率,"标准件"思维已经跟不上需求。

为什么绕过JEDEC走定制路线​

超大规模厂商选择定制HBM,动机有三:

  • 性能天花板:标准HBM的规格迭代节奏由JEDEC委员会决定,而AI负载的内存需求以年为单位翻倍。定制方案可以围绕特定加速器优化堆栈数、接口带宽和容量配比,榨取最大能效。
  • 供应安全:HBM产能持续紧张,已成为整个AI芯片产业的瓶颈。定制协议绑定的不只是技术规格,更是产能分配——把内存供应商变成深度盟友。
  • 成本控制:HBM占AI加速器物料成本的重要比重。云厂商自建芯片团队后,有动力也有能力参与内存定义,消除中间层的规格冗余。

HBM短缺:国产芯片涨价潮的根源​

定制HBM军备赛的另一面,是HBM产能的普遍短缺。近期的国产芯片涨价潮,其根源正是HBM供应不足——当NVIDIA、AMD以及各云厂商自研芯片都在争夺有限的HBM产能时,位于优先级末端的采购方(包括部分国产AI芯片厂商)面临的是"有芯片设计、没有内存可用"的窘境,成本随之水涨船高。

这解释了为什么HBM产能与成本已成为芯片厂商的核心竞争维度:谁能锁定HBM供应,谁就能锁定出货量;谁的定制内存方案能效更高,谁的产品就更具竞争力。存储厂商的地位因此空前提升——SK海力士在发布"New Spectrum"后次日即于硅谷设立SK hynix Ventures投资AI生态,正是从供应商向生态节点跃迁的标志性动作。

对下一代平台意味着什么​

NVHBM若落地,影响将体现在两个层面:

  • NVIDIA Vera Rubin及后续代际:定制内存与加速器协同设计,意味着未来Rubin后续产品的内存子系统可能针对AWS负载定制,云厂商对芯片平台的参与度从"采购方"升级为"共同定义方"。
  • 机架级内存竞赛:AMD已展示31TB HBM4机架方案,机架级内存容量的军备竞赛已经开打。当内存容量从单卡432GB演进到机架数十TB,内存架构的设计自由度(定制HBM vs 标准HBM4)将直接决定产品竞争力。

小结​

AWS联手NVIDIA开发NVHBM,标志着存储正式从"采购关系"进入"协同设计"时代:SK海力士以HBF/PIM/eSSD/SALT-KV重构存储产品线并设立风投部门,美光推出超密度内存模组,超大规模厂商开始绕过JEDEC定制内存。HBM短缺引发的国产芯片涨价潮则揭示了新秩序的残酷一面——内存即产能,产能即话语权。当"造内存"成为芯片巨头的必修课,AI基础设施的竞争维度被彻底改写。

SK海力士发布AI存储"新频谱":HBF、PIM、SALT-KV重新定义AI基础设施

· 5 min read
Industry Research Team

2026年9月17日,SK海力士在AI Infra Summit 2026上发布面向AI基础设施的"New Spectrum"技术组合。当Agentic AI与长上下文推理把存储推向瓶颈中心,存储厂商正从部件供应商转型为AI基础设施平台玩家。

New Spectrum:四大技术方向​

SK海力士此次发布的"New Spectrum"组合覆盖四个方向,每一项都瞄准AI工作负载中最突出的存储瓶颈:

技术方向全称核心定位
HBFHigh Bandwidth Flash(高带宽闪存)把闪存带宽提升至内存量级
PIMProcessing In-Memory(存内计算)在存储侧完成计算,减少数据搬运
eSSD企业级固态硬盘AI数据湖与训练数据底座
SALT-KV—面向KV Cache的键值存储方案

这四项技术的共同指向非常清晰:AI推理时代的存储不再是"够大就行",而是要同时满足带宽、容量、成本与数据通路效率的多重约束。

KV Cache经济性:Agentic AI拉动的存储需求​

理解New Spectrum的关键,是理解KV Cache经济性。

大语言模型推理时,每一个token的生成都要读取之前所有上下文的KV Cache。上下文越长,KV Cache越大;Agentic AI的兴起让"长对话、多轮次、多Agent协作"成为常态——一个Agent任务可能持续数十轮调用,每轮都在累积上下文。这意味着:

  • KV Cache容量需求爆炸式增长:长上下文模型动辄数十万token的窗口,单请求KV Cache可达数十GB量级;
  • 带宽成为隐性成本中心:每生成一个token都要完整读取KV Cache,内存带宽直接决定了单位token成本;
  • 层级化存储成为必然:HBM放不下的KV Cache需要更快的次级存储,这正是HBF与SALT-KV的切入点。

同期,华为OceanStor M900已提供PB级KV Cache集群方案,说明"KV Cache基础设施化"已是行业共识。谁能把KV Cache存得更多、读得更快、成本压得更低,谁就掌握了推理经济的新杠杆。

HBF:把闪存带宽提到内存量级​

HBF(High Bandwidth Flash)是New Spectrum中最具想象空间的一项。传统NAND闪存的致命短板是带宽——顺序读尚可,随机读性能与内存相差数个量级,因此长期只能承担"冷数据"角色。

HBF借鉴HBM的设计哲学,通过堆叠与宽接口把闪存带宽提升至接近内存的量级。这带来的可能性是:原本必须驻留HBM的热数据,可以部分下沉到HBF层,在成本几乎不变的情况下大幅扩展"有效内存容量"。对于动辄以TB计的模型权重和KV Cache而言,HBF有望成为HBM与eSSD之间缺失的中间层。

PIM:推理场景的近数据计算​

PIM(存内计算)的定位则是解决另一个痛点:数据搬运。在传统架构中,数据从内存搬运到计算单元的能耗与延迟开销,往往超过计算本身。PIM把计算能力直接嵌入存储介质,让"数据不动、计算过来"。

在推理场景中,PIM尤其适合权重固定的矩阵乘加等访存密集操作,能够在降低功耗的同时提升吞吐。随着每瓦token数成为数据中心的核心KPI,PIM的价值会持续放大。

行业同期动作:存储军备竞赛全面展开​

SK海力士的动作并非孤立。2026年9月中旬,存储与定制硬件领域密集出招:

时间厂商动作
9月15日美光发布全球首款超密度服务器内存模组
9月17日SK海力士AI Infra Summit 2026发布New Spectrum技术组合
9月18日SK海力士在硅谷成立SK hynix Ventures,扩大全球AI生态投资
9月同期亚马逊Annapurna Labs × NVIDIA合作NVHBM定制HBM

三个信号值得注意:其一,美光的超密度内存模组直指单机内存容量天花板;其二,亚马逊与NVIDIA的NVHBM合作说明头部应用方已深入定制内存控制器层面;其三,SK hynix Ventures落地硅谷,表明存储巨头不再满足于卖部件,而是要通过投资生态锁定AI基础设施的平台位置。

2026年9月的半导体周报对此有明确判断:存储正与AI加速器协同设计,存储公司正从部件供应商转型为AI基础设施平台玩家。HBM4时代的定制化(如NVHBM)正是协同设计趋势的直接体现——内存不再是可以即插即用的标准件,而是与GPU、ASIC深度耦合的系统组件。

小结​

SK海力士的New Spectrum组合——HBF、PIM、eSSD、SALT-KV——勾勒出AI存储的完整路线图:HBF把闪存带宽提到内存量级、填补HBM之下的层级空白,PIM用近数据计算降低搬运开销,SALT-KV直击KV Cache经济性这一推理时代的核心命题。叠加美光超密度内存、亚马逊与NVIDIA的NVHBM定制HBM等同期动作,2026年的存储行业已经清晰地完成了角色转身:从跟随GPU节奏的部件供应商,变成与AI加速器协同设计、共同定义AI基础设施形态的平台玩家。存储,正在成为AI竞争的下一个主战场。

平头哥公布倚天CPU路线图:倚天720/730明年推出,730首次全自研微架构

· 5 min read
Industry Research Team

在Agentic AI重塑算力需求结构的当下,平头哥首次公开倚天服务器CPU发展蓝图——全自研微架构与ICN总线直连,是这份路线图最值得关注的两个关键词。

云栖大会:倚天蓝图首次公开​

2026年9月22日的云栖大会上,平头哥首次公开倚天系列服务器CPU的发展蓝图:2027年将推出倚天720与倚天730两款服务器CPU。这是平头哥第一次以路线图的形式,系统性地向外界展示倚天CPU的演进节奏——从"发布单点产品"到"公布多代路线",意味着倚天系列的研发与规划已经形成了清晰的代际滚动机制。

型号推出时间核心亮点
倚天710已商用现役主力,后续产品的性能基准
倚天7202027年单核性能、核密度与能效全面提升
倚天7302027年首次基于平头哥全自研CPU微架构设计,单核SPECint2017/GHz性能最高提升至倚天710的1.4倍
倚天750时间未公开基于第二代自研核,支持平头哥自研ICN片间互联总线协议

倚天720与倚天730:差异化分工​

两款2027年的新品各有侧重。倚天720走的是"全面均衡"路线:单核性能、核密度与能效三项指标同步提升,面向通用算力场景的规模化部署——在数据中心机柜功率与空间约束日益收紧的背景下,核密度与能效的提升直接决定了单位机柜可承载的算力上限。

倚天730则是更具突破意义的一代:它首次基于平头哥全自研CPU微架构设计,单核SPECint2017/GHz性能最高提升至倚天710的1.4倍。SPECint2017/GHz衡量的是单位频率下的整数性能(即IPC水平),1.4倍意味着微架构层面的显著优化,而非单纯依靠频率或制程红利。从"基于授权架构"到"全自研微架构",这是服务器CPU自研道路上最关键的一次跨越——它决定了后续每一代产品能否摆脱外部授权的节奏约束。

ICN总线:CPU与AI芯片的直连时代​

路线图中另一个关键角色是ICN片间互联总线协议。根据蓝图,基于第二代自研核的倚天750将支持平头哥自研的ICN总线协议,倚天CPU与真武AI芯片之间可通过ICN总线直接互联,进一步提升CPU与AI芯片的协同效率。

这一设计直指传统架构的痛点:在现有体系中,CPU与AI加速卡之间通常通过PCIe等通用互联通信,带宽与延迟都存在损耗,而这些损耗恰恰发生在数据预处理、梯度同步、通信协同等高频环节。ICN总线让CPU与AI芯片"原生对话",相当于把CPU纳入AI集群的整体互联拓扑,而非让它们停留在AI芯片的"外围"。

Agentic AI时代的CPU需求分化​

平头哥此时公布CPU路线图,并非偶然。其背景是Agentic AI正在驱动CPU需求分化:智能体应用大规模兴起后,CPU不再是AI服务器里"配平"的角色——Agent的调度、编排、数据处理与轻量推理,对CPU的核密度、能效与协同能力都提出了新要求。通用CPU与AI算力的配比、互联方式,都在被重新设计。

同期发布的真武V900构成了这套蓝图的全栈拼图:216GB显存、1200GB/s片间互联、支持50万卡集群。叠加倚天CPU经ICN总线直连的能力,阿里云正在构建"AI芯片+CPU+网络"的全栈算力体系——芯片自研、互联自研、CPU自研,三层能力的耦合度越高,系统的整体效率上限就越高。

小结​

倚天720/730定档2027年、倚天730首次采用全自研微架构、单核SPECint2017/GHz性能最高提升至倚天710的1.4倍,再加上ICN总线与真武AI芯片直连的规划、真武V900(216GB显存、1200GB/s片间互联、50万卡集群)的全栈拼图,平头哥给出了一条清晰且野心不小的CPU自研路线。在Agentic AI驱动的算力变革中,"AI芯片+CPU+网络"的全栈协同能力,或将成为云厂商竞争的下一个分水岭。

高通与AWS达成40亿美元AI联盟:多代定制AI芯片+1.6T光互联

· 6 min read
Industry Research Team

当全球最大云计算服务商选择与一家手机SoC巨头联手开发定制AI芯片,数据中心算力市场的竞争逻辑正在被改写。

一场跨多代的战略牵手​

当地时间2026年9月8日,高通技术公司与亚马逊AWS正式宣布达成一项跨多代产品的战略合作。双方将围绕大规模AI数据中心展开两个方向的深度协同:其一是联合开发多代定制AI芯片,其二是共同推进高速光互联解决方案,其中明确包含1.6T光连接方案。

这份协议最值得注意的不是"合作"本身,而是"跨多代"三个字。云厂商与芯片供应商之间的合作,通常以单颗芯片的流片项目为单位;而跨多代的框架式合作,意味着双方在芯片定义、迭代节奏、互联演进路线上都建立了长期协同机制。对高通而言,这是其在数据中心AI芯片市场战略布局上获得的、来自全球最大云计算服务商的关键背书。

合作要点一览​

合作维度具体内容
合作双方高通技术公司 × 亚马逊AWS
宣布时间当地时间2026年9月8日
合作性质跨多代产品的战略合作
定制芯片面向大规模AI数据中心联合开发多代定制AI芯片
光互联联合推进高速光互联解决方案,包含1.6T光连接方案

芯片与光互联并举,是这份协议的另一个信号。在超大规模AI集群中,互联带宽早已成为与算力同等重要的瓶颈,1.6T光连接代表的正是下一代集群网络的带宽量级。芯片设计能力与光互联能力的组合输出,让这桩合作超出了单纯的"定制ASIC"范畴。

高通的第二次冲锋​

对高通而言,数据中心并不陌生,但此前的探索主要集中在推理侧。高通此前已推出AI100、AI200、AI250等推理加速卡产品线,试图将自己在低功耗计算、SoC集成上的多年积累迁移到数据中心场景。

产品线定位具体规格
AI100推理加速卡未公开
AI200推理加速卡未公开
AI250推理加速卡未公开

从手机SoC转向数据中心AI芯片,是高通的第二次冲锋。第一次冲锋(AI100/AI200/AI250推理卡)走的是标准产品路线;而这一次的不同之处在于:它不再只是卖标准推理卡,而是直接切入头部云厂商的定制芯片供应链——这恰恰是博通(Broadcom)、Marvell等定制芯片玩家长期占据、且利润丰厚的位置。

这个转变的产业逻辑并不难理解。AI推理需求的爆发让云厂商迫切需要"够用、便宜、可定制"的算力方案,而高通在低功耗设计、异构集成上的基因,恰好与推理场景的诉求契合。借助AWS这个锚点客户,高通有望把定制芯片业务从"试水"升级为"主业"。

AWS的双轨算力战略​

AWS是业内少数坚持自研芯片路线的云计算巨头。其Annapurna Labs团队打造了Trainium训练芯片与Inferentia推理芯片两条自研产品线,支撑起自家大规模算力底座,也是AWS在算力成本上对抗NVIDIA溢价的核心筹码。

此番与高通合作,可以视为AWS在"自研 + 外部定制"双轨战略上的进一步加码:

  • 自研线:Trainium/Inferentia保证核心架构可控与成本优化;
  • 外部定制线:引入高通等外部设计力量,扩充设计带宽与供应链弹性,应对爆发式的AI算力需求。

两条腿走路的本质是风险对冲:自研芯片的迭代周期难以无限压缩,而外部定制伙伴可以在关键代际上补充产能与设计资源。全球最大云厂商选择加码双轨,本身就说明单一供给模式已经无法满足AI算力的需求曲线。

对行业格局的影响​

这笔合作最直接冲击的,是数据中心定制芯片与互联方案的既有格局:

  • 对NVIDIA:头部云厂商在旗舰GPU之外扩充定制AI芯片选项,算力采购组合将更加多元,NVIDIA在数据中心市场的议价空间面临新的边际压力;
  • 对Marvell、博通:高通携AWS背书进入定制芯片赛道,定制ASIC设计服务的竞争者又多了一家重量级玩家,客户资源与设计人才的争夺将更激烈;
  • 对光互联生态:1.6T光连接的联合推进,意味着超大规模集群的互联带宽军备竞赛继续提速,光模块、光引擎、CPO/NPO相关供应链都将受益于这一代际切换。

更长远地看,"云厂商深度参与芯片定义"正在成为AI基础设施的主流范式。当芯片规格越来越贴近具体业务负载,通用GPU与定制ASIC之间的边界会被不断重画。

小结​

高通与AWS的跨多代合作,是"云厂商定制芯片"趋势下的标志性事件:手机SoC巨头以定制芯片+1.6T光互联的组合拳向数据中心发起第二次冲锋,全球最大云厂商则以"自研+外部定制"双轨强化供应链弹性。对NVIDIA、Marvell、博通而言,一个新的强敌已经入场;对整个AI基础设施行业而言,竞争的维度正在从"单点芯片性能"转向"芯片+互联+云"的全栈博弈。这是2026年下半年最值得持续跟踪的合作之一。

Intelligent Compute to Hit 9,800 EFLOPS by 2030: Five Hard Targets in the ICT Industry "15th Five-Year" Plan

· 6 min read
Industry Research Team

This article is based on the MIIT "15th Five-Year" Plan for ICT Industry Development (issued in September 2026) and official interpretations by the People's Post and Telegraph News, The Paper, Huaxia Times, and other outlets.

In early September, the MIIT issued the "15th Five-Year" Plan for ICT Industry Development, drawing a roadmap for the ICT industry over the next five years with 13 major indicators and 26 key tasks. For the AI compute industry, this is the most substantive policy document — we have picked out five hard targets and break down their industry implications one by one.

Target 1: Intelligent Compute from 1,590 to 9,800 EFLOPS, More Than 5x Growth in Five Years​

This is the standout number in the entire plan. For reference:

  • As of the end of June 2026, national intelligent compute capacity had reached 2,185 EFLOPS, up 177% year over year — the first half alone overshot the year-end 2025 target (1,590 EFLOPS)
  • The country has built 42 10,000-card-class intelligent computing clusters; in July 2026, the first fully domestic 100,000-card-class AI compute cluster, the Sugon 8000, was completed in Zhengzhou
  • Huawei's rotating chairman Wang Tao's assessment: super-node clusters of more than 100,000 cards will become basic configuration by 2027

Going from 2,185 to 9,800 means that over the next four years the country must build 3.5 times the current installed base of intelligent computing facilities. The plan also calls for "orderly deployment of 10,000-card, 100,000-card and larger intelligent computing clusters" and "stepping up efforts to adapt domestic compute chips" — this is the most certain demand base for domestic AI chips over the next five years.

Target 2: Cumulative Information Infrastructure Investment of RMB 3.8 Trillion​

Some have compared this with the "14th Five-Year" figure of RMB 3.7 trillion and concluded that "investment has peaked." Official interpretations explicitly reject this claim: incremental capital is shifting from "scale expansion" to "quality-and-efficiency gains," precisely targeted at intelligent computing infrastructure, 10G optical networks, 6G, and other new tracks. The industry chain pull effect is changing accordingly — AI servers, high-speed optical interconnects, domestic compute chips, and new smart terminals were named as beneficiaries across the whole chain.

Target 3: PUE of New Large Compute Facilities Reduced Below 1.2​

At the end of the "14th Five-Year" period this figure was 1.25, and it must fall another 0.05 within five years — it doesn't sound like much, but with AI servers running at high load year-round and per-rack power density generally exceeding 20kW, every point of PUE reduction is a hard fight. The technical path laid out in the plan is very clear: liquid cooling.

  • The "15th Five-Year" Plan for ICT Industry Development: guide compute facilities to adopt high-efficiency energy-saving equipment and advanced technologies such as liquid cooling
  • The "15th Five-Year" Plan for Electronic Information Manufacturing Development (jointly issued by the MIIT and the NDRC on September 15): lists liquid cooling alongside high-bandwidth memory pooling and all-optical switching as key technologies to be broken through

Industry-side data confirms the trend: according to Omdia, liquid cooling's share of the global data center cooling market climbed from about 20% in 2024 to about 37% in 2025, with penetration expected to exceed 45% by 2029. The ceiling on compute expansion is shifting from chip supply to power supply, and the energy-efficiency constraint of "compute up, energy down" will be the norm for the next five years.

Target 4: Advanced Storage Capacity of 1,700 EB, More Than 2x Growth​

While intelligent compute grows 5x, advanced storage grows more than 2x — storage-compute coordination is given equal weight. The logic: training checkpoints for large models, and the intermediate states and contextual memory of agent inference, are all stored in layers within high-performance storage. As of the end of June, national storage capacity totaled about 2,021 EB, of which advanced storage accounted for about 32%; the 1,700 EB advanced storage target for 2030 means structural upgrading matters more than total-volume growth.

A direct implication for chip selection: KV cache and long context are eating the memory budget — when evaluating AI servers, memory capacity and memory bandwidth should carry more weight than peak compute.

Target 5: The Agent Interconnection Network Enters the Plan for the First Time​

This is the most forward-looking part of the plan: the "agent interconnection network" gets its own dedicated column, deploying four areas of work — building an agent network identifier system, accelerating the construction and application of agent network infrastructure, promoting global interconnection, and establishing a space governance system. It also explicitly states "launching 6G commercial use in a timely manner."

As AI shifts from "applications for people" to "agent infrastructure," the role of the communications network upgrades from connecting people to connecting agents — providing a national-level narrative for the distributed deployment of inference compute (edge inference, compute scheduling).

Three Judgments for Compute Practitioners​

JudgmentBasis
Domestic compute demand is highly certainThe plan explicitly states "stepping up efforts to adapt domestic compute chips" + the 100,000-card cluster build cycle has begun
Energy-efficiency targets become hard siting constraintsPUE below 1.2 + liquid cooling named as a key technology; high-density liquid cooling solutions take priority
Inference compute sinks to the edge on demand"Deploy inference compute facilities as needed for scenarios"; edge and regional compute centers enjoy a policy window

Under a 5x compute expansion target, what has always been scarce is not planning but chips, power, and delivery capability. For buyers, the supply window remains tight; for solution selection, we recommend using the TCO Calculator to convert PUE differences into electricity costs — the gap between 1.25 and 1.2 amounts to tens of millions on the electricity bill of a 10,000-card cluster.

Summary​

The "15th Five-Year" Plan writes intelligent compute into a national-level project: 5x compute, 2x storage, RMB 3.8 trillion in investment, PUE 1.2, and the agent internet. Looking back five years from now, the wave of domestic 100,000-card clusters in the second half of 2026 may well prove to be the starting point of this curve.

(Plan data is cited from MIIT documents and official media interpretations; market data is cited from statistics by CAICT, Omdia, and other institutions.)

GPU Rental Rates Climb Again: Nebius Raises H100/B200 On-Demand Prices About 20% From October, and the Build-vs-Rent Balance Is Shifting

· 5 min read
Industry Research Team

According to ZhiXun (media) reporting in late September, Nebius announced that on-demand rates for H100 / H200 / B200 will rise by an average of about 20% starting October 1. The same month, Cailian Press reported that as of August 11 CoreWeave's contracted power had grown to 4.2 GW and that it would "keep signing new compute at higher prices". This is the Nth consecutive price increase in the rental market this AI cycle — and for buyers, the TCO balance between building and renting is shifting. This article works through the math using the site's TCO calculator methodology.


1. Three Forces Behind the Price Hikes​

  • Exploding agentic inference demand: from MLPerf v6.1 to SemiAnalysis AgentX, agentic workloads have become the main engine of inference growth — token consumption is orders of magnitude beyond chat scenarios, and inference compute has gone from "enough" to "never enough";
  • Supply premium on the new platform generation: Vera Rubin NVL72 has debuted on CoreWeave, and early-ramp pricing on new platforms is naturally elevated — which also raises the anchor for renewal prices on the previous generation (H100/H200/B200);
  • Power has become a hard constraint: CoreWeave's 4.2GW of contracted power shows the data center supply bottleneck has shifted from GPUs to power and racks; enterprises holding power contracts have no reason to cut prices.

2. What a 20% Rent Increase Means for TCO​

The site's TCO calculator splits total cost of ownership into five parts: purchase + energy + operations + network + discounting. Rent increases don't enter that model directly, but they change the "rental baseline" — the opportunity cost a build option must beat:

ScenarioBefore 20% Rent HikeAfter 20% Hike
Short-term elastic workloads (under 1 year)Renting winsRenting still wins (build deployment lead times can't catch up)
Steady inference workloads (2-3 years)Crossover zoneBuild starts to win (opportunity cost rises)
Training clusters (3 years+)Build winsBuild's advantage widens

Rules of thumb:

  • For workloads running 24/7 at full load for 2 years or more, a 20% rent increase is usually enough for building (even at a 1.5x purchase premium and with a PUE 1.3 energy model) to overtake renting within 30 months;
  • Tidal workloads (daytime peaks, idle nights) should still rent — under the assumption that a build pays a continuous 15% idle power draw, building almost never breaks even below roughly 50% utilization;
  • A hybrid strategy (owned baseline + rented peaks) is least sensitive to rent increases and is the robust play in the current interest-rate and power-price environment.

You can re-derive these conclusions in the TCO calculator: enter the "cloud rental unit price" at +20% and compare scenarios across purchase price, electricity price, and PUE. The default discount rate is 8%; purchase costs are not discounted, and annual electricity is discounted by 1.08^-y.

3. Pricing Implications for Domestic Compute​

Rent increases have a layer of impact on domestic AI chip purchasing decisions that is easy to overlook:

  • The rental market for domestic chips is not yet mature: compute from Ascend / Cambricon / Moore Threads is delivered mostly as appliances, full racks, and intelligent computing center allocations; public on-demand rental prices are scarce — so procurement comparisons naturally lean toward "build / full-system" models;
  • Relative TCO shift: a 20% NVIDIA rent increase raises the "relative attractiveness" of every domestic alternative, especially for inference workloads (actual market transaction prices for 910C / 950PR / P800 on the primary market are not public, but the full-system price gap versus dollar-priced cards is widening);
  • Supply cadence: DeepSeek betting on Ascend training and rumors of 160,000-unit 950DT purchases — top demand eats capacity first, and queue times for later buyers are lengthening. Deciding early has value in itself.

4. Takeaways​

  • Nebius raises H100/H200/B200 on-demand rates +20% from October; CoreWeave's contracted power at 4.2GW keeps locking in volume at high prices — rental market supply and demand remain tight;
  • Agentic inference + Rubin supply premium + power constraints: three forces pushing rents up, with no near-term reversal in sight;
  • Decision framework: steady workloads 2 years+ → the build window opens; tidal workloads → keep renting; hybrid strategies are most price-hike resistant;
  • What to watch: whether other clouds follow with price moves, formal Rubin rental pricing, and whether a public rental market for domestic compute emerges.

Further Reading​

References​

  • ZhiXun (media): Nebius raises AI chip rental prices; from October 1, H100/H200/B200 on-demand rates rise about 20% on average (2026-09-21)
  • Cailian Press / East Money: CoreWeave deploys multi-rack Vera Rubin NVL72 cluster, contracted power grows to 4.2 GW (2026-09)

This article is compiled from public reports; TCO conclusions depend on assumptions such as utilization, electricity price, and discount rate. Please re-compute with your own parameters using the TCO calculator.

Alibaba Zhenwu V900 Unveiled at Apsara Conference: 3x M890 Performance, 216GB Memory, 500,000-Card Cluster, Mass Production in 2027 Q1

· 5 min read
Industry Research Team

Just five days after Huawei officially announced the Ascend 960 at HUAWEI CONNECT on September 17, Alibaba unveiled its new unified training-and-inference AI chip, Zhenwu V900, at the Apsara Conference in Hangzhou on September 22 — which Alibaba calls "the most powerful Chinese self-developed AI chip in terms of compute performance to date." This article is compiled from Alibaba's official announcements and reports from Sina Tech, C114, Huanqiu.com, and other sources.


1. Single Chip: 3x M890, 216GB + 1200GB/s​

MetricZhenwu V900 (this launch)Zhenwu M890 (previous generation)
Performance3x Zhenwu M890 (official figure; absolute value undisclosed)FP16 600 TFLOPS (as catalogued on this site)
Memory216 GB144 GB (HBM3)
Chip-to-chip interconnect1200 GB/s—
PrecisionNative FP8 / FP4 (including high-precision training)—
PositioningUnified training and inference (trillion-parameter-scale training + low-precision inference)Unified training and inference
Mass production2027 Q1, scaled deployment in Alibaba Cloud data centersAlready deployed at scale

Three takeaways:

  • Memory crosses into the 200GB+ tier: 216GB puts it in the same capacity class as the Ascend 960DT (288GB self-developed HBM) and NVIDIA Rubin (288GB HBM4), leveling the capacity threshold for long-context and very large MoE models;
  • 1200GB/s chip-to-chip interconnect: laying the foundation for the supernode's "memory-semantics interconnect" — the chip-level prerequisite that pairs with ICN Switch;
  • Precision coverage across all scenarios: officially described as "high-precision training, low-precision and ultra-low-precision inference across all scenarios," with native FP8/FP4 support aligned with the common spec of 2026's new cards.

The absolute single-chip compute figure has not been officially disclosed; this site records it using the official relative figure of "3x M890." See the Zhenwu M890 spec page for M890 details.

2. System Level: ICN Switch + Panjiu Supernode, a 500,000-Card Single Cluster​

V900's real selling point is not the single chip but system-level collaboration:

  • ICN Switch self-developed interconnect chip: once connected, the supernode gains native memory semantics and unified memory addressing, with a thousand cards interconnected at full bandwidth — over a thousand V900s can "work together like a single super chip";
  • Panjiu supernode server: integrates V900 (compute) + ICN Switch (interconnect) + Panmai intelligent NIC (network) + Zhenyue SSD controller (storage), a fully self-developed compute-storage-network stack;
  • 500,000-card single cluster: combined with Alibaba Cloud's next-generation intelligent computing center network architecture, a single cluster can scale up to 500,000 cards.

This mirrors Huawei's "11 key chips" approach: the unit of competition has shifted from the single chip to whole-system delivery capability — Zhenwu handles compute, Yitian handles general-purpose computing, Panmai handles networking, Zhenyue handles storage, and ICN Switch handles interconnect.

3. Business and Roadmap​

  • The Zhenwu family has served over 650+ enterprise customers (as of June 2026), spanning autonomous driving, finance, large models, embodied AI, energy, and manufacturing;
  • Supernodes based on the M890 are already deployed at scale, running models with over 2 trillion parameters such as Qwen3.8 and Kimi K3; Alibaba Cloud will add new serving nodes in Q4 to expand supernode supply;
  • Roadmap: V900 enters mass production and sales in 2027 Q1; Zhenwu J900 is planned for release in 2027 Q3;
  • CPU synergy: Yitian 720 / 730 arrive in 2027 (the 730 is the first to adopt T-Head's fully self-developed CPU microarchitecture, with single-core SPECint2017/GHz up to 1.4x that of Yitian 710); the 2029 Yitian 750 will interconnect directly with Zhenwu AI chips via the ICN bus;
  • Alibaba Group CEO Eddie Wu said T-Head's AI chip annual shipment volume will increase substantially.

4. Competitive Coordinates: Two Swords in One Week​

Viewing the two mid-September launches side by side, the landscape of "system-level competition" among domestic AI chips is now clear:

DimensionHuawei Ascend 960 (9-17)Alibaba Zhenwu V900 (9-22)
Launch eventHC2026Apsara Conference 2026
Per-card memory288GB (self-developed HBM)216GB
Memory bandwidth9.6 TB/sUndisclosed
InterconnectLinJu UnifiedBus / NPO optical interconnectICN Switch memory-semantics interconnect
SupernodeAscend 960 supernode (4,096 cards, 8 EFLOPS FP8)Panjiu supernode (500,000-card single cluster)
Availability2027 Q22027 Q1

Huawei is taking the "supernode + open-source CANN ecosystem" route, while Alibaba is taking the "full cloud stack + open-source model ecosystem" route; both still trail in per-card specs, but what they deliver are procurable, operable ultra-large-scale clusters. The substitution logic against NVIDIA's CUDA ecosystem is shifting from "performance parity" to "supply certainty + system efficiency."

5. Summary​

  • V900: 3x M890, 216GB, 1200GB/s chip-to-chip interconnect, native FP8/FP4, mass production in 2027 Q1;
  • System: ICN Switch with thousand-card full bandwidth, Panjiu supernode with a fully self-developed compute-storage-network stack, 500,000-card single cluster;
  • Cadence: J900 in 2027 Q3, Yitian 730 in 2027, Yitian 750 in 2029 — T-Head's first three-year generational roadmap;
  • What to watch: actual mass production and Alibaba Cloud deployment scale in 2027 Q1, disclosure of V900's absolute compute, and the possibility of external supply of ICN Switch.

Further Reading​

References​

  • Huanqiu.com: T-Head launches new unified training-and-inference AI chip Zhenwu V900 (2026-09-22)
  • Sina Tech / TechWeb: Alibaba T-Head launches new AI chip Zhenwu V900, mass production in the first quarter of 2027
  • C114: Alibaba launches new AI chip Zhenwu V900, mass production in 2027 Q1

This article is compiled from Alibaba's official announcements and public reports. The absolute single-chip compute of V900 has not been officially disclosed; supernode and cluster scale figures are official claims, subject to actual future delivery.