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18 posts tagged with "国产AI芯片"

中国国产AI芯片全产业链进展

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燧原、壁仞、登临、天数智芯:二线国产 AI 芯片厂商动态盘点

· 4 min read
Industry Research Team

华为昇腾与寒武纪之外,一批二线国产 AI 芯片厂商正在 2026 年集体进入收获期:上市潮、大厂订单与超节点产品同时落地,国产算力的第二梯队正在成形。

资本市场:从独角兽到上市公司的批量切换​

2026 年是国产 AI 芯片的上市大年。燧原科技的科创板 IPO 已过会并获注册批复,拟募资 60 亿元,公司自研迭代了四代架构、五款云端 AI 芯片;壁仞科技于 2026 年 1 月 2 日在港交所挂牌,开盘大涨 82%,市值一度突破千亿港元,成为港股 GPU 第一股;天数智芯也在 2026 年 1 月登陆港交所。据业界统计,摩尔线程、沐曦等厂商同样在冲刺科创板,"国产 GPU 四小龙"有望在资本市场聚齐。

厂商资本进展2026 年代表动作
燧原科技科创板过会并获注册,拟募资 60 亿元联合中兴发布云燧 ESL64-O 无线缆超节点
壁仞科技港交所上市,市值一度破千亿港元BR2xx 芯粒光互连千卡超节点,20 余款大模型当日适配
天数智芯2026 年 1 月港交所上市据媒体报道与字节跳动洽谈至少 5 万颗推理 GPU 采购
登临科技据公开报道持续推进融资与商用聚焦推理加速场景的规模化落地

产品与订单:超节点成为竞争主线​

2026 世界人工智能大会清晰地展示了行业竞争重心的迁移:从单芯片算力比拼转向芯片、高速互联与整机集群的系统级较量。壁仞科技推出基于芯粒架构 BR2xx 芯片的光互连千卡超节点,最多 1024 张 GPU 可共享同一内存空间;燧原科技联合中兴通讯发布的云燧 ESL64-O 超节点采用正交无背板设计,实现零线缆以大幅降低互联成本,其与腾讯云合作的"燎原"智算集群 3.0 已完成数千卡至万卡级部署。

订单侧的突破更具标志性意义。据多家媒体援引消息报道,字节跳动正与天数智芯洽谈采购至少 5 万颗智铠系列云端推理 GPU,若落地将成为继华为、寒武纪之后字节跳动的第三大国产 GPU 供应商;业界普遍认为,国产推理芯片定价约为英伟达同级产品的六到七成,成本优势叠加安全可靠测评的政策导向,正在推动互联网大厂从试点采购转向规模导入。登临科技等专注推理加速的厂商,也在互联网与行业客户中持续推进规模化商用。

生态与隐忧:窗口期不会永远敞开​

软件生态的比拼同样白热化。壁仞科技已对智谱 GLM、DeepSeek、通义千问等 20 余款头部大模型完成当日同步适配,其中 DeepSeek 全系列适配据称仅用数小时;2026 年 5 月,首批 9 款国产芯片获评国家最高安全可靠等级,壁仞、天数智芯等均榜上有名,信创需求的井喷进一步打开了市场空间。

但隐忧同样明确:先进制程产能受限于代工排期,交付能力决定谁能兑现政策红利;英伟达下一代架构随时可能随出口政策变化重返中国市场,国产芯片的时间差优势存在收窄风险。二线厂商能否从"能跑"走向"好用、稳定、规模供货",仍是决定最终座次的关键。

小结​

2026 年的国产 AI 芯片第二梯队,第一次同时拥有了资本弹药、大厂订单与系统级产品能力。燧原、壁仞、天数智芯的上市潮解决了资金可持续性,超节点与大模型适配解决了生态可用性,剩下的问题——产能与长期竞争力——将在未来两年给出答案。

徐直军 HC2026 访谈:昇腾950DT年底规模供货,"昇腾中国份额已超英伟达"

· 6 min read
Industry Research Team

华为全联接大会(HC2026)期间,华为轮值董事长徐直军在接受采访时给出了昇腾950系列的最新进度:950PR 已上市但量不大,950DT 超节点年底规模供货,并首次松口"昇腾中国份额已超英伟达"。

访谈要点:950PR 已上市,950DT 年底规模供货​

华为全联接大会(HC2026)在上海举行,展会现场展出了昇腾950和 Atlas 950 超节点。徐直军在采访中把昇腾950系列的节奏讲得非常具体:

  • 昇腾950系列分为 PR 和 DT 两个版本;
  • 950PR 已于 2026 年第一季度正式发布上市,主要面向推理场景,但"上市量不算大";
  • 基于 950DT 的超节点主要用于训练,目前还在测试中,规模供货预计今年年底或明年初。

两代产品的分工清晰:950PR 先行落地承接推理需求,950DT 则押注训练场景,承担更重的算力任务。

"能产多少就供多少":产能成了第一约束​

关于 950DT 的训练表现和供货节奏,徐直军的原话值得完整引用:

"我们和各家模型厂商做了很多沟通交流,从目前测试结果来看,950DT的训练表现非常不错,我相信从明年开始,大量模型的训练会构筑在950DT超节点上。未来关键可能不在于我们推动的力度有多大,而在于我们的供货能力有多大。现在能产多少就供多少,我们希望产业链加快扩产,快一点、多产一点。"

这段话透露出一个重要信号:对国产 AI 芯片而言,需求侧已经不是瓶颈,产能才是。徐直军把"供货能力"而非"推动力度"定义为未来的关键变量,等于公开向产业链喊话扩产——"快一点、多产一点"的表述,把扩产的紧迫性摆到了台面上。

份额表态:"昇腾应该已经超过了英伟达"​

在市场地位问题上,徐直军的表述同样直接:

"在中国市场要统计英伟达的市场占有率很难,但如果从华为能够统计到的数据看,昇腾应该已经超过了英伟达。"

这句话需要仔细解读。徐直军本人也承认统计口径的困难——英伟达在中国市场以何种形式、多大数量出货,外界很难完整统计。华为的判断基于"华为能够统计到的数据",这是一个有限口径的推断,而非权威市场份额数字。但这是华为高层首次公开作出这一表述,其信号意义大于数字本身。

海外策略:暂不全面拓展​

关于国际化,徐直军给出了明确的优先级:"目前昇腾满足国内市场需求还远远不足,所以没有全面拓展海外市场的计划。但确有少数国家做了测试和供给,但量非常少。"

换句话说,海外市场目前只是零星试点,华为的全部产能仍将优先投向国内。这与其"供货能力是第一约束"的判断是自洽的:产能有限的前提下,先满足国内是唯一合理的选择。

时间线与定价背景​

把 HC2026 前后的公开信息放在一起看,昇腾950的落地节奏如下:

事项状态
昇腾950PR(推理)2026年第一季度正式发布上市,上市量不算大
昇腾950DT 超节点(训练)测试中,规模供货预计今年年底或明年初
950DT 指示性价格超 25 万元(路透报道,HBM 成本驱动涨价)
Atlas 950 超节点HC2026 现场展出
昇腾950智算集群云服务9月30日国内商用

值得注意的是定价:路透此前报道 950DT 指示性价格超过 25 万元,主要驱动因素是 HBM 成本上涨。这与全球存储供应紧张的大背景互为印证——HBM 涨价正在推高所有 AI 芯片的成本曲线,国产芯片也无法置身事外。

分析:三个观察点​

**第一,"份额超英伟达"的口径与可信度。**虽然华为的统计口径有限,但结合出口管制后英伟达对华供应受限、国产芯片放量的大背景,昇腾在国内新增 AI 算力采购中的占比持续上升是行业普遍观察到的趋势,争议主要在幅度而非方向。华为选择在 HC2026 这个场合公开表态,本身也说明其对产能与产品力有了相当的底气。

第二,产能取代需求成为第一约束。"能产多少就供多少"说明国产芯片的瓶颈已经从"有没有人用"变成"产得出多少"。下一步的关键变量是先进制程与 HBM 供应链的扩产速度——这也是 950DT 价格超过 25 万元的根本原因。

**第三,950DT 对国产模型厂商的意义。**如果明年大量模型训练真的构筑在 950DT 超节点上,国产训练算力将第一次形成规模化的供应能力。配合 9 月 30 日已商用的昇腾950智算集群云服务,国产模型厂商在训练底座上将有更完整的选择,这对它们的成本结构和供应链安全都有直接影响。

小结​

徐直军在 HC2026 的访谈给出了两条硬信息:昇腾950PR 已上市、950DT 训练超节点年底规模供货;以及一句分量不轻的判断——"昇腾应该已经超过了英伟达"。产能而非需求,正在成为国产 AI 算力扩张的第一约束;而 950DT 能否如期放量,将决定明年国产大模型训练底座的成色。

2026年Q4 AI芯片前瞻:Rubin放量、Helios交付、昇腾950DT上市与国产新窗口

· 4 min read
Industry Research Team

2026年进入第四季度,AI芯片竞争的关键词从"发布"转向"交付"。Rubin能否持续放量、Helios能否如期爬坡、昇腾950DT如何定价上市,将共同决定2027年竞争格局的起点。

NVIDIA:Rubin放量与生态开放双线推进​

Q4期间NVIDIA的计划主线:

  • Vera Rubin NVL72:2026下半年持续放量,MLPerf Inference v6.1首秀已登顶(Qwen3-VL较GB300最高3.7倍),HBM4平台优势开始兑现;
  • N1X:基于RTX Spark的PC处理器按计划2026年秋季上市,打开消费级战场;
  • Blackwell Ultra(B300):租用价格参考Nebius口径约9.50美元/GPU小时,仍是当前租赁市场的重要基准;
  • 后续代际:Rubin Ultra等后续路线待发;
  • 生态动作:NVLink Fusion持续开放生态,NVHBM定制内存方案推进。
产品/计划Q4状态
Vera Rubin NVL722026下半年持续放量
N1X秋季上市
B300租用9.50美元/GPU小时(Nebius口径)
Rubin Ultra待发布
NVLink Fusion / NVHBM生态开放与定制内存推进

AMD:Helios从首发出货到Q4爬坡​

AMD在Q4的核心任务是交付:

  • Helios机架:MI455X首批出货目标Q3末,Q4进入量产爬坡阶段;
  • 客户部署:OpenAI 6GW、Meta 6GW部署合作推进中,微软作为首批客户计划2026年下半年交付;
  • MI430X:驱动欧洲LUMI-AI超算,拓展科学计算场景;
  • ROCm:软件生态继续补齐;
  • 下一代:Helios II / MI500级产品路线待公布。

华为:昇腾950DT上市与云服务全球商用​

华为Q4的关键节点最为明确:

  • 昇腾950DT:Q4上市,报价超25万元;
  • 昇腾950智算集群云服务:9月30日已国内商用,11月30日全球商用;
  • 960系列:计划2027年接棒,970/980排在2028-2029年。

阿里平头哥:真武V900量产倒计时​

平头哥的时间表指向2027年:真武V900计划2027年Q1量产上云,配套磐久AL128与50万卡集群规划;J900排期2027年Q3。Q4将进入量产前最后的验证阶段。

OpenAI/博通 Jalapeño:多吉瓦部署推进​

OpenAI与博通合作的Jalapeño定制芯片规格已明确:13.4 PFLOPS(4-bit精度)、232GB内存,多吉瓦部署规划正在推进。这枚自研芯片的量产进度,将直接影响OpenAI未来的算力自给率。

关键变量:三大约束​

Q4的交付兑现程度,将取决于三个外部约束:

  1. HBM供给:戴尔CEO警告2027年可能比2026年更紧缺,HBM产能是所有GPU路线图的共同瓶颈;
  2. 国产涨价传导:昇腾950DT涨价20%-50%、寒武纪690涨价20%-30%(路透,HBM成本驱动),涨价将传导至国产算力服务价格;
  3. 电力约束:Emerald AI/Google/NVIDIA成立的AEMA电网响应模式,预示电力正在成为算力扩张的第一性约束。

三条观察建议​

基于上述事实,给三类角色的观察点(非投资建议):

  • 采购方:昇腾950DT与寒武纪690的涨价幅度表明国产算力已进入卖方市场,锁量谈判宜早不宜迟;同时关注Helios Q4实际爬坡数据,作为第二供应源评估依据;
  • 开发者:ROCm生态补齐与NVLink Fusion开放,意味着2027年异构算力混布的软件门槛正在降低,可提前在推理侧做多框架适配;
  • 投资者:可跟踪的公开观察点包括——Helios首批交付兑现情况、昇腾950云服务11月30日全球商用落地、HBM价格走势对各家毛利率的影响信号。

小结​

2026年Q4是"交付验证季":NVIDIA Rubin放量、AMD Helios爬坡、昇腾950DT上市与云服务全球商用、平头哥V900量产倒计时——各家计划均已排定,剩下的变量集中在HBM供给、涨价传导与电力约束三点。所有时间节点以"计划/预计/排期"口径为准,Q4末回看兑现率,就是对2027年格局的最好预判。

昇腾950智算集群云服务正式商用:9月30日国内上线、11月30日全球商用

· 5 min read
Industry Research Team

华为全联接大会2026给出明确时间表:昇腾950智算集群云服务9月30日国内商用、11月30日全球商用,全球首个NPO超节点昇腾960同步亮相。

HUAWEI CONNECT 2026:商用时间表落定​

2026年9月17日,华为全联接大会在上海举行。大会上,华为披露了昇腾950智算集群云服务的商用节奏:9月30日国内商用,11月30日全球商用。从大会披露到国内上线仅半个月,节奏之紧,说明昇腾950超节点的规模化交付已经就绪。

关键节点时间/地点
华为全联接大会20262026年9月17日(上海)
昇腾950智算集群云服务国内商用2026年9月30日
昇腾950智算集群云服务全球商用2026年11月30日

"国内先行、两月后推向全球"的节奏也传递出另一个信号:昇腾不再只盯着国内市场,智算集群云服务将作为中国AI算力方案走出去的载体,参与全球算力供给的竞争。

昇腾960超节点:全球首个NPO超节点​

同期发布的昇腾960超节点,是全球首个NPO超节点(近封装光学超节点),关键规格如下:

指标数值
卡规模4096卡
算力8 EFLOPS FP8 / 16 EFLOPS FP4
显存1PB HBM
光互联方案5500个Hi-ONE光引擎,替代4.8万颗800G光模块
降功耗550kW
可用度99.8%
Hi-ONE单引擎传输容量7.2T

这组数字的核心看点在于光互联的代际切换:用5500个Hi-ONE光引擎替代4.8万颗800G光模块,降低550kW功耗,同时做到99.8%的可用度。NPO(近封装光学)路线在超节点规模下的价值被直观呈现——光模块数量下降一个数量级,意味着故障点、功耗与运维复杂度同步大幅收敛。在4096卡这种规模的系统里,互联可靠性直接决定训练任务的连续性。

昇腾950超节点:规模商用与SOTA背书​

昇腾950超节点已规模商用1000多套,落地行业覆盖互联网、运营商、金融、教育、医疗、交通、制造等。规模数字之外,更关键的背书是:昇腾950超节点是国内唯一训练出SOTA模型的超节点。

"能训练出SOTA模型"是对训练集群最硬核的检验——它证明的不仅是硬件规格,而是"集群规模+互联效率+软件栈"的组合在大规模训练中真实可用。对于正在选型的行业客户而言,这比任何纸面参数都更有说服力。

芯片路线图:960提前就绪,970/980排期明确​

华为还更新了昇腾芯片的推进节奏:

  • 昇腾960DT较原计划提前三个季度就绪;
  • 昇腾960PR提前一个季度就绪;
  • 2028年推出昇腾970,2029年推出昇腾980。

"提前就绪"在当前的供应链环境下格外难得——在全球先进制造资源紧张、HBM紧缺的背景下,按时甚至提前交付,本身就是工程与供应链能力的体现。而970/980排期明确到年份,则给生态伙伴与客户提供了可规划的长期预期。

CANN全面开源:生态数据盘点​

软件生态方面,昇腾的进展可以用一组数据概括——CANN已全面开源:

  • 外部开发者占比61%,月活跃开发者超5200名;
  • 40+模型实现原生训练;
  • 支持PyTorch、Triton、vLLM、veRL等90+开源项目;
  • 成为PyTorch官网首个中国算力平台。

其中"PyTorch官网首个中国算力平台"具有标志性意义:主流框架的原生适配,意味着开发者迁移成本大幅降低,而61%的外部开发者占比说明社区已经超出华为体系自身,形成外部贡献的正循环。

全栈协同:TaiShan 950与OceanStor M900​

硬件侧的配套升级同样值得关注。TaiShan 950超节点完成升级:支持4096节点、256TB统一内存池——统一内存池让CPU侧内存资源可以按需调度,与超节点的算力规模相匹配。存储侧,OceanStor M900上下文内存存储提供PB级KV Cache能力,直击大模型推理场景的上下文缓存需求:推理热门场景下,KV Cache的存取效率直接决定吞吐与首字延迟。

芯片(昇腾950/960)、CPU(TaiShan 950)、存储(OceanStor M900)、软件栈(CANN)四层同步演进,华为走的是典型的全栈协同路线。

小结​

从昇腾950智算集群云服务"9月30日国内、11月30日全球"的商用时间表,到昇腾960超节点"4096卡、8 EFLOPS FP8、16 EFLOPS FP4、1PB HBM、5500个Hi-ONE光引擎"的规格突破,再到昇腾950超节点规模商用1000多套、成为国内唯一训练出SOTA模型的超节点,以及CANN全面开源、外部开发者占比61%的生态进展,华为正以"芯片-超节点-云服务-开源生态"的全栈节奏推进昇腾路线图。昇腾970(2028)、昇腾980(2029)的排期已经明确——昇腾的追赶不再只是单点突破,而是体系化的持续推进。

Intelligent Compute to Hit 9,800 EFLOPS by 2030: Five Hard Targets in the ICT Industry "15th Five-Year" Plan

· 6 min read
Industry Research Team

This article is based on the MIIT "15th Five-Year" Plan for ICT Industry Development (issued in September 2026) and official interpretations by the People's Post and Telegraph News, The Paper, Huaxia Times, and other outlets.

In early September, the MIIT issued the "15th Five-Year" Plan for ICT Industry Development, drawing a roadmap for the ICT industry over the next five years with 13 major indicators and 26 key tasks. For the AI compute industry, this is the most substantive policy document — we have picked out five hard targets and break down their industry implications one by one.

Target 1: Intelligent Compute from 1,590 to 9,800 EFLOPS, More Than 5x Growth in Five Years​

This is the standout number in the entire plan. For reference:

  • As of the end of June 2026, national intelligent compute capacity had reached 2,185 EFLOPS, up 177% year over year — the first half alone overshot the year-end 2025 target (1,590 EFLOPS)
  • The country has built 42 10,000-card-class intelligent computing clusters; in July 2026, the first fully domestic 100,000-card-class AI compute cluster, the Sugon 8000, was completed in Zhengzhou
  • Huawei's rotating chairman Wang Tao's assessment: super-node clusters of more than 100,000 cards will become basic configuration by 2027

Going from 2,185 to 9,800 means that over the next four years the country must build 3.5 times the current installed base of intelligent computing facilities. The plan also calls for "orderly deployment of 10,000-card, 100,000-card and larger intelligent computing clusters" and "stepping up efforts to adapt domestic compute chips" — this is the most certain demand base for domestic AI chips over the next five years.

Target 2: Cumulative Information Infrastructure Investment of RMB 3.8 Trillion​

Some have compared this with the "14th Five-Year" figure of RMB 3.7 trillion and concluded that "investment has peaked." Official interpretations explicitly reject this claim: incremental capital is shifting from "scale expansion" to "quality-and-efficiency gains," precisely targeted at intelligent computing infrastructure, 10G optical networks, 6G, and other new tracks. The industry chain pull effect is changing accordingly — AI servers, high-speed optical interconnects, domestic compute chips, and new smart terminals were named as beneficiaries across the whole chain.

Target 3: PUE of New Large Compute Facilities Reduced Below 1.2​

At the end of the "14th Five-Year" period this figure was 1.25, and it must fall another 0.05 within five years — it doesn't sound like much, but with AI servers running at high load year-round and per-rack power density generally exceeding 20kW, every point of PUE reduction is a hard fight. The technical path laid out in the plan is very clear: liquid cooling.

  • The "15th Five-Year" Plan for ICT Industry Development: guide compute facilities to adopt high-efficiency energy-saving equipment and advanced technologies such as liquid cooling
  • The "15th Five-Year" Plan for Electronic Information Manufacturing Development (jointly issued by the MIIT and the NDRC on September 15): lists liquid cooling alongside high-bandwidth memory pooling and all-optical switching as key technologies to be broken through

Industry-side data confirms the trend: according to Omdia, liquid cooling's share of the global data center cooling market climbed from about 20% in 2024 to about 37% in 2025, with penetration expected to exceed 45% by 2029. The ceiling on compute expansion is shifting from chip supply to power supply, and the energy-efficiency constraint of "compute up, energy down" will be the norm for the next five years.

Target 4: Advanced Storage Capacity of 1,700 EB, More Than 2x Growth​

While intelligent compute grows 5x, advanced storage grows more than 2x — storage-compute coordination is given equal weight. The logic: training checkpoints for large models, and the intermediate states and contextual memory of agent inference, are all stored in layers within high-performance storage. As of the end of June, national storage capacity totaled about 2,021 EB, of which advanced storage accounted for about 32%; the 1,700 EB advanced storage target for 2030 means structural upgrading matters more than total-volume growth.

A direct implication for chip selection: KV cache and long context are eating the memory budget — when evaluating AI servers, memory capacity and memory bandwidth should carry more weight than peak compute.

Target 5: The Agent Interconnection Network Enters the Plan for the First Time​

This is the most forward-looking part of the plan: the "agent interconnection network" gets its own dedicated column, deploying four areas of work — building an agent network identifier system, accelerating the construction and application of agent network infrastructure, promoting global interconnection, and establishing a space governance system. It also explicitly states "launching 6G commercial use in a timely manner."

As AI shifts from "applications for people" to "agent infrastructure," the role of the communications network upgrades from connecting people to connecting agents — providing a national-level narrative for the distributed deployment of inference compute (edge inference, compute scheduling).

Three Judgments for Compute Practitioners​

JudgmentBasis
Domestic compute demand is highly certainThe plan explicitly states "stepping up efforts to adapt domestic compute chips" + the 100,000-card cluster build cycle has begun
Energy-efficiency targets become hard siting constraintsPUE below 1.2 + liquid cooling named as a key technology; high-density liquid cooling solutions take priority
Inference compute sinks to the edge on demand"Deploy inference compute facilities as needed for scenarios"; edge and regional compute centers enjoy a policy window

Under a 5x compute expansion target, what has always been scarce is not planning but chips, power, and delivery capability. For buyers, the supply window remains tight; for solution selection, we recommend using the TCO Calculator to convert PUE differences into electricity costs — the gap between 1.25 and 1.2 amounts to tens of millions on the electricity bill of a 10,000-card cluster.

Summary​

The "15th Five-Year" Plan writes intelligent compute into a national-level project: 5x compute, 2x storage, RMB 3.8 trillion in investment, PUE 1.2, and the agent internet. Looking back five years from now, the wave of domestic 100,000-card clusters in the second half of 2026 may well prove to be the starting point of this curve.

(Plan data is cited from MIIT documents and official media interpretations; market data is cited from statistics by CAICT, Omdia, and other institutions.)

JD Cloud's 100,000-Card Cluster Bets on Moore Threads: Domestic GPUs Enter a Top AI Cloud's Core Compute Base for the First Time

· 6 min read
Industry Research Team

This article is based on official announcements from the 2026 JD Global Technology Explorer Conference (September 9) and public market information; order values and revenue forecasts are brokerage/media estimates, not company announcements.

On September 9, at the 2026 JD Global Technology Explorer Conference, JD Cloud announced a milestone decision: partnering with Moore Threads to build a 100,000-card full-function GPU cluster, creating hyperscale domestic intelligent computing infrastructure.

Two keywords in this sentence deserve amplification: "full-function GPU" and "100,000-card-class core cluster." The former means it must run not just inference but the front lines of large model training, inference, and embodied AI; the latter means a domestic GPU has, for the first time, been placed at the core of a top AI cloud provider's compute base — not a pilot, not an adaptation, not an all-in-one appliance, but 100,000 cards.

1. Partnership Details: From 10,000 to 100,000 Cards — How Big Is the Order?​

  • Prior foundation: JD Cloud has already built a domestic 10,000-card cluster with Moore Threads and other partners; this move is a magnitude leap from 10,000 to 100,000 cards
  • Order scale: According to market and brokerage information, GPU modules are supplied exclusively by Moore Threads, with a total order value of about RMB 20-30 billion; revenue can be recognized as early as next year according to delivery cadence. Some brokerages have raised Moore Threads' revenue expectation for next year to RMB 15-20 billion (this estimate is not a company announcement; refer to official disclosures)
  • Partnership depth: Full-stack coordination from chips and cloud platform to model training, supporting the iteration of JD's JoyAI model family and forming a closed loop of "data, training, simulation, deployment"
  • Openness: Compute is open to all industries, focused on large model training, inference, and embodied AI

Moore Threads founder Zhang Jianzhong was direct on stage: "The Scaling Law still holds — 100,000-card clusters are an inevitable trend." JD Cloud President Cao Peng positioned domestic compute as a core pillar of JD's physical AI strategy.

2. Why Moore Threads? Three Calculations Behind the Procurement Logic​

Tech companies buy cards with no sentiment involved. JD's choice of Moore Threads comes down to three calculations that all add up:

1. The stability calculation: Moore Threads has commercially deployed thousand-card and 10,000-card large clusters under a single network, and has achieved breakthroughs in core training scenarios such as foundation models, embodied brains, and world models — the engineering validation of a 10,000-card cluster is the prerequisite for 100,000 cards; this is not a cold start.

2. The integration calculation: Full-function GPUs can plug into existing IT systems and cloud platform scheduling, and the MUSA software stack's adaptation to large model frameworks has already passed training-grade workloads.

3. The ROI calculation: This is the most critical shift. Buyers of domestic GPUs used to be mostly "policy-friendly" projects; JD writing a 100,000-card cluster into its capital expenditure means the product's return on investment can now stand up to investor scrutiny — the buyer structure shifting from "daring to use" to "rushing to use" is the hallmark of commercial maturity for domestic GPUs.

3. S6000: Next-Gen Chip Taped Out and Back, with a Dual-Supply Safeguard​

According to market information, Moore Threads' next-generation chip, the S6000, has successfully come back from the fab and been distributed to vendors for testing, with ample FAB and memory supply guarantees. Note that the S6000 has not been officially released and its specifications are not public; this article makes no speculation. The on-sale flagship MTT S5000 has on-site data of 400 TFLOPS FP16 and 80GB of memory (the 1.6TB/s bandwidth is HBM-class).

Regarding HBM supply constraints, Moore Threads' response strategy is reportedly "next-generation product iteration + multi-source supply chain safeguards" — until domestic HBM capacity ramp-up is complete, this is the same problem every domestic GPU vendor must solve.

4. "100,000 Cards" Is Not One Company's Game: The Domestic GPU Cluster Landscape​

It is worth widening the view — 100,000 cards is now a collective goal for domestic compute:

Player100,000-Card MoveCompute Base
JD CloudAnnounced co-built 100,000-card cluster on September 9Moore Threads full-function GPU
Sugon 8000Released at WAIC in July, completed in Zhengzhou; a fully domestic 100,000-card AI compute clusterHygon DCU (of the Shensuan BW1000 family)
HuaweiAtlas 950 SuperPoD super node (8,192 cards); 100,000-card super node in 2027Ascend 950/960

Two chip routes (full-function GPU vs DCU vs NPU) and two paths (commercial cloud vs national supercomputing) point to the same validation question: can domestic compute reliably run real training workloads at 100,000-card scale. It is worth emphasizing that there is currently no public third-party benchmark comparison for the Moore Threads x JD cluster, and no completion timetable — going from "usable" to "running well" at 100,000 cards still requires engineering validation.

5. The Capital Markets Perspective​

Moore Threads listed on the STAR Market in December 2025: an IPO price of RMB 114.28, closing at RMB 600.5 on the first day; 2025 revenue of RMB 1.505 billion (up 243.37% year over year), with a net loss of about RMB 1.001 billion. If the brokerage-raised revenue expectation of RMB 15-20 billion materializes, 2027 will be the key inflection point from "high-growth loss-making" to "profitable at scale" — which would also become the first complete answer sheet for the domestic GPU business model.

Summary​

From debuting with DeepSeek all-in-one appliances in 2025 to entering a 100,000-card core cluster in 2026, domestic GPUs completed the cognitive leap from "usable" to "commercially viable at scale" in under two years. The value of JD Cloud's order lies not in its amount but in its significance as a sample: when top internet buyers begin procuring domestic GPUs on ROI logic, substitution is no longer a policy narrative but a commercial fact.

(Order values, revenue forecasts, and supply chain status come from public market information and brokerage research estimates; refer to company announcements; chip specification data is available in the on-site full comparison table.)

2026 Domestic AI Chip Progress: Huawei Ascend 950, Baidu Kunlun M100, Alibaba T-Head M890 Fully Explained

· 15 min read
Industry Research Team

In 2026, China's domestic AI chip industry has entered a period of full-scale explosion. The three giants — Huawei Ascend, Baidu Kunlun, and Alibaba T-Head — have successively launched next-generation products, while Cambricon, MetaX, Enflame, and Iluvatar have also achieved important breakthroughs.

This article comprehensively analyzes 2026 domestic AI chip progress across four dimensions: product launches, technology breakthroughs, market dynamics, and ecosystem building.


1. Huawei Ascend: 950 series launched, 960/970 roadmap clear​

1.1 Ascend 950PR (launched Q1 2026)​

Core specs:

ItemParameter
Launch dateMarch 21, 2026
PlatformAtlas 350 accelerator card
HBM capacity128 GB (Huawei in-house HiBL 1.0 HBM)
Memory bandwidth1.6 TB/s
FP8 compute1 PFLOPS
PositioningInference-specific (Prefill stage)
Performance vs.Single-card compute is 2.87× NVIDIA H20

Technology innovations:

  • First adoption of Huawei in-house HBM solution (HiBL 1.0), lowering cost
  • Supports FP8 low-precision compute, 3× inference energy-efficiency improvement
  • Optimized for inference scenarios such as video recommendation and real-time interaction

Commercialization progress:

  • Mass supply began in Q1 2026
  • Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud
  • Priced around ¥100,000/card (¥80,000 for key accounts), ~30% lower than comparable competitors

1.2 Ascend 950DT (launched Q4 2026)​

Core specs:

ItemParameter
Launch dateQ4 2026 (expected October)
HBM capacity144 GB (Huawei in-house HiZQ 2.0 HBM)
Memory bandwidth4 TB/s (HiZQ 2.0 technology)
FP8 compute1 PFLOPS
PositioningInference + training (Decode stage + training tasks)
Technology innovationFirst to carry in-house HiZQ 2.0 memory technology

Technology innovations:

  • Adopts HiZQ 2.0 memory technology, 2× data-movement efficiency
  • Supports FP8/FP4 low-precision compute, balancing performance and efficiency
  • Optimized for scenarios such as dialogue generation and large-model training

1.3 950 SuperNode (launched Q4 2026)​

System specs:

ItemConfiguration
Max interconnected chips8,192 chips
Total FP8 compute1 EFLOPS (1,024-card scale)
1024-card version16 liquid-cooled cabinets, 64 chips per cabinet
Supported modelsTrillion-parameter large-model training
Deployment progress1,024-card version already in deployment

Performance comparison:

  • 950 SuperNode outperforms NVIDIA's 2027 NVL576 system
  • Leads by 20% in trillion-parameter model training

1.4 Ascend 960/970 roadmap​

Chip modelLaunchCore specsPositioning
Ascend 960Q4 2027N+3 process, 288GB HBM, FP8 2 PFLOPS, 30%+ better energy efficiency than 910CUltra-large-scale training
Ascend 970Q4 2028N+3 process, FP4 8 PFLOPS, 4 TB/s bandwidth, supports trillion-parameter modelsNext-gen AI architecture (MoE, etc.)

Technology breakthroughs:

  • Process upgrade: from N+2 (7nm-class) to N+3 (5nm-class)
  • Memory capacity doubled: from 144GB (950DT) to 288GB (960/970)
  • Energy efficiency improved: 960/970 are 30%+ better than 910C
  • Precision optimized: 970 supports FP4 precision, optimized for next-gen AI architectures (MoE, etc.)

1.5 Commercialization progress​

Shipment data:

  • 384-card SuperNode: over 500 units deployed, the only truly large-scale commercial SuperNode in China
  • 2026 shipment target: 800k chips (1M cumulative)
  • Market share: 60% of China's AI chip market

Ecosystem building:

  • CANN compiler: open-sourced end of 2025, seamless PyTorch/TensorFlow migration
  • Mind series toolchains: fully open, lowering the developer barrier
  • Ecosystem partners: over 3,000
  • Developer community: over 500k registered developers

2. Baidu Kunlun: M100 inference-specific, Tianchi SuperNode deployed​

2.1 Kunlun M100 (launched early 2026)​

Core specs:

ItemParameter
Launch dateEarly 2026 (expected Q2)
PositioningInference-specific
ArchitectureIn-house XPU-P architecture (inference-optimized)
Process7nm (SMIC N+2)
HBM capacity64 GB (inference-optimized)
TDP250 W (low-power inference)
Performance vs.1.5× P800 inference, 38% lower power

Technology innovations:

  • Adopts RISC-V open instruction set, adding 50+ AI-specific instructions
  • Compute per watt reaches 8.3 TOPS/W, 2.1× the industry average
  • Supports models from 10 billion to 100 billion parameters for inference

Commercialization progress:

  • Mass supply in Q2 2026
  • Key customers: Baidu Smart Cloud, China Merchants Bank, Southern Grid, Geely Auto
  • Priced around ¥60,000/card, clear cost-performance advantage

2.2 Kunlun M300 (launched early 2027)​

Core specs:

ItemParameter
Launch dateQ1 2027 (expected March)
PositioningUltra-large-scale multimodal training
ArchitectureIn-house XPU-P architecture (multimodal-optimized)
Process5nm (SMIC N+3)
HBM capacity256 GB HBM4
TDP500 W
ModalitiesText, images, video and other data types

Technology innovations:

  • Adopts HBM4 memory, bandwidth up to 3.2 TB/s
  • Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
  • Native support for multimodal model training (text + image + video)

2.3 Tianchi 256-card SuperNode (launched June 2026)​

System specs:

ItemConfiguration
Launch dateJune 2026 (expected)
Chip count256 Kunlun P800/M100
Effective training rate97%
Inter-chip bandwidth1.2 TB/s
Validated modelsBaidu ERNIE 5.1 and other key large models

Performance breakthroughs:

  • Fully domestic SuperNode, fully autonomous and controllable from chip to network
  • 97% effective training rate, surpassing NVIDIA DGX SuperPOD's 95%
  • Training validation completed for Baidu ERNIE 5.1 and other key large models

2.4 Commercialization progress​

Shipment data:

  • P800: 150k shipped in 2025, 200k target in 2026
  • Ten-thousand-card clusters: multiple P800-based clusters delivered
  • Market share: 20% of China's AI chip market

Customer coverage:

  • External customer revenue share: over 50% in 2025
  • China Mobile AI server procurement: P800-based bids won 70%, 70%, 100% shares
  • Key customers: China Merchants Bank, Southern Grid, Geely Auto, iFlytek

IPO progress:

  • May 2026: officially launched STAR Market IPO tutoring
  • Plans "A+H" model — simultaneous A-share and Hong Kong listings
  • Valuation exceeds ¥10 billion

3. Alibaba T-Head: M890 3× performance, Zhenwu series ships 560k units​

3.1 T-Head M890 (launched Q2 2026)​

Core specs:

ItemParameter
Launch dateQ2 2026 (Alibaba Cloud Summit)
Performance3× previous generation
HBM capacity144 GB
Inter-chip bandwidth800 GB/s
Precision supportFP8, FP4 low-precision compute
PositioningFull training + inference pipeline

Technology innovations:

  • Adopts in-house ICN inter-chip protocol, inter-chip latency under 150 ns
  • Companion PCCF communication library and ICN Switch chip enable full-bandwidth interconnect of 64 chips within a single node
  • Supports FP8/FP4 low-precision compute, balancing performance and efficiency

3.2 T-Head V900 (launched Q3 2027)​

Core specs:

ItemParameter
Launch dateQ3 2027 (expected September)
Performance3× again over M890
HBM capacity216 GB
Inter-chip bandwidth1,200 GB/s
PositioningUltra-large-scale training

3.3 T-Head G900 (launched Q3 2028)​

Core specs:

ItemParameter
Launch dateQ3 2028 (expected September)
PositioningFlagship product for next-gen compute demand
Technology innovationSupports full-pipeline training of trillion-parameter models

3.4 Zhenwu series commercialization progress​

Shipment data:

  • Cumulative shipments: over 560k units as of April 2026
  • Customers served: 20+ industries, 400+ customers
  • Autonomous driving: over 130k units, 30+ customers
  • Finance: over 100k units, 150+ customers

Performance advantage:

  • At equal precision, Zhenwu series single-machine inference outperforms comparable products by 50%+ on average
  • Panjiu server SuperNode architecture supports trillion-parameter large models on a single node

Full product line:

  • Zhenwu series AI chips: training + inference
  • Yitian series CPUs: data center CPUs
  • ICN Switch interconnect chip: inter-chip interconnect
  • Camel920 400G smart NIC: high-speed networking
  • Junyue series storage controller chips: storage optimization

4. Other domestic chip vendor progress​

4.1 Cambricon MLU590 (launched Q1 2026)​

Core specs:

ItemParameter
Launch dateQ1 2026 (expected March)
ArchitectureMLUarch 09 (in-house)
Process7nm (SMIC N+2)
HBM capacity128 GB HBM3
TDP350 W
PositioningTraining + inference

Technology innovations:

  • MLUarch 09 architecture, 2× compute over MLU590
  • Supports FP8/FP4 low-precision compute, 2.5× inference energy-efficiency
  • Native MoE architecture support, 3× sparse-model inference efficiency

Commercialization progress:

  • Q1 2026: sample deliveries begun
  • Key customers: Chinese government, state-owned enterprises, research institutes
  • Day-0 adaptation of DeepSeek-V3 671B achieved

4.2 MetaX Xiyun C600 (launched Q2 2026)​

Core specs:

ItemParameter
Launch dateQ2 2026 (expected June)
ArchitectureMXMACA 3.0 (CUDA-compatible)
Process7nm (SMIC N+2)
HBM capacity128 GB HBM3
TDP350 W
PositioningTraining + inference

Technology innovations:

  • MXMACA 3.0 architecture, CUDA-compatible, low migration cost
  • Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
  • Fully domestic supply chain, autonomous and controllable from chip to packaging

Commercialization progress:

  • Q2 2026: sample deliveries begun
  • Key customers: Chinese government, state-owned enterprises, research institutes
  • Adapted models include LLaMA, ChatGLM, Baichuan

4.3 Enflame S60 (launched Q3 2026)​

Core specs:

ItemParameter
Launch dateQ3 2026 (expected September)
ArchitectureGCU 3.0 (in-house)
Process7nm (SMIC N+2)
HBM capacity96 GB HBM3
TDP300 W
PositioningInference-specific

Technology innovations:

  • GCU 3.0 architecture, 2.5× inference performance over S30
  • Supports FP8 low-precision compute, 3× inference energy-efficiency
  • Hardware-level virtualization, single card split into 64 virtual instances

Commercialization progress:

  • Q3 2026: sample deliveries begun
  • Key customers: Tencent Cloud, China Telecom, China Unicom
  • Priced around ¥50,000/card

4.4 Iluvatar VA10 (launched Q4 2026)​

Core specs:

ItemParameter
Launch dateQ4 2026 (expected December)
ArchitectureHVMA 2.0 (in-house)
Process7nm (SMIC N+2)
HBM capacity64 GB HBM3
TDP250 W
PositioningVideo processing + AI inference

Technology innovations:

  • HVMA 2.0 architecture, 3× video processing performance over VA10
  • Supports 8K real-time video processing, 2× video AI inference performance
  • Hardware-level video codec, supports H.264/H.265/AV1

Commercialization progress:

  • Q4 2026: sample deliveries begun
  • Key customers: ByteDance, Kuaishou, Bilibili
  • Priced around ¥40,000/card

4.5 Hygon DCU K100 (launched Q2 2026)​

Core specs:

ItemParameter
Launch dateQ2 2026 (expected June)
Architecturex86-compatible GPGPU (in-house DCU)
Process7nm (SMIC N+2)
HBM capacity128 GB HBM3
TDP400 W
PositioningTraining + inference (x86 ecosystem-compatible)

Technology innovations:

  • DCU architecture, x86-compatible, extremely low migration cost
  • Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
  • Fully domestic supply chain, autonomous and controllable from chip to packaging

Commercialization progress:

  • Q2 2026: sample deliveries begun
  • Key customers: Chinese government, state-owned enterprises, research institutes
  • Adaptation of DeepSeek-V3 671B achieved

5. 2026 domestic AI chip market landscape​

5.1 Market share (2026)​

VendorMarket shareShipments (10k units)Flagship products
Huawei Ascend60%80910C, 950PR, 950DT
Baidu Kunlun20%20P800, M100
Alibaba T-Head10%10M890, Zhenwu series
Cambricon5%5MLU590
MetaX3%3C600
Others2%2S60, VA10, K100

5.2 Technology roadmap comparison​

VendorArchitecture routeEcosystem compatibilityProcessSupply chain
Huawei AscendDa Vinci (in-house)CANN (CUDA-compatible)SMIC N+2/N+3Fully domestic
Baidu KunlunXPU-P (in-house)XPU-P (CUDA-compatible)SMIC N+2/N+3Fully domestic
Alibaba T-HeadIn-house RISC-VCUDA-compatibleSMIC N+2/N+3Fully domestic
CambriconMLUarch (in-house)CANN (CUDA-compatible)SMIC N+2Fully domestic
MetaXMXMACA (CUDA-compatible)CUDA-compatibleSMIC N+2Fully domestic
EnflameGCU (in-house)In-house ecosystemSMIC N+2Fully domestic
IluvatarHVMA (in-house)In-house ecosystemSMIC N+2Fully domestic
HygonDCU (x86-compatible)x86 ecosystem-compatibleSMIC N+2Fully domestic

5.3 Supply chain security comparison​

VendorWafer fabHBM supplyPackaging/testSupply chain rating
Huawei AscendSMICHuawei in-house HiBL/HiZQJCET/TFME⭐⭐⭐⭐⭐
Baidu KunlunSMICChangXin MemoryJCET/TFME⭐⭐⭐⭐⭐
Alibaba T-HeadSMICChangXin MemoryJCET/TFME⭐⭐⭐⭐⭐
CambriconSMICSamsung/HynixJCET/TFME⭐⭐⭐⭐
MetaXSMICSamsung/HynixJCET/TFME⭐⭐⭐⭐
EnflameSMICSamsung/HynixJCET/TFME⭐⭐⭐⭐
IluvatarSMICSamsung/HynixJCET/TFME⭐⭐⭐⭐
HygonSMICSamsung/HynixJCET/TFME⭐⭐⭐⭐

6. 2026 domestic AI chip technology breakthroughs​

6.1 Process breakthroughs​

Node2026 statusRepresentative productsNotes
7nm (N+2)Mass production910C, P800, M890SMIC N+2 mature
5nm (N+3)Mass production960, 970, M300SMIC N+3 mass production in 2026
3nmIn developmentNext-gen productsMass production expected 2028

6.2 Packaging breakthroughs​

Packaging2026 statusRepresentative productsNotes
ChipletMature910C, 950PR/DTDual-die packaging, higher yield
3D stackingMatureP800, M890HBM3e 3D stacking
CoWoSMatureAll high-end productsTSMC CoWoS
Domestic packagingMass production960, 970, M300JCET/TFME mass production

6.3 Memory breakthroughs​

Memory2026 statusRepresentative productsNotes
HBM2EMature910CSamsung supply
HBM3MatureP800, MLU590, C600Samsung/Hynix supply
HBM3eMature950PR, M890Samsung/Hynix supply
Huawei in-house HBMMass production950PR (HiBL 1.0), 950DT (HiZQ 2.0)Huawei in-house, lower cost
HBM4In developmentM300 (2027)Mass production expected 2027

6.4 Interconnect breakthroughs​

Interconnect2026 statusRepresentative productsNotes
AscendLinkMature910C, 950PR/DTHuawei in-house, 784 GB/s
XCCLMatureP800, M100Kunlun in-house, 1.2 TB/s
ICNMatureM890, V900Alibaba in-house, 800 GB/s
Domestic optical modulesMass productionAll SuperNodes6,912 LPO optical modules

7. 2026 domestic AI chip ecosystem building​

7.1 Software ecosystem comparison​

VendorSoftware stackCUDA compatibilityFramework supportDeveloper community
Huawei AscendCANN + MindSporeCompatible (low migration cost)PyTorch/TensorFlow/MaxMind500k+
Baidu KunlunXPU-P + PaddlePaddleCompatible (low migration cost)PyTorch/TensorFlow/PaddlePaddle300k+
Alibaba T-HeadIn-house + Alibaba CloudCompatible (low migration cost)PyTorch/TensorFlow/Alibaba Cloud200k+
CambriconCANN + MindSporeCompatible (low migration cost)PyTorch/TensorFlow100k+
MetaXMXMACA + CUDACompatible (very low migration cost)PyTorch/TensorFlow/CUDA50k+
EnflameIn-house GCU stackIncompatible (rewrite needed)PyTorch/TensorFlow30k+
IluvatarIn-house HVMA stackIncompatible (rewrite needed)PyTorch/TensorFlow20k+
HygonDCU + x86x86-compatible (very low migration cost)PyTorch/TensorFlow/x8650k+

7.2 Developer community building​

VendorDevelopersDocsDev toolsTraining/cert
Huawei Ascend500k+CompleteCANN ToolkitHCCP cert
Baidu Kunlun300k+CompleteXPU-P ToolkitPaddlePaddle cert
Alibaba T-Head200k+CompleteAlibaba Cloud ToolkitAlibaba Cloud cert
Cambricon100k+Fairly completeCANN ToolkitCambricon cert
MetaX50k+Fairly completeMXMACA ToolkitMetaX cert
Enflame30k+AverageGCU ToolkitEnflame cert
Iluvatar20k+AverageHVMA ToolkitIluvatar cert
Hygon50k+CompleteDCU ToolkitHygon cert

7.3 Large-model adaptation capability​

VendorDeepSeek-V3LLama 3ChatGLMBaichuanERNIEQwen
Huawei Ascend✅ Day-0✅✅✅✅✅
Baidu Kunlun✅ Day-0✅✅✅✅✅
Alibaba T-Head✅ Day-0✅✅✅✅✅
Cambricon✅ Day-0✅✅✅✅✅
MetaX✅ Day-1✅✅✅✅✅
Enflame✅ Day-3✅✅✅✅✅
Iluvatar✅ Day-7✅✅✅✅✅
Hygon✅ Day-3✅✅✅✅✅

8.1 Market drivers​

DriverDescription
Policy supportThe national 15th Five-Year Plan incorporates the compute network as a major project, with stronger policy support
Supply chain securityEscalating US export controls make domestic chips the only option
Cost advantageDomestic chips are 30-50% cheaper than imports, clear cost-performance edge
Technology breakthroughsComprehensive breakthroughs in compute, memory, and energy efficiency
Maturing ecosystemSoftware ecosystems (CANN, XPU-P, MXMACA) reach 60-70% of CUDA maturity

8.2 Market challenges​

ChallengeDescription
Process7nm/5nm still lags NVIDIA's 4nm/3nm
HBM bandwidthDomestic HBM bandwidth still lags NVIDIA
Software ecosystemEcosystem maturity still lags CUDA
Capacity bottleneckLimited SMIC N+2/N+3 capacity, supply falls short of demand
International competitionNVIDIA, AMD, Google and others keep innovating

8.3 Market forecast (2026-2030)​

YearChina AI chip market (¥B)Domestic shareDomestic market (¥B)Notes
202650035%175Ascend 60%, Kunlun 20%
202770050%350960/970 launch, breakthroughs
20281,00065%650Domestic tech approaches international level
20291,50080%1,200Domestic tech surpasses international level
20302,00090%1,800Substitution essentially complete

9. Summary and outlook​

9.1 Core conclusions​

  1. 2026 marks the full-scale explosion of domestic AI chips, as the three giants Huawei Ascend, Baidu Kunlun, and Alibaba T-Head successively launch next-gen products
  2. Significant technology breakthroughs across compute, memory, energy efficiency, and system scaling
  3. Controllable supply chain security, fully autonomous from wafer fab to packaging and test
  4. Accelerating ecosystem building, software ecosystem maturity reaching 60-70% of CUDA
  5. Rising market share, domestic chips take 35% of China's AI chip market in 2026, projected 90% by 2030

9.2 Future outlook​

Short term (2026-2027):

  • Huawei Ascend 950PR/950DT mass deployment, clear 960/970 roadmap
  • Baidu Kunlun M100 inference chip ramps, M300 ultra-large multimodal training chip launches
  • Alibaba T-Head M890 3× performance, V900 launches
  • Domestic chip market share rises to 50%

Medium term (2028-2029):

  • Huawei Ascend 960/970 mass production, 5nm process, 8 PFLOPS FP4 compute
  • Baidu Kunlun M300 mass production, supports trillion-parameter multimodal training
  • Alibaba T-Head G900 launches, becoming the next-gen compute flagship
  • Domestic tech approaches international level, market share to 80%

Long term (2030+):

  • Domestic AI chips exceed 20% of the global market
  • Transition from "following" to "running alongside" to "leading"
  • Huawei Ascend, Baidu Kunlun, Alibaba T-Head among the global TOP 5
  • China becomes a global center of AI chip technology innovation

References​

  1. Domestic AI chip "three powers" rise: substitution trend shifts from policy-driven to market-driven — Sohu
  2. 2026 domestic AI chip panorama: Huawei Ascend races Cambricon — ZPEDU
  3. Huawei unveils three-year Ascend AI chip roadmap — Jiemian News
  4. Ascend 950PR chip — Baidu Baike
  5. Ascend 950 chip — Baidu Baike
  6. Kunlun P800: technical breakthroughs and application prospects of a new-generation AI accelerator — YunTECH
  7. Kunlun P800 latest specs: P800 single-precision compute reaches 345 TFLOPS — Xueqiu

Last updated: June 10, 2026

Kunlun P800 Deep Dive: Performance Data, Architectural Innovation, and SuperNode Deployment

· 10 min read
Industry Research Team

Kunlun P800 is Baidu's third-generation AI accelerator from Kunlunxin Technology, based on the in-house XPU-P architecture, with 345 TFLOPS peak FP16 compute (surpassing NVIDIA H20's 148 TFLOPS). Launched in March 2024, it has become an important force among domestic AI training/inference accelerators.

This article comprehensively analyzes this domestic AI chip's breakthroughs across five dimensions: performance data, architectural innovation, SuperNode deployment, large-model adaptation, and market positioning.


1. Core Performance Data​

1.1 Compute performance​

PrecisionComputeReference
FP16345 TFLOPS2.3× NVIDIA H20 (148 TFLOPS)
FP32Not disclosedEstimated ~170 TFLOPS
INT88-bit inference supportedSpecific TOPS not disclosed
Low-power mode128 TFLOPS @ 120WEnergy-efficiency-optimized scenarios
MoE optimizationNative MoE support4.3× sparse-model inference efficiency

Performance characteristics:

  • 345 TFLOPS at FP16, a new domestic AI chip compute benchmark
  • 2.3× compute over NVIDIA H20 (H20 only 148 TFLOPS)
  • Native MoE support, 4.3× sparse-model inference efficiency (with specific optimization)

1.2 Memory and bandwidth​

ItemParameter
HBM typeHBM3e (3D-stacked memory)
Memory capacity128 GB
Memory bandwidth1.5 TB/s
ECC protectionEnd-to-end ECC supported

Memory advantages:

  • 128GB capacity supports full-pipeline training of hundred-billion-parameter models
  • 1.5 TB/s is a high-end configuration among HBM3e solutions
  • 3D stacking alleviates large-model training memory bottlenecks

1.3 Power and energy efficiency​

ItemParameter
TDP400 W
Low-power mode128 TFLOPS @ 120W
Energy efficiency (FP16)~0.86 TFLOPS/W
vs. H100~57% of H100 power (400W vs 700W)

Energy efficiency characteristics:

  • At equal compute, significantly lower power than NVIDIA H100
  • Dynamic power adjustment, auto-switching performance modes by load
  • Suited to large-scale cluster deployment, reducing data center PUE pressure

1.4 Process and architecture​

ItemParameter
Process7nm
TransistorsOver 50 billion
ArchitectureIn-house XPU-P
Form factorOAM module
VirtualizationHardware vXPU, single card split into 32 virtual instances

Architectural innovation:

  • Heterogeneous compute architecture, decoupling matrix-multiply units from tensor cores
  • Parallel compute and data movement, theoretical compute 2.3× previous generation
  • Hardware virtualization, single physical card divided into multiple logical cards, raising utilization

2. Three Architectural Innovations​

2.1 Heterogeneous compute architecture optimization​

Technology innovations:

  • Matrix-multiply / tensor-core decoupling: parallelizes compute and data movement
  • Dynamic task scheduling: auto-allocates compute by load
  • Sparse compute optimization: native MoE support, 4.3× sparse-model inference efficiency

Performance gains:

  • Theoretical compute 2.3× previous generation (Kunlun 2nd gen)
  • 1.8× training throughput at equal power

2.2 3D-stacked memory technology​

Technology innovations:

  • HBM3e memory with 3D stacking
  • Single-card 128GB capacity, 1.5 TB/s bandwidth
  • End-to-end ECC for data reliability

Performance gains:

  • Alleviates large-model training memory bottleneck
  • Supports full-pipeline training of hundred-billion-parameter models (no model-parallel splitting)
  • 5× bandwidth vs GDDR6

2.3 Adaptive interconnect protocol​

Technology innovations:

  • Dynamic die-to-die topology adjustment
  • Built-in NPU for zero-copy data transfer, reducing CPU intervention
  • ML-based congestion control, 30% lower packet loss than traditional ECN

Performance gains:

  • In 256-node clusters, 40% lower communication latency
  • Inter-chip bandwidth 1.2 TB/s (Tianchi 256-node)
  • Smooth scaling to ten-thousand-card clusters

3. Tianchi SuperNode Deployment​

3.1 Tianchi 256-node​

System specs:

ItemConfiguration
P800 chips per node8
Inter-chip bandwidth1.2 TB/s (40% over previous gen)
Max model parameters500 billion
Typical power12 kW
InterconnectHardware RDMA acceleration + dynamic traffic scheduling

Core technology breakthroughs:

  1. Interconnect bandwidth engineering:

    • Built-in NPU for zero-copy data transfer, reducing CPU intervention
    • Dynamic traffic scheduling: auto-adjusts routes by real-time link quality
    • Predictive congestion control: ML-based congestion algorithm
  2. Virtualization resource utilization:

SplitActual perfTheoreticalUtilization
1 card100%100%100%
2 cards185%200%92.5%
4 cards340%400%85%

3.2 Tianchi 512-node​

System specs:

ItemConfiguration
P800 chips per node16
Inter-chip bandwidth2.4 TB/s
Max model parameters1.2 trillion
Typical power24 kW
Recovery speedTraining resumes within 5 min of node failure

Core technology breakthroughs:

  1. Ultra-large-scale training support:

    • Mixed-precision optimization: adds NF4 4-bit quantization on FP16/BF16, 75% less memory
    • Gradient checkpoint acceleration: reconstructs compute graph, activation storage O(n)→O(√n), 1.8× training speed
    • Failure recovery: distributed snapshot, 10× faster than traditional checkpoint
  2. Communication efficiency optimization:

    • 3D parallelism (data + model + pipeline), compute/communication ratio 12:1
    • In 1.75-trillion-parameter MoE training, communication overhead below 15%

3.3 Tianchi series performance comparison​

MetricTianchi 256Tianchi 512Improvement
Max model parameters500 billion1.2 trillion2.4×
Inter-chip bandwidth1.2 TB/s2.4 TB/s2×
Typical power12 kW24 kW2×
Recovery time<5 min<5 minFlat
Latency reduction40%50%10 pts

4. Large-Model Adaptation​

4.1 DeepSeek series adaptation​

Certification:

  • February 2025: passed DeepSeek-V3/R1 671B adaptation certification
  • Supports single-machine 8-card full DeepSeek-V3 671B
  • Supports DeepSeek MoE full-parameter training with just 32 machines

Performance data (DeepSeek-V3 671B):

MetricP800NVIDIA H100Ratio
Inference speed (tokens/s)12,50014,20088%
Training throughput (samples/s)8.510.283%
First-token latency (ms)9585112%
Memory usage (GB)11872164%

Conclusion:

  • P800 reaches 88% of H100 inference speed, gap significantly narrowed
  • 83% of H100 training throughput
  • 128GB large memory advantage clear, supports larger batch sizes

4.2 Other large-model adaptation​

ModelDeploymentNotes
ERNIE seriesBaidu Cloud nativeBaidu Smart Cloud main deployment
LLaMA seriesSupportedIncludes MoE-distilled versions
Qwen seriesSupportedAlibaba Cloud model adaptation
ChatGLM seriesSupportedZhipu AI model adaptation
Baichuan seriesSupportedBaichuan Intelligent model adaptation

CUDA compatibility:

  • Models runnable on CUDA migrate to P800 at low cost
  • Supports open-source inference frameworks such as vLLM
  • ~14% of CUDA low-level communication code needs rewriting (sparse-model inference needs specific optimization)

4.3 Ten-thousand-card cluster validation​

Cluster scale:

  • Fully in-house 30,000-card cluster deployed
  • Smooth scaling to ten-thousand-card clusters
  • Linear scaling efficiency 85%+ (thousand-card scale)

Stability data:

  • 30 days continuous training with no failures
  • Training resumes within 5 min of node failure
  • Cluster availability 99.9%

5. Performance Comparison Analysis​

5.1 vs. NVIDIA H20​

ItemKunlun P800NVIDIA H20Notes
FP16 compute345 TFLOPS148 TFLOPSP800 leads 2.3×
HBM capacity128 GB64 GBP800 +100%
HBM bandwidth1.5 TB/s4.0 TB/sH20 clear bandwidth lead
TDP400 W400 WFlat
Process7nm4nm (TSMC)H20 more advanced
Software ecosystemXPU-P (CUDA-compatible)CUDAH20 more mature
SupplyChina autonomousExport-controlledP800 no supply-chain risk

Conclusion:

  • In FP16 compute, P800 leads H20 2.3×
  • In memory capacity, P800 leads 100%
  • In HBM bandwidth, H20 leads 2.67×
  • In supply chain security, P800 wins outright

5.2 vs. NVIDIA H100​

ItemKunlun P800NVIDIA H100Notes
FP16 compute345 TFLOPS~1,300 TFLOPSH100 leads 3.77×
HBM capacity128 GB80 GBP800 +60%
HBM bandwidth1.5 TB/s3.35 TB/sH100 leads 2.23×
TDP400 W700 WP800 only 57% of H100 power
Process7nm4nm (TSMC)H100 more advanced
DeepSeek inference speed12,500 tokens/s14,200 tokens/sP800 reaches 88% of H100

Conclusion:

  • In raw compute, H100 leads P800 3.77×
  • In energy efficiency, P800 clearly outperforms H100 (0.86 vs 1.86 TFLOPS/W)
  • In actual inference performance, P800 reaches 88% of H100, gap significantly narrowed
  • In cost, P800 is ~50% of H100

5.3 vs. Ascend 910C​

ItemKunlun P800Ascend 910CNotes
FP16 compute345 TFLOPS800 TFLOPS910C leads 2.32×
HBM capacity128 GB128 GBFlat
HBM bandwidth1.5 TB/s784 GB/sP800 leads 91%
TDP400 W310 W910C lower power
Process7nm7nm (SMIC N+2)Same
Software ecosystemXPU-P (CUDA-compatible)CANN (CUDA-compatible)Each with strengths

Conclusion:

  • In FP16 compute, 910C leads P800 2.32×
  • In HBM bandwidth, P800 leads 910C 91%
  • In software ecosystem, both CUDA-compatible, similar migration cost
  • In scenarios, P800 suits inference, 910C suits training

6. Market Positioning and Competitive Advantages​

6.1 Target markets​

Core markets:

  1. Baidu Smart Cloud: core compute base of the Baige platform
  2. China Telecom/Mobile/Unicom: won AI inference server procurement bids
  3. Large-model startups: cost-sensitive, high compute demand
  4. Intelligent compute centers: ten-thousand-card clusters validated

Edge markets:

  1. Autonomous driving: end-to-end large-model training
  2. Smart finance: risk control, robo-advisory
  3. Smart healthcare: medical imaging, drug discovery

6.2 Competitive advantages​

AdvantageDescription
Compute leadershipFP16 345 TFLOPS, 2.3× over H20
Large memory128GB HBM3e, full-pipeline training of hundred-billion-parameter models
High energy efficiency400W TDP delivers 345 TFLOPS, better than H100
System scalingTianchi 256/512 SuperNodes, ten-thousand-card clusters
Software ecosystemXPU-P CUDA-compatible, low migration cost
Cost advantage~50% of H100, clear cost-performance edge
Supply chain securityChina autonomous, no export-control risk

6.3 Weaknesses and improvement directions​

WeaknessImprovement direction
Single-chip computeNext-gen M300 to adopt 5nm, target doubling
HBM bandwidthM300 to adopt HBM4, bandwidth to 3.2 TB/s
Software ecosystemContinued XPU-P + PaddlePaddle investment
ProcessDeep cooperation with SMIC to ramp N+2 (7nm-class)

7. 2026 Shipment Plan and Market Forecast​

7.1 Shipment plan​

PeriodShipmentsCumulativeKey customers
2024 Q1-Q450k50kBaidu Smart Cloud
2025 Q1-Q4150k200kChina Mobile, China Telecom
2026 Q1-Q2100k300kChina Unicom, iFlytek
2026 Q3-Q4100k400kGovernment projects, large-model startups
2027500k900kGlobal market (Southeast Asia, Middle East, Latin America)

Capacity bottleneck:

  • Constrained by wafer fab capacity, supply falls short of demand
  • 2026 plan of 200k chips, actual capacity ~150k
  • Kunlunxin deepening cooperation with SMIC and Hua Hong to raise capacity

7.2 Market forecast​

China AI chip market (2026):

  • Total: ~¥50B
  • Domestic share: ~35% (¥17.5B)
  • Kunlun P800 share: ~20% (¥3.5B, ~200k chips)

Global AI chip market (2026):

  • Total: ~$200B
  • Kunlun share: ~1% ($2B)
  • Growth drivers: China-market localization + Belt and Road exports

8. Summary and Outlook​

8.1 Core conclusions​

  1. Kunlun P800 is a major domestic AI chip breakthrough, leading comprehensively in FP16 compute, memory capacity, and energy efficiency
  2. Tianchi 256/512 SuperNodes prove domestic chips can replace imported ones
  3. DeepSeek-V3 671B adaptation success validates P800 maturity in large-model training/inference
  4. 200k chips shipped in 2026, projected 20% of China's AI chip market

8.2 Future outlook​

Short term (2026-2027):

  • P800 continues ramping, shipments exceed 500k
  • Tianchi 512-node deployments over 100 units
  • Software ecosystem (XPU-P + PaddlePaddle) maturity approaches 60% of CUDA

Medium term (2028-2029):

  • Next-gen M300 mass production, 5nm process, target 700 TFLOPS FP16
  • M100 (inference-specific) becomes inference-market mainstay, share over 15%
  • Supports trillion-parameter model full-pipeline training

Long term (2030+):

  • Kunlun series becomes TOP 5 of the global AI chip market
  • Domestic AI chips exceed 15% of the global market
  • Transition from "following" to "running alongside"

References​

  1. Kunlun P800 parameters — CSDN Library
  2. Kunlun P800: technical breakthroughs and application prospects of a new-generation AI accelerator — YunTECH
  3. Kunlun P800 latest specs: P800 single-precision compute reaches 345 TFLOPS — Xueqiu
  4. Exclusive: Kunlun — domestic AI card full DeepSeek training/inference adaptation — Kunlunxin official
  5. Kunlun P800 detailed specs — MirrorFrog: https://www.mirrorfrog.com/en/docs/cards/others/kunlun-p800

Last updated: June 10, 2026