12 posts tagged with "Google"

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.

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Key Takeaways​

• Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
• AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
• Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
• Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
• NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

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1. Qualcomm: Mobile Giant Moves Into Datacenter AI​

AI 100 → AI 200 → AI 250​

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

Model	Launch	Availability	Key Features
AI 100	2025-10	2026 H2	Rack-scale AI inference, 768GB LPDDR per card
AI 250	2025-10	2027 H1	Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed​

1. Low TCO: LPDDR memory is far cheaper than HBM
2. Energy efficiency: Mobile chip design heritage, excellent power control
3. Inference-focused: Not chasing training performance, focused on inference scenarios
4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact​

• Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
• Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
• Diversifies choice: Breaks NVIDIA's monopoly in the inference market

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2. AMD MI400 Series: Three Models, Precise Positioning​

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)​

Feature	Spec
Positioning	HPC + sovereign AI
FP32/FP64	Supported (key differentiator)
Use cases	Scientific computing, climate simulation, national AI infrastructure
Competitor	NVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)​

Feature	Spec
Positioning	Enterprise 8-GPU servers
Compatibility	Works with existing datacenter infrastructure
Use cases	Enterprise AI, private cloud, edge inference
Advantage	Cheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)​

Feature	Spec
Positioning	Flagship AI training + inference
Optimized precision	FP4/FP8/BF16
Helios rack	Core component
Competitor	NVIDIA Rubin R200

Helios Rack-Scale Solution​

AMD also launched the Helios rack-scale AI solution at CES 2026:

• 18 Zen 6 CPUs (2nm process)
• 72 MI455X GPUs
• Direct liquid cooling
• Shipment expected in 2026 H2

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3. Huawei Three-Generation Roadmap: 950 → 960 → 970​

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)​

Model	Launch	Key Features
950PR	2026-Q1	PR (inference-optimized), already in mass production
950DT	2026-Q4	DT (Decode + training), expected to scale up

Technical highlights:

• Added FP8/MXFP8/MXFP4 support
• Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)​

• Doubled compute: All specs double versus the 950 series
• FP8: ~2 PFLOPS expected
• Process: N+3 (equivalent to 5nm)
• Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)​

• Third-generation flagship: Only timeline announced, specs TBD
• Significance: Huawei's first complete generation-spanning roadmap
• Signal: China's domestic AI chips have entered a "roadmap-driven" phase

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4. Intel Jaguar Shores: Timeline Uncertain​

Original Plan​

• Launch: 2026
• Architecture: Xe-HPC + Gaudi fusion
• Process: 18A (Intel's most advanced)
• Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments​

• Possible delay: Some sources suggest a slip to 2027
• Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
• Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap​

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.

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5. NVIDIA Rubin Platform: Full Mass Production​

Rubin R200 (2026-Q2 full mass production)​

Feature	Spec
HBM	288GB HBM4
Compute	50 PFLOPS FP4
NVLink	NVLink 6 (1800 GB/s)
Process	TSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)​

• 72 Rubin GPUs
• 36 Vera CPUs
• 1.8 EFLOPS FP4
• Direct liquid cooling

Vera CPU (Debut)​

• Architecture: Custom CPU replacing Grace
• Positioning: Deep co-design with Rubin GPU
• Significance: NVIDIA's transformation from a GPU company into a computing platform company

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6. Google TPU v8: Training/Inference Officially Split​

TPU 8t (training) + TPU 8i (inference)​

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

Feature	TPU 8t (training)	TPU 8i (inference)
Optimization	High compute, high bandwidth	Low latency, low cost
Interconnect	Optical interconnect	Ethernet
Launch	2027	2027

Significance​

• Industry trend: Specialization of training/inference chips
• Followers: Qualcomm AI 200 is also inference-only
• NVIDIA pressure: Does it need an inference-specific chip?

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7. Cerebras WSE-4: Wafer-Scale Engine Evolves​

Core Specs​

Feature	Spec
Transistors	1.4 trillion
Compute	125 PFLOPS FP8
Launch	2026 H2
Process	TSMC 5nm

Competitive Advantages​

• Massive model training: A single WSE-4 can train 10T+ parameter models
• Low-latency inference: Entire model on one chip, no communication overhead
• Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

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8. Market Landscape Analysis​

Training Market​

Rank	Vendor	Product	Market Share (est.)
1	NVIDIA	Rubin R200	70%
2	AMD	MI455X	15%
3	Google	TPU v8t	10%
4	Huawei	Ascend 960	5% (mostly China)

Inference Market (New Battlefield)​

Rank	Vendor	Product	Advantage
1	NVIDIA	H200 / Rubin CPX	Mature ecosystem
2	Qualcomm	AI 200	Low TCO
3	AMD	MI440X	Good compatibility
4	Intel	Gaudi 4	Low price

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9. Key Trends​

Trend 1: Rise of Inference-Specific Chips​

• Qualcomm AI 200: Mobile giant enters the market
• NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
• Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard​

• NVIDIA NVL72: 72 GPU + 36 CPU
• AMD Helios: 18 CPU + 72 GPU
• Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase​

• Huawei three-generation roadmap: 950 → 960 → 970
• Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
• Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck​

• SK hynix: HBM4 capacity already booked by NVIDIA
• Samsung: HBM4E samples delivered to AMD
• Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

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10. Procurement Recommendations​

If Procuring in 2026 H2​

1. Training scenarios:

   • First choice: NVIDIA Rubin R200 (best performance)
   • Alternative: AMD MI455X (better price/performance)
   • Domestic: Huawei Ascend 950DT (China-based customers)

2. Inference scenarios:

   • First choice: NVIDIA H200 (mature ecosystem)
   • Best value: Qualcomm AI 200 (if available)
   • Cost-sensitive: AMD MI440X

3. HPC scenarios:

   • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027​

• Wait for Rubin Ultra: Performance possibly 2x R200
• Watch MI500: AMD's next-generation product
• Evaluate TPU v8: If already on Google Cloud

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Conclusion​

2026 H2 will be the most fiercely contested half-year in AI chip market history:

• NVIDIA continues to lead, but its advantage is narrowing
• AMD precisely positions three models; market share will keep rising
• Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
• Huawei has a clear three-generation roadmap; domestic substitution accelerates
• Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.

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References​

• AI Compute Card Future Roadmap - MirrorFrog real-time updates
• NVIDIA Rubin R200 deep dive (see related articles on this site)
• AMD MI400 series CES 2026 launch (see related articles on this site)
• Qualcomm AI 100 launch analysis (coming soon)

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Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement

On April 22, 2026, at Google Cloud Next '26 in Las Vegas, Google officially launched its 8th-generation Tensor Processing Unit (TPU). For the first time in Google's history, it split AI training and inference onto two independent chips:

• TPU 8t: designed for model training
• TPU 8i: focused on high-concurrency inference

This launch introduces no new physical concept, but focuses on solving the core pain points of AI data centers: ten-thousand-card cluster scaling efficiency, Agentic AI workload optimization, and performance per watt.

TPU 8i (inference-specific): eliminating the "waiting room effect"​

TPU 8i is the first inference-specific chip co-designed by Google and MediaTek, aimed at eliminating the "waiting room effect" — where user requests are intentionally queued or delayed to maximize hardware utilization.

TPU 8i core specs (estimated)​

Parameter	TPU 8i	TPU v7 Ironwood
Positioning	Inference-specific	Mostly inference
Process	TSMC 2nm	—
Die design	Dual compute die (est.)	—
Memory	8× HBM3e 12-layer (~192GB est.)	8× HBM3 (192GB)
Memory bandwidth	~7 TB/s (est.)	7,380 GB/s
FP8 compute	~4,614 TFLOPS (est.)	4,614 TFLOPS
TDP (per chip)	1,300 W	1,000 W
Interconnect	ICI 3D Torus	ICI 3D Torus
Integrated CPU	Arm Axion (64 cores)	None
Cooling	Air or liquid	4th-gen liquid
Announced	2026-04-22	2025-08-25
Mass production	End of 2027	2026

Key features:

• ✅ High-concurrency inference optimization: built for Agentic AI, supports inference chains of thousands of steps
• ✅ Arm Axion CPU integration: 64-core Neoverse V2, host CPU + data preprocessing synergy
• ✅ Low latency: eliminates the "waiting room effect", extremely low TTFT (time to first token)
• ✅ 117% better performance per watt: vs Ironwood (at equal price)

TPU 8t (training-specific): the "engine" of Gemini 3/4​

TPU 8t is designed for training Google's frontier models like Gemini 3 / Gemini 4, continuing Google's long-term partnership with Broadcom.

TPU 8t core specs​

Parameter	TPU 8t	TPU v7 Ironwood	Improvement
Positioning	Training-specific	Mostly inference	Form-factor split
Process	TSMC 2nm	—	New gen
Die design	Dual compute die	—	Architecture upgrade
Memory	8× HBM3e 12-layer (~256GB per chip est.)	8× HBM3 (192GB)	Upgrade
Memory bandwidth	~7 TB/s (per chip est.)	7,380 GB/s	Flat
Pod chip count	9,600 chips	9,216	+4%
Pod total HBM	2 PB	—	Far exceeds
Pod FP4 compute	121 EFLOPS	~42 EFLOPS (est.)	~3×
Integrated CPU	Arm Axion (64 cores)	None	New
TDP (per chip)	1,300 W	1,000 W	+30%
Mass production	End of 2027	2026	—

Key features:

• ✅ Native MoE training support: Expert-Parallel optimization (DeepSeek / Mixtral style)
• ✅ Long-context training: 1M+ token context training optimization
• ✅ RLHF / post-training: native Online RL (DPO/PPO/GRPO) optimization
• ✅ Arm Axion CPU synergy: data preprocessing / weight init offloaded to CPU
• ✅ SparseCore acceleration: MoE routing and recommendation systems

Strategic significance of the 8th-generation TPU​

1. Training and inference split for the first time​

Previously, Google's TPU design philosophy was "one architecture for both training and inference" (e.g., TPU v5p, v6e). But the arrival of the Agentic AI era changed that:

• Training workloads: large-scale matrix multiply, long-sequence backpropagation, sparse MoE
• Inference workloads: high concurrency, low latency, KV Cache-intensive, dynamic batching

These two workloads impose very different demands on chip architecture. After the split:

• TPU 8t can focus on optimizing compute density and memory capacity
• TPU 8i can focus on optimizing inference throughput and performance per watt

2. Dual-track partnership with Broadcom and MediaTek​

• Broadcom: continues designing TPU 8t (training), extending the long-term partnership since TPU v1
• MediaTek: first-time collaboration designing TPU 8i (inference), bringing mobile-chip low-power design expertise

This "dual-track" strategy lets Google:

• Pursue peak performance on training chips (combined with Broadcom's high-end ASIC experience)
• Pursue peak energy efficiency on inference chips (combined with MediaTek's mobile-chip experience)

3. Versus NVIDIA Vera Rubin​

Comparison	Google TPU 8t + 8i	NVIDIA Vera Rubin
Strategy	Training/inference split	Unified architecture (GPU+CPU)
Process	TSMC 2nm	TSMC 3nm (est.)
Ecosystem	Google Cloud only	Globally available
Software	JAX / PyTorch-XLA	CUDA / PyTorch
Mass production	End of 2027	Fall 2026
Strength	Deep Gemini integration	Most mature ecosystem

Deep technical analysis​

TSMC 2nm: why 2nm?​

Google is the first vendor to adopt TSMC 2nm on an AI accelerator (NVIDIA Rubin uses 3nm). 2nm (N2) vs 3nm (N3E):

• Transistor density: ~15-20% higher
• Power reduction: ~25-30% (at equal performance)
• Performance gain: ~10-15% (at equal power)

For TPU 8t/8i, which already hit 1,300W, 2nm is mandatory — otherwise 4nm/3nm couldn't integrate dual compute dies and 8× HBM3e within reasonable power.

Arm Axion CPU: Google's in-house CPU enters the TPU node for the first time​

Previously, TPU nodes used Intel Xeon or AMD EPYC as host CPUs. TPU 8t/8i integrate Google's in-house Arm Axion CPU (64-core Neoverse V2) for the first time:

Significance:

1. Data preprocessing offload: tokenization, data augmentation can run entirely on Axion, freeing TPU compute
2. Weight initialization: large-model training weight init on CPU, accelerating training startup
3. Inference scheduling: Axion handles request scheduling and load balancing for multi-model inference

This marks the TPU node's evolution toward a "SuperNode": no longer a pure accelerator, but a TPU + Axion CPU co-design system, comparable to NVIDIA's Vera CPU.

4th-gen liquid cooling: the 1,300W thermal challenge​

TPU 8t/8i TDP reaches 1,300W (30% over Ironwood's 1,000W), posing a huge data-center cooling challenge.

Google adopts a 4th-gen liquid cooling solution:

• Cold-plate liquid cooling: directly cools GPU die and HBM
• Immersion cooling: optional (ultra-high-density deployment)
• Smart thermal control: dynamically adjusts pump speed and fan RPM by workload

Production timeline and use cases​

Time	Event
2026-04-22	Cloud Next '26 official announcement
H2 2026	Internal testing (Google DeepMind first)
End of 2027	Mass production, Google Cloud availability
2028	Next-gen TPU (possibly TPU 9)

Target use cases:

• ✅ Frontier model training (Gemini 3/4, external customers)
• ✅ MoE large-model inference (high concurrency, low latency)
• ✅ Multimodal AI (ViT + LLM simultaneous inference)
• ✅ Agentic AI (Agentic AI workloads)

Competitive comparison​

Vendor	Product	Process	TDP	Mass production
Google	TPU 8i (inference)	TSMC 2nm	1,300W	End of 2027
Google	TPU 8t (training)	TSMC 2nm	1,300W	End of 2027
NVIDIA	Rubin GPU	TSMC 3nm (est.)	~1,000W	Fall 2026
NVIDIA	Vera CPU	TSMC 3nm (est.)	~500W	Fall 2026
AMD	MI455X (MI400)	TSMC 3nm (est.)	~700W	2026
Huawei	Ascend 950PR	—	~500W	Q1 2026

Industry impact​

1. AI chips enter the 2nm era: Google leads with TSMC 2nm; NVIDIA and AMD will follow
2. Training/inference split becomes a new trend: other vendors (NVIDIA, AMD) may follow suit
3. In-house CPUs become standard: Google (Axion), NVIDIA (Vera), Huawei (Kunpeng) all do CPU+accelerator co-design
4. Liquid cooling becomes inevitable: 1,300W TDP means air cooling can no longer suffice

Related chips​

• Google TPU 8i - inference-specific TPU detailed specs
• Google TPU 8t - training-specific TPU detailed specs
• Google TPU v7 Ironwood - previous-gen inference TPU
• NVIDIA Rubin R200 - same-generation competitor
• NVIDIA Vera CPU - counterpart to Google Axion

References​

• Google blog: Introducing new TPUs at Cloud Next '26
• Google Cloud Next '26 keynote replay
• Tencent News: Google 8th-gen TPU deep dive

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This article is compiled from Google's official announcements and public sources; some specs are estimates, subject to final official release.