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HBM4 high bandwidth memory

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HBM4 Mass-Production Year One: Samsung Yield Breaks 80%, Three Giants Pass NVIDIA Certification, the Last Bottleneck of AI Compute Supply

· 6 min read
Industry Research Team

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.


1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

TimelineSamsung HBM4 YieldNotes
Feb 2026 (mass production start)Under 60%Line ramp-up period
Early Aug 2026~80%Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.


2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor2026 Rubin HBM4 Allocation (est.)Notes
SK Hynix60%–70%Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung25%–30%Rapid share gains after yield leap
MicronRemainderLimited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.


3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

  • Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
  • HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
  • Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

SpecHBM4 (12-Hi / 16-Hi)HBM4E
Per-stack capacity36 GB / 48 GB—
Pin rate11.7–13.0 Gbps16 Gbps
Per-stack bandwidthup to 3.3 TB/sup to 3.6 TB/s
Bus width2048-bit—
Energy efficiency+40% vs HBM3E—
Thermal resistance / cooling+10% improvement / +30%—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.


5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

  • 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
  • The industry already anticipates significant price increases;
  • For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.


6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

References​


This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

AMD Advancing AI 2026 Opens Tomorrow: Three CDNA5 MI400 Models, Helios Rack Hits 3 exaFLOPS, OpenAI + Meta Lock 12GW Deal

· 4 min read
AI Hardware Analyst

AMD has confirmed its flagship AI event Advancing AI 2026 will be held July 22-23, 2026 at the Moscone Center in San Francisco, with the keynote on July 23 hosted by Chair and CEO Lisa Su. The event will complete the Instinct MI400 series availability timeline, pricing, and independent benchmark data.

1. Instinct MI400 family: three CDNA 5 accelerators​

AMD fully revealed the MI400 matrix at CES 2026; all three accelerators use CDNA 5 architecture, TSMC 2nm process, differentiated by precision and scenario:

ModelPositioningKey specs
MI455X (flagship)Large-scale train/inference (rack-scale)320B transistors, 12 chiplets, 432 GB HBM4 (12×36GB), 19.6 TB/s, FP4 40 PFLOPS / FP8 20 PFLOPS
MI440X (enterprise)Local enterprise AI (8-card node)Low-precision AI (FP4/FP8/BF16), direct MI300/MI350 replacement, compatible with existing power/cooling
MI430X (HPC/sovereign AI)High-precision scientific computing + AIFull FP32/FP64, already deployed at Oak Ridge Discovery and France's first exascale Alice Recoque

MI455X and MI440X target low-precision AI (FP4/FP8/BF16); MI430X fills traditional HPC high-precision needs — improving energy efficiency and cost-performance by "trimming execution units by precision." All three support UALink (among the first accelerators compatible with the standard) and Infinity Fabric die-to-die interconnect; rack scaling uses Ultra Ethernet.

Lisa Su confirmed on the Q1 2026 earnings call: MI455X samples have been sent to core customers, with demand "exceeding the company's internal expectations for 2027."

2. Helios rack: 3 exaFLOPS per cabinet​

AMD enters the hyperscale market with the Helios rack-scale platform:

MetricHelios rack
Accelerators72 × MI455X
Aggregate HBM431 TB
Total memory bandwidth1.4 PB/s
Per-cabinet computeUp to 3 AI exaFLOPS (Q3 delivery target)
Target customersHyperscale train/inference clusters

Helios uses AMD's in-house Zen 6 EPYC Venice CPU (18 per rack) + Pensando Vulcano 800G NIC, integrated via the open ROCm software stack; AMD also plans a double-width 128-card Helios variant, pushing per-cabinet compute to the 3 AI exaFLOPS ceiling. Further out, the MI500 series (CDNA 6, 2nm, HBM4E) is planned for 2027, with official claims of up to 1000× AI performance vs MI300X.

3. 12GW deal: OpenAI + Meta dual endorsement​

AMD holds two historic-scale compute agreements totaling about 12 GW, with lifetime potential revenue possibly reaching $100B:

CustomerScaleFirst deploymentStructure
OpenAI6 GW (multi-gen products)First 1 GW, H2 2026 on MI450"compute-for-upside": up to 160M warrants, vesting by milestone and stock-price targets
Meta6 GWCustom MI450 chips, from H2 2026Deployed in next-gen data centers

Financial expectations​

Metric2026 forecast
MI400 series revenue~$7.2B (about 25% of data-center sales)
Data-center GPU revenue~$15B (up +114% YoY)
Total data-center revenuePossibly $28.7B (up +73% YoY)

⚠️ Execution risk: AMD has flagged that MI450's Q3 mass production will weigh on gross margin (new products below company average); advanced process and advanced packaging (TSMC CoWoS) capacity remain the main constraint.

Industry interpretation​

  1. CUDA moat being pried open: when companies building the world's largest training clusters — Meta, OpenAI — bet on AMD silicon, AMD's long-standing 5-7% GPU share ceiling is being broken.
  2. Memory advantage as differentiation: 432 GB HBM4 / 19.6 TB/s vs NVIDIA Rubin's 288 GB offers capacity advantage, critical for large-model inference (KV Cache-constrained scenarios).
  3. Tight benchmarking pace: MI450 and NVIDIA Vera Rubin both ramp in H2 2026, with the two giants competing head-on over HBM4 supply and CoWoS capacity.

References​


This article was written on the eve of Advancing AI 2026 (July 22-23, opening tomorrow); the keynote is July 23 hosted by Lisa Su, where MI400's final availability, pricing, and independent benchmarks will be revealed — we will update in sync.

NVIDIA Vera Rubin Officially Ships: First VR200 NVL72 Delivered, Samsung HBM4 Mass Production, Rubin Ultra Cabinet Sky-High Price

· 5 min read
Industry Research Team

July 2026, NVIDIA's next-gen AI compute platform Vera Rubin officially began its first shipments, succeeding the Blackwell architecture, with large-scale mass production planned for H2 2026. First customers include Microsoft, Google, Amazon, Meta, Oracle, and other large cloud providers.

1. World's First VR200 NVL72 Delivered (Milestone)​

CoreWeave jointly with Dell announced that the world's first NVIDIA Vera Rubin VR200 NVL72 cabinet has been officially delivered and passed the L11 full-cabinet hardware diagnostics on the first try. This marks Rubin's move from roadmap to physical product, with no major bottlenecks in core supply-chain links (HBM4, advanced packaging, liquid cooling, ultra-high-power power supply).

VR200 NVL72 Core Configuration​

MetricVera Rubin VR200 NVL72
Cabinet codenameOberon
GPU72 Rubin GPUs
CPU36 Vera CPUs
Per-GPU memory288 GB HBM4
Per-CPU memory1.5 TB LPDDR5X
Total cabinet HBM420.7 TB (20,736 GB)
Total cabinet LPDDR5X54 TB
InterconnectNVLink 6 full mesh
Inference performance~3.6 exaFLOPS class
CoolingLiquid cooling
Generational improvement~3.5× per-GPU compute, ~2.8× memory bandwidth (vs Blackwell)

Vera CPU integrates 88 custom Olympus ARM cores, with 1.8 TB/s interconnect to the GPU, usable as a GPU memory expansion pool. NVIDIA completed its first Vera CPU deliveries to Anthropic, OpenAI, xAI, and Oracle Cloud in May.

2. Samsung HBM4 Mass Production: Key Bottleneck Eases​

July 8, 2026, Samsung Electronics officially started HBM4 mass production for the Vera Rubin platform, with reported HBM4 mass-production yield reaching 70% (above the initial 60-65% expectation). Confirmation of this key supply-chain link clears obstacles for Rubin's large-scale deployment.

HBM Supply Landscape (2026 Q1)Share
SK hynix45%
Samsung40%
Micron15%

HBM4 uses 8-layer stacking (12-layer design planned for 2028), priced at about 2.8× HBM3e. TrendForce predicts HBM supply will grow 65% annually, with HBM4 reaching 35% of total output by 2027 Q4.

3. Rubin Ultra Sky-High Price: HBM Cost Dominates​

Per BofA Global Research estimates, the Rubin generation will push single-server cost to a new high:

Cost ItemRubin VR200 (Oberon)Comparison
Cabinet HBM4 usage20,736 GB—
HBM4 unit price~$18.40 / GBBlackwell (HBM3e) ~$11.26 / GB
HBM4 cost alone~$382KExcluding LPDDR5X
Rubin Ultra cabinet estimated price~$21MITHome / BofA estimate

4. Rubin Ultra Design Change: Original 4-die Cancelled (per SemiAnalysis)​

Semiconductor research firm SemiAnalysis (2026-06-30) disclosed that the original 4-die Rubin Ultra GPU unveiled at GTC 2026 has been cancelled; the version actually shipping in 2027 is roughly halved in scale and performance:

  • Reason for cancellation: The original integrated 4 compute dies + 16 HBM4E in a single CoWoS-L package; the substrate warped under the 4-die config, causing compute-die-to-substrate contact failure and yield collapse; the alternative CoPoS won't reach mass production until after late 2028, missing the 2027 node.
  • New approach: Changed to dual-die (same construction as standard Rubin) + HBM4E, ~384 GB HBM4E per GPU (higher than standard Rubin's 288 GB), but total compute and bandwidth only half the original; to approach the original's aggregate compute, NVIDIA plans to assemble "2+2" board-level configs within the Kyber rack to reach four-die equivalent scale.
  • Kyber rack delay: The companion Kyber NVL144 rack is delayed 12+ months to 2028 due to midplane PCB manufacturing difficulties; the 800V DC power scheme is likewise delayed to 2028.

⚠️ Note: NVIDIA has not commented officially on the above design change; some on X argue "the chip count hasn't changed, it's old news reheated." This section is compiled from SemiAnalysis public reports, subject to final NVIDIA disclosure. We have marked "specs pending official confirmation" on the Rubin Ultra preview card.

Industry Interpretation​

  1. "Never doubt" moment realized: Rubin's first delivery passed L11 on the first try, dispelling market doubts about "Rubin delay," locking in H2 2026 AI compute supply certainty ahead of time.
  2. Designed for Agentic AI: Rubin targets agentic workflows and ultra-long-context inference, further lowering the training/inference cost curve for trillion-parameter models.
  3. HBM is the full-chain winner: 20.7 TB HBM4 per cabinet is enormous usage; SK hynix, Samsung, Micron, advanced packaging (CoWoS-L), liquid cooling, and power retrofitting all benefit across the chain, while also becoming the biggest cost and capacity constraint.

References​


This article continuously tracks Vera Rubin mass-production ramp and HBM4 supply-chain dynamics.

AMD MI455X Stuns at CES 2026: AI Chip Performance Up 1000x in 4 Years

· 6 min read
Industry Research Team

On January 5, 2026, on the opening day of CES 2026 (Consumer Electronics Show), AMD Chair and CEO Dr. Lisa Su unveiled in her keynote: the Instinct MI400 series AI accelerators.

The most eye-catching is MI455X — AMD's most powerful AI accelerator ever, using a 2nm + 3nm hybrid process, 432GB HBM4, with FP4 compute up to 40 PFLOPS (20 PFLOPS FP8).

Key highlights​

  • MI455X: FP4 40 PFLOPS, FP8 20 PFLOPS, 10× over MI355X
  • MI450: cost-performance version, FP4 28 PFLOPS, 288GB HBM4
  • Process upgrade: world's first AI chip with 2nm + 3nm hybrid process (GCD on 2nm, MCD on 3nm)
  • Memory upgrade: from MI350X's 288GB HBM3e to 432GB HBM4 (MI455X)
  • Bandwidth upgrade: from MI350X's 8 TB/s to 19.6 TB/s (2.45×)
  • Architecture upgrade: from CDNA 4 to CDNA 5
  • Mass production: MI455X Q4 2026, MI450 Q3 2026

Full MI400 series specs​

📌 Important correction (2026-06-16): After official spec verification, MI455X memory is 432GB HBM4 (not the earlier reported 288GB), and FP4 compute is 40 PFLOPS. Corrected herein.

ModelPositioningMemoryFP4 computeFP8 computeTDP (est.)
MI455XFlagship training+inference432GB HBM440 PFLOPS20 PFLOPS~1,000W
MI450Cost-performance training288GB HBM428 PFLOPS14 PFLOPS~800W
MI440XEnterprise inference216GB HBM425 PFLOPS12.5 PFLOPS~600W
MI430XHPC / scientific computing192GB HBM420 PFLOPS10 PFLOPS~500W
MI400XGeneral / edge inference128GB HBM412 PFLOPS6 PFLOPS~400W

Key upgrades (vs MI350 series):

  • Memory: HBM3e → HBM4, capacity +50% (432GB vs 288GB)
  • Bandwidth: 19.6 TB/s (vs MI350's 8 TB/s, +2.45×)
  • Compute: FP4 40 PFLOPS (vs MI355X's 20 PFLOPS, +2×)
  • Process: 2nm + 3nm hybrid (GCD on 2nm, MCD on 3nm)
  • Architecture: CDNA 5 (vs MI350's CDNA 4)

Performance vs. MI355X​

MetricMI355X (2025)MI455X (2026)Improvement
FP4 compute20 PFLOPS40 PFLOPS2×
FP8 compute10 PFLOPS20 PFLOPS2×
Memory capacity288GB HBM3e432GB HBM41.5×
Memory bandwidth8 TB/s19.6 TB/s2.45×
ProcessTSMC 3nm2nm + 3nm hybridNew gen
ArchitectureCDNA 4CDNA 5New gen
TDP800-1000W~1,000WFlat

Lisa Su at CES 2026:

"Four years ago, MI250's AI performance was X. Today, MI455X's performance is 1000× that. That's the pace of AI chip progress."

CDNA 5 architecture in detail​

The MI400 series adopts the CDNA 5 architecture (MI355X uses CDNA 4):

Key upgrades​

  1. Matrix Core upgrade: FP8/INT8/FP16 support, sparsity acceleration
  2. HBM4 controller: 12-layer HBM4 (vs HBM3e's 8 layers)
  3. Infinity Fabric 4.0: 50% higher die-to-die / die-to-GPU bandwidth
  4. Native sparsity support: MoE Expert-Parallel optimization
  5. Long-context optimization: 1M+ token KV Cache acceleration

vs. NVIDIA Blackwell / Rubin​

MetricAMD MI455XNVIDIA B200NVIDIA Rubin R200 (2026 Q4)
FP4 compute40 PFLOPS20 PFLOPS (45 sparse)~40 PFLOPS (est.)
FP8 compute20 PFLOPS10 PFLOPS (22.5 sparse)~20 PFLOPS (est.)
Memory432GB HBM4192GB HBM3e288GB HBM4
Memory bandwidth19.6 TB/s8 TB/s13 TB/s
TDP~1,000W700-1000W~1,000W
Process2nm + 3nm hybridTSMC 4npTSMC 3nm
Mass production2026 Q42024 Q42026 Q4
Software ecosystemROCmCUDACUDA
StrengthMemory capacity, open ecosystemMost mature ecosystemNext-gen architecture
WeaknessSoftware ecosystem gapSmaller memoryNot yet launched

Conclusion: MI455X leads B200 in FP4/FP8 compute and memory capacity/bandwidth, but software ecosystem remains a weak point. Versus Rubin R200, paper specs are close, but Rubin has the CUDA ecosystem moat.

Production timeline​

TimeEvent
June 12, 2025MI400 series specs first announced at Advancing AI
January 5, 2026MI455X/MI450/MI440X formally launched at CES 2026
2026 Q3MI450 sampling begins
2026 Q4MI455X mass production
2026 Q4MI440X (enterprise inference) launched
2027 Q1MI430X/MI400X (HPC/edge inference) launched
2027MI500 series (next gen)

AMD AI chip roadmap (2025-2027)​

TimeProductProcessNotes
Q4 2024MI325XTSMC 5nmHBM3e upgraded
Q3 2025MI355X (MI350 series)TSMC 3nmCDNA 4, 288GB HBM3e
Q4 2026MI455X (MI400 series)2nm + 3nm hybridCDNA 5, 432GB HBM4
Q1 2027MI500 seriesTSMC 2nm (est.)Next gen, further gains

Software ecosystem: ROCm's progress and challenges​

✅ Progress​

  • PyTorch 2.5+: native MI300X/MI455X support
  • Hugging Face Transformers: official AMD GPU support
  • vLLM 0.8+: MI300X inference support (experimental)
  • JAX: AMD adapting (vs Google TPU)

⚠️ Challenges​

  • Framework optimization: PyTorch on AMD GPUs still below NVIDIA
  • Operator coverage: some niche operators need hand-written HIP
  • Multi-card communication: RCCL (vs NCCL) still lags
  • Developer ecosystem: tutorials, cases, community activity far below NVIDIA

Competitive comparison​

VendorProductFP4 computeMemoryMass productionStrengthWeakness
AMDMI455X40 PFLOPS432GB HBM42026 Q4Largest memory, open ecosystemSoftware gap
NVIDIAB20020 PFLOPS192GB HBM3e2024 Q4Most mature ecosystemSmaller memory
NVIDIARubin R200~40 PFLOPS288GB HBM42026 Q4Next-gen architecture, CUDAExpensive
HuaweiAscend 910C~1.6 PFLOPS64GB HBM2026 Q2China-localizedExport-controlled
GoogleTPU 8t~9.2 PFLOPS~256GB HBM3eLate 2027Gemini-integratedGoogle Cloud only

Industry impact​

1. Impact on NVIDIA​

On paper, AMD MI455X has already caught up to B200 (FP4 40 PFLOPS vs 20 PFLOPS), even leading substantially in memory capacity (432GB vs 192GB).

But:

  • NVIDIA has the CUDA ecosystem moat
  • NVIDIA has the Vera Rubin platform (full solution, 2026 Q4)
  • AMD only sells cards/nodes, NVIDIA sells AI factories
  • MI455X mass production (2026 Q4) coincides with Rubin R200 — head-on competition

2. Pressure on domestic chips​

MI455X's launch means: mainstream international AI chips enter the 2nm + HBM4 era in 2026.

Domestic chips (Huawei Ascend, Cambricon, MetaX, etc.) need to:

  • Catch up to 5nm + HBM3e by 2026-2027
  • Otherwise the gap widens from "1 generation" to "2 generations"

3. Significance for cloud providers​

MI455X gives cloud providers a second option beyond NVIDIA:

  • Microsoft Azure: already deployed MI355X, may follow with MI455X
  • Google Cloud: in-house TPU, won't use AMD
  • Amazon AWS: in-house Trainium/Inferentia, won't use AMD
  • Alibaba Cloud, Tencent Cloud: may procure MI455X as NVIDIA alternative

References​


This article is compiled from AMD CES 2026 official announcements, Baidu Baike, and Zhihu on-site reports; specs verified against official sources. Updated 2026-06-16: corrected MI455X memory (288GB → 432GB) and compute (FP8 6 PFLOPS → FP4 40 PFLOPS).