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Huawei AI chips and Ascend series

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2026 H2 AI Chip Roadmap Major Update: Qualcomm Enters, AMD MI400 Three Models Unveiled, Huawei Three-Generation Roadmap

· 7 min read
Charles Qing
AI Hardware Analyst

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.

Key Takeaways​

  • Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
  • AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
  • Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
  • Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
  • NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

1. Qualcomm: Mobile Giant Moves Into Datacenter AI​

AI 100 → AI 200 → AI 250​

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

ModelLaunchAvailabilityKey Features
AI 1002025-102026 H2Rack-scale AI inference, 768GB LPDDR per card
AI 2502025-102027 H1Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed​

  1. Low TCO: LPDDR memory is far cheaper than HBM
  2. Energy efficiency: Mobile chip design heritage, excellent power control
  3. Inference-focused: Not chasing training performance, focused on inference scenarios
  4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact​

  • Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
  • Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
  • Diversifies choice: Breaks NVIDIA's monopoly in the inference market

2. AMD MI400 Series: Three Models, Precise Positioning​

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)​

FeatureSpec
PositioningHPC + sovereign AI
FP32/FP64Supported (key differentiator)
Use casesScientific computing, climate simulation, national AI infrastructure
CompetitorNVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)​

FeatureSpec
PositioningEnterprise 8-GPU servers
CompatibilityWorks with existing datacenter infrastructure
Use casesEnterprise AI, private cloud, edge inference
AdvantageCheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)​

FeatureSpec
PositioningFlagship AI training + inference
Optimized precisionFP4/FP8/BF16
Helios rackCore component
CompetitorNVIDIA Rubin R200

Helios Rack-Scale Solution​

AMD also launched the Helios rack-scale AI solution at CES 2026:

  • 18 Zen 6 CPUs (2nm process)
  • 72 MI455X GPUs
  • Direct liquid cooling
  • Shipment expected in 2026 H2

3. Huawei Three-Generation Roadmap: 950 → 960 → 970​

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)​

ModelLaunchKey Features
950PR2026-Q1PR (inference-optimized), already in mass production
950DT2026-Q4DT (Decode + training), expected to scale up

Technical highlights:

  • Added FP8/MXFP8/MXFP4 support
  • Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)​

  • Doubled compute: All specs double versus the 950 series
  • FP8: ~2 PFLOPS expected
  • Process: N+3 (equivalent to 5nm)
  • Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)​

  • Third-generation flagship: Only timeline announced, specs TBD
  • Significance: Huawei's first complete generation-spanning roadmap
  • Signal: China's domestic AI chips have entered a "roadmap-driven" phase

4. Intel Jaguar Shores: Timeline Uncertain​

Original Plan​

  • Launch: 2026
  • Architecture: Xe-HPC + Gaudi fusion
  • Process: 18A (Intel's most advanced)
  • Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments​

  • Possible delay: Some sources suggest a slip to 2027
  • Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
  • Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap​

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.

5. NVIDIA Rubin Platform: Full Mass Production​

Rubin R200 (2026-Q2 full mass production)​

FeatureSpec
HBM288GB HBM4
Compute50 PFLOPS FP4
NVLinkNVLink 6 (1800 GB/s)
ProcessTSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)​

  • 72 Rubin GPUs
  • 36 Vera CPUs
  • 1.8 EFLOPS FP4
  • Direct liquid cooling

Vera CPU (Debut)​

  • Architecture: Custom CPU replacing Grace
  • Positioning: Deep co-design with Rubin GPU
  • Significance: NVIDIA's transformation from a GPU company into a computing platform company

6. Google TPU v8: Training/Inference Officially Split​

TPU 8t (training) + TPU 8i (inference)​

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

FeatureTPU 8t (training)TPU 8i (inference)
OptimizationHigh compute, high bandwidthLow latency, low cost
InterconnectOptical interconnectEthernet
Launch20272027

Significance​

  • Industry trend: Specialization of training/inference chips
  • Followers: Qualcomm AI 200 is also inference-only
  • NVIDIA pressure: Does it need an inference-specific chip?

7. Cerebras WSE-4: Wafer-Scale Engine Evolves​

Core Specs​

FeatureSpec
Transistors1.4 trillion
Compute125 PFLOPS FP8
Launch2026 H2
ProcessTSMC 5nm

Competitive Advantages​

  • Massive model training: A single WSE-4 can train 10T+ parameter models
  • Low-latency inference: Entire model on one chip, no communication overhead
  • Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

8. Market Landscape Analysis​

Training Market​

RankVendorProductMarket Share (est.)
1NVIDIARubin R20070%
2AMDMI455X15%
3GoogleTPU v8t10%
4HuaweiAscend 9605% (mostly China)

Inference Market (New Battlefield)​

RankVendorProductAdvantage
1NVIDIAH200 / Rubin CPXMature ecosystem
2QualcommAI 200Low TCO
3AMDMI440XGood compatibility
4IntelGaudi 4Low price

Trend 1: Rise of Inference-Specific Chips​

  • Qualcomm AI 200: Mobile giant enters the market
  • NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
  • Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard​

  • NVIDIA NVL72: 72 GPU + 36 CPU
  • AMD Helios: 18 CPU + 72 GPU
  • Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase​

  • Huawei three-generation roadmap: 950 → 960 → 970
  • Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
  • Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck​

  • SK hynix: HBM4 capacity already booked by NVIDIA
  • Samsung: HBM4E samples delivered to AMD
  • Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

10. Procurement Recommendations​

If Procuring in 2026 H2​

  1. Training scenarios:

    • First choice: NVIDIA Rubin R200 (best performance)
    • Alternative: AMD MI455X (better price/performance)
    • Domestic: Huawei Ascend 950DT (China-based customers)

  2. Inference scenarios:

    • First choice: NVIDIA H200 (mature ecosystem)
    • Best value: Qualcomm AI 200 (if available)
    • Cost-sensitive: AMD MI440X

  3. HPC scenarios:

    • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027​

  • Wait for Rubin Ultra: Performance possibly 2x R200
  • Watch MI500: AMD's next-generation product
  • Evaluate TPU v8: If already on Google Cloud

Conclusion​

2026 H2 will be the most fiercely contested half-year in AI chip market history:

  • NVIDIA continues to lead, but its advantage is narrowing
  • AMD precisely positions three models; market share will keep rising
  • Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
  • Huawei has a clear three-generation roadmap; domestic substitution accelerates
  • Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.

References​

  • AI Compute Card Future Roadmap - MirrorFrog real-time updates
  • NVIDIA Rubin R200 deep dive (see related articles on this site)
  • AMD MI400 series CES 2026 launch (see related articles on this site)
  • Qualcomm AI 100 launch analysis (coming soon)

Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement

Milestone! Huawei Ascend 910C Completes Full-Parameter Training of a 1.6-Trillion-Parameter Model

· 6 min read
AI Compute Cards Wiki Editorial
Industry Research Team

On June 5, 2026, Shenzhen announced a major piece of news: Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, used 1,000 Huawei Ascend 910C chips to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model.

This was no tentative attempt, but a milestone technological breakthrough. It proved with irrefutable engineering results that: domestic AI chips are fully capable of supporting world-class, super-large-parameter model training.

Why this matters​

The two thresholds of AI chips: "inference" and "training"​

  • Inference: using an existing model to chat, write copy. Domestic chips could already do this
  • Training: adjusting model parameters to learn new capabilities. Full-parameter training adjusts all 1.6 trillion parameters at once — maximum difficulty

Previously, full-parameter training of trillion-scale models was monopolized by NVIDIA H100/H200. Domestic chips could only do inference, not large-scale training.

The significance of this breakthrough: domestic compute leapt from "usable" to "useful", from "inference" to "training".

Technical details​

Training configuration​

ItemParameter
ChipsHuawei Ascend 910C × 1,000
ModelDeepSeek-V4-Pro
Parameters1.6 trillion (1600B)
Training typeFull-parameter post-training
FrameworkMindSpore + torch_npu
CompletedAnnounced June 5, 2026

Performance metrics​

MetricValueAssessment
Compute utilization>30%Industrial grade (top overseas chips ~40%)
Key training operator efficiency+14%vs previous-gen 910B
Communication bandwidth utilization>60% (est.)MoE All-to-All communication
Stability1,000 cards trained continuously with no failuresCluster stability met standard

💡 About 30% compute utilization: many feel 30% is low, but in large-model training this is already a very respectable industrial-grade level. Even with the most advanced overseas chips, many teams' actual utilization is around 40%.

Ascend 910C detailed specs​

Ascend 910C is Huawei's AI training/inference chip announced at the Huawei Analyst Conference (April 24, 2024), with a theoretical peak of 800 TFLOPS (BF16), in the same class as NVIDIA H100.

ParameterAscend 910CAscend 910BNVIDIA H100
ArchitectureAscend 910CAscend 910BHopper
ProcessTSMC 7nm (est.)TSMC 7nmTSMC 4NP
BF16 compute800 TFLOPS256 TFLOPS989 TFLOPS (sparse)
Memory64GB HBM (est.)64GB HBM2e (B1/B2)80GB HBM3
Memory bandwidth~2TB/s (est.)600 GB/s (B1/B2)3.35 TB/s
TDP~400W (est.)300-400W700W
Mass productionApril 2026 (full production)Nov 2022Mar 2022

Key upgrades:

  • ✅ 3× compute: from 910B's 256 TFLOPS to 800 TFLOPS
  • ✅ Mature software ecosystem: torch_npu adapts PyTorch, MindSpore framework mature
  • ✅ Cluster stability: 1,000 cards trained continuously with no failures (the biggest breakthrough)

Technical challenges and solutions​

Challenge 1: Memory demand of trillion-scale models​

A 1.6-trillion-parameter model needs, just for model parameters:

  • FP16: 1.6T × 2 bytes = 3.2 TB
  • Plus gradients and optimizer states: at least 10 TB of memory

Huawei's solution:

  • Model Parallel: distribute the model across 1,000 910C chips
  • ZeRO optimizer: optimize memory footprint
  • Gradient accumulation: update parameters in stages

Challenge 2: Communication efficiency of thousand-card clusters​

Training with 1,000 chips, inter-chip communication becomes the bottleneck. MoE models need All-to-All communication (each expert may need to communicate with all others).

Huawei's solution:

  • HCCS (Huawei Collective Communication Scheduler): in-house high-speed interconnect protocol
  • Layered communication: intra-node NVLink + inter-node HCCS
  • Communication-compute overlap: data transfer concurrent with computation

Challenge 3: Training stability​

Trillion-scale model training takes weeks or months; any single card failure can interrupt the entire training.

Huawei's solution:

  • Fault detection and auto-recovery: real-time monitoring of card status, auto-restart and recovery on failure
  • Checkpoint optimization: high-frequency training-state saves (every N steps)
  • Ascend cluster management software: designed specifically for enterprise training

Competitive comparison​

VendorChip1.6T-param trainingEcosystem maturityAvailability
HuaweiAscend 910C✅ Completed⭐⭐⭐ (improving)China-localized
NVIDIAH100/H200✅ Industry standard⭐⭐⭐⭐⭐Global (export-controlled)
AMDMI300X✅ Feasible⭐⭐⭐⭐Global
GoogleTPU v5p/8t✅ JAX-native⭐⭐⭐⭐Google Cloud

Conclusion: Ascend 910C has caught up to H100 in hardware performance, still lags in software ecosystem, but this training success proves engineering feasibility.

Industry impact​

1. The "Zunyi Conference" of domestic compute​

This breakthrough is called the "Zunyi Conference" of domestic compute — from passive defense to strategic counteroffensive.

Specific impact:

  • ✅ Breaks the bias that "domestic chips can only do inference"
  • ✅ Proves domestic chips can train frontier models
  • ✅ Provides compute foundation for domestic large models (e.g., DeepSeek-V4, ERNIE 5.0)

2. Impact on NVIDIA​

Huawei Ascend 910C completing trillion-scale training means China's AI industry is less dependent on NVIDIA.

ScenarioBeforeNow
InferenceDomestic chips usableDomestic chips useful
TrainingMust use H100/H200Can use 910C
Large-scale trainingMust use H100 clustersCan use 910C clusters

3. Boost to the domestic chip industry​

This breakthrough will drive the entire domestic AI chip supply chain:

  • Chip design: Cambricon, MetaX, Moore Threads accelerate iteration
  • Wafer manufacturing: SMIC, Hua Hong get more orders
  • Packaging/test: JCET, TFME benefit

Huawei Ascend roadmap (2025-2028)​

TimeChipPositioning
Q1 2025Ascend 910CFlagship training/inference (mass-produced)
Q1 2026Ascend 950PRInference-optimized (~500 TFLOPS BF16)
Q4 2026Ascend 950DTData-center training
Q4 2027Ascend 960Next-gen flagship
Q4 2028Ascend 970Next-next-gen

Training lessons shared​

The Shenzhen Hetao College team accumulated valuable experience:

✅ Successes​

  1. Progressive training: start from small models (7B), gradually scale to 1.6T
  2. Mixed-precision training: BF16 main + FP32 gradient accumulation
  3. Communication optimization: All-to-All overlap with computation
  4. Fault recovery: save checkpoint every 1,000 steps

⚠️ Challenges encountered​

  1. Memory fragmentation: severe fragmentation over long training, needs periodic cleanup
  2. Communication bottleneck: MoE All-to-All takes 30%+ of training time
  3. Software bugs: torch_npu occasional memory leak, needs training process restart

References​

This article is compiled from public reports. Salute to the teams at Shenzhen Hetao College, HIT (Shenzhen), and Huawei — you proved the feasibility of China's AI compute with engineering results.