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Hyperscaler Custom Silicon Wave 2026: OpenAI Jalapeno, Maia 200, MTIA, TPU v8 Together "De-NVIDIA-ize"

· 6 min read
AI Compute Cards Wiki Editorial
Industry Research Team

The Tuesday-afternoon AI session at Hot Chips 2026 this August was the most historically significant of the conference — not because any single chip was so powerful, but because almost everything on stage was a "hyperscaler de-NVIDIA-ization" custom ASIC: Google's 8th-gen TPU, OpenAI's first self-designed chip, Microsoft Maia, Meta MTIA, and Cerebras wafer-scale racks, all on one stage. When the world's largest AI compute buyers start treating GPUs as "one of the options," the power structure of AI hardware is loosening.

1. OpenAI Jalapeno: Building a Chip in 9 Months​

On June 24, 2026, OpenAI, together with Broadcom, unveiled its first self-designed inference ASIC, Jalapeno — the fifth member of the "custom inference chip club."

DimensionJalapeno
PartnerBroadcom + TSMC manufacturing
PositioningInference-specific ASIC
Design cycle9 months end-to-end (Greg Brockman says aided by OpenAI's own models)
Cost target~50% lower token cost vs general-purpose GPU stack
Commercial timingFirst deployments by end-2026; long-term goal 10GW of self-designed chips
Deal scaleUp to $10B strategic partnership with Broadcom (accelerators + networking by 2029)

The talk title "You Can Just Build Things … Chips" is itself a signal: the largest AI compute buyer no longer defaults to GPU as the only path.

2. Google TPU v8: The Biggest Architectural Pivot in a Decade — Train/Infer Split​

Google has the longest custom-chip history (2016 to now), and its 8th-gen TPU for the first time splits the product line in two:

ModelCodenamePartnerPositioningKey Specs
TPU 8tSunfishBroadcomTraining9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM, 2× ICI bandwidth
TPU 8iZebrafishMediaTekInference288GB HBM, 384MB on-chip SRAM (3× prior gen), 19.2 Tb/s ICI

On capacity, Morgan Stanley estimates based on supply-chain interviews that Google TPU production in 2026 may exceed 3 million units (a brokerage estimate, not an official target). Google is also the only vendor to achieve large-scale custom-chip deployment and sell compute externally (Gemini runs on TPUs).

3. Meta MTIA: From Recommendation Systems to a GenAI Dual Mission​

Meta's custom journey has the clearest starting point — MTIA was originally built for recommendation ranking hardware and is being pulled toward a dual mission by generative AI.

  • MTIA 300 is deployed; 400 / 450 / 500 are planned at roughly one new model every 6 months through 2027;
  • Based on RISC-V, Meta claims up to 25× compute gain;
  • Node evolves with industry cadence: 100 (7nm) → 200 (5nm) → 300 series (3nm + CoWoS);
  • In partnership with Broadcom; another chip codenamed Iris reportedly passed testing in July 2026;
  • Meta plans to start volume production of one of them in September 2026, doubling its overall compute.

4. Microsoft Maia 200/300: Most Advanced Deployment​

Microsoft's Maia 200, released January 26, 2026, is the most advanced in deployment among the four:

DimensionMaia 200
ProcessTSMC 3nm, 140B+ transistors
Compute10+ PFLOPS FP4 / 5 PFLOPS FP8
Memory216GB HBM3E, 7 TB/s
Power750W
DeploymentAlready running in Des Moines data center, serving OpenAI GPT-5.2 and Microsoft 365 Copilot

Microsoft claims roughly 3× the performance of Amazon's Trainium on specific benchmarks. The short-term strategy is a dual track of "self-designed Maia + purchased NVIDIA" in parallel — self-designed chips need time from design to mass production, and NVIDIA's mature ecosystem cannot be replaced in the short term.

5. Amazon Trainium 3 and Anthropic's In-House Team​

  • Amazon: The Trainium series is already commercial, with 1.4 million units cumulatively deployed (officially disclosed) — a multi-billion-dollar business; its strength is the AWS customer base, letting enterprises choose between NVIDIA GPUs and self-designed chips. Trainium 3 continues this path.
  • Anthropic: In August 2026 announced the formation of an in-house chip team, with no tape-out or mass-production timeline yet; initially positioned as a complement (not a replacement) to existing partnerships with NVIDIA/AMD/AWS/Google Cloud, aiming to tailor-build for the Claude architecture and shed reliance on a single GPU.

6. NVIDIA's Answer: Not a Faster GPU, But Full-Stack​

It's easy to simplify the narrative to "four companies build chips, NVIDIA defends GPU." But NVIDIA took 6 slots at Hot Chips: a RISC-V tutorial, the Vera CPU, the Rubin GPU, the BlueField-4 DPU, the Spectrum-X multi-plane network, and an LPU accelerator.

A hyperscaler ASIC replaces only one of those five pillars. If the CPU, NIC, switching fabric, and software all come from the same vendor, what you save by swapping out the accelerator is far less than the accelerator line item on the bill suggests. Rubin's play is a full-stack AI factory platform spanning seven chips and five racks — the competitive answer is "full-stack positioning," not "a faster single chip."

7. Trend Judgment: Inference De-GPU-izes, Training Still GPU-Led​

  • Inference side: The CUDA moat visibly shallows. Inference is parallelizable and replaceable at the endpoint; custom ASICs trade away the generality tax (implementing only the operations LLMs actually execute) for lower cost/token. Groq LPU, Cerebras, and various TPU/ASIC players all compete on the same metric.
  • Training side: Foundation models are still trained on GPUs, with no serious challenger in the short term. NVIDIA's three training moats (fastest silicon + NVLink + CUDA) remain firm.
  • Conclusion: Custom chips are not "replacing NVIDIA," but giving buyers a credible external negotiation option in the largest and fastest-growing battlefield — inference. That alone is enough to reshape the economics of AI infrastructure.

References​

This article is compiled from August 2026 Hot Chips on-site reports, corporate announcements, and industry analysis. Some capacity and performance figures are brokerage estimates or vendor-disclosed figures; actual results are subject to mass-produced products.

HBM4 Mass-Production Year One: Samsung Yield Breaks 80%, Three Giants Pass NVIDIA Certification, the Last Bottleneck of AI Compute Supply

· 6 min read
AI Compute Cards Wiki Editorial
Industry Research Team

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.

1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

TimelineSamsung HBM4 YieldNotes
Feb 2026 (mass production start)Under 60%Line ramp-up period
Early Aug 2026~80%Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.

2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor2026 Rubin HBM4 Allocation (est.)Notes
SK Hynix60%–70%Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung25%–30%Rapid share gains after yield leap
MicronRemainderLimited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.

3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

  • Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
  • HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
  • Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

SpecHBM4 (12-Hi / 16-Hi)HBM4E
Per-stack capacity36 GB / 48 GB—
Pin rate11.7–13.0 Gbps16 Gbps
Per-stack bandwidthup to 3.3 TB/sup to 3.6 TB/s
Bus width2048-bit—
Energy efficiency+40% vs HBM3E—
Thermal resistance / cooling+10% improvement / +30%—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.

5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

  • 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
  • The industry already anticipates significant price increases;
  • For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.

6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

References​

This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

Domestic Big Three 2026 H2: Localization Rate Crosses 40% Toward 60%, Ascend 960 Roadmap, MLU690 and S5000 Ecosystems Ramp Up

· 6 min read
AI Compute Cards Wiki Editorial
Industry Research Team

In 2026, China's AI chip market landscape has shifted from "NVIDIA unipolar dominance" to "overseas vendors leading, domestic multi-route catch-up." According to industry research, China's overall AI accelerator market was ~4M units in 2025, of which 1.65M were domestic, with share first breaking 40%; as products iterate and fabs follow up, the localization rate is expected to rise to 60%-70% by 2027. This article focuses on the latest H2 2026 progress of Huawei Ascend, Cambricon, and Moore Threads — the domestic "Big Three."

1. Huawei Ascend: 950 Capacity Fully Booked, 960 Roadmap Unveiled​

Ascend's core advantage is "architecture + full-stack ecosystem synergy," with ~800K units shipped in 2025, capturing 50% of the total domestic vendor share. The product iteration cadence is clear:

TimeProductNote
2025 Q1Ascend 910CMain transitional model
2026 Q1Ascend 950PRInference flagship
2026 Q4 (planned)Ascend 950DTTraining flagship, drives domestic HBM iteration
2027-2028Ascend 960 / 970Roadmap products

950 series capacity has entered a "fully booked" state: 950PR entered mass production in April 2026; June monthly capacity jumped to 500K-600K units (nearly 10x MoM), with a full-year target of 1.2M units at 100% certainty; ByteDance locked in 350K units for $5.6B, while Tencent / Alibaba / Baidu combined locked in 400K units.

Ascend 960 roadmap specs (per roadmap disclosure):

MetricAscend 960
ArchitectureAscend 6th gen (Da Vinci v6)
FP8 compute~4 PFLOPS
Memory288GB
Memory bandwidth9.6 TB/s
Super-nodeAtlas 960 SuperPoD, 15,488 cards, Lingqu optical-electrical converged bus
Debut2027 Q4 (roadmap)

The previous-gen Ascend 384 super-node has cumulatively shipped over 750 sets, deployed across 20+ industries including internet, operators, finance, education, and healthcare — Huawei calls it "the only domestic super-node that has trained a SOTA model."

2. Cambricon MLU690: H2 Mass Production, Entering ByteDance Bidding Window​

Cambricon is the core domestic compute leader in the absence of an Ascend IPO, with the technology gap continuously narrowing:

  • Siyuan 590 (7nm): Performance equivalent to 80% of A100, already supports DeepSeek, continuously adapting to mainstream large models like Qwen 3 and GLM
  • Siyuan 690 series: Will enter mass production in H2 2026, expected to achieve order scale-up during ByteDance's H2 bidding window
  • Revenue certainty: Equity incentive targets show >100% revenue growth for the next 3 years: 2026 revenue target 13.5B RMB, 2027 27B RMB, 2028 60B RMB

Cambricon fully benefits from the industry dividend of "domestic CSP capex + full adaptation of domestic large models and domestic chips," making it the most direct elasticity play on rising localization rate.

3. Moore Threads MTT S5000: Full-Function GPU + Ecosystem Breakthrough​

Moore Threads takes a differentiated "full-function GPU" route, with the flagship MTT S5000 based on the 4th-gen "Pinghu" MUSA architecture:

MetricMTT S5000
Dense AI compute1000 TFLOPS
Memory80GB
Memory bandwidth1.6 TB/s
Inter-card interconnect784 GB/s
PrecisionFP8 to FP64 full precision (training + inference)
SecurityFirst batch to pass national "Safe and Reliable Evaluation" (Level I)

Its engineering capability is verified: the Kuae (KUAE) intelligent computing cluster based on S5000 achieves 95% training linear scaling efficiency, with compute efficiency loss within 5% at ten-thousand-card scale; supports checkpoint-resume training with effective training time ratio >90%; and has trained a MoE-236B base model with >25 trillion tokens of corpus from scratch.

The ecosystem is Moore Threads' deepest moat: MUSA has achieved 100% core math library compatibility, 3000+ PyTorch operator compatibility, covers 55 categories of core AI operators, has official vLLM and SGLang support, Day-0 adaptation of mainstream models, and 800K+ developers. Its PD heterogeneous-disaggregation solution achieves equivalent replacement of international high-end GPUs at a 2:1 ratio with S5000, significantly reducing inference cost.

The 5th-gen "Huagang" architecture (released 2025-12) supports FP4 to FP64 full precision, with 50% higher compute density and 10x better energy efficiency than the previous gen, supporting 100K+ card clusters; cumulative R&D investment in the "Huashan" (train-infer integrated) and "Lushan" (graphics rendering) new chips based on this architecture exceeds 900M RMB.

4. Software Ecosystem Decides: Day-0 Adaptation Becomes Routine​

Beyond hardware, software ecosystem realization is the watershed for domestic compute in 2026:

  • Huawei's CANN heterogeneous computing architecture and MindSeries suite are fully open-sourced, with the community incubating 67 projects, 12.44M+ lines of code, and 3,500+ monthly active developers
  • The "release-and-adapt" closed loop between domestic large models and domestic chips has basically formed: Tencent Hunyuan T3 (295B), DeepSeek-V4, and GLM-5.2 all completed Day-0 adaptation
  • 2026 is regarded as the "first year of domestic super-nodes"; Huatai Securities estimates China's super-node architecture market will reach 341.4B RMB by 2028, with a 2026-2028 CAGR of 194%

5. Industry Judgment: From "Can It Be Built" to "Can It Be Used Well"​

The domestic Big Three are converging along three paths:

  1. Huawei: Locks government/enterprise and internet big customers with super-node system-level capability + full-stack software
  2. Cambricon: Impacts the revenue inflection point by narrowing the training-side gap + scaling up via big-customer bidding
  3. Moore Threads: Covers cloud-edge-end full scenarios with full-function GPU generality + mature CUDA-compatible ecosystem

The common shortcoming of all three remains advanced process and HBM supply — precisely the core link of overseas controls. But as domestic HBM iterates and fabs follow up, a realistic path to 60%-70% localization by 2027 exists.

References​

This article is compiled from public industry research, broker views, and corporate announcements as of August 2026. Some shipment and market-share figures are third-party estimates, not officially confirmed data.

Inference Accelerator Market 2026: 60%–70% of the Accelerator Market, GPU vs ASIC Share Inverts, Five Schools Clash

· 5 min read
AI Compute Cards Wiki Editorial
Industry Research Team

For the past three years, the entire AI hardware story was "training": who had the most H100s, who could connect a hundred thousand GPUs into a cluster. That race is essentially settled — NVIDIA won. But the next battlefield, "inference," is being fought under completely different rules: the measure is no longer peak FLOPS, but cost-per-token, latency, and power. In 2026, inference chips overtake training in scale for the first time, becoming the main battlefield of AI accelerators.

1. Inference Becomes the Main Battlefield: 80%–90% of Compute Spent on Inference​

Training a large model costs hundreds of millions of dollars — once. But once the model goes live, it must answer billions of queries day after day. A popular consumer model may need tens of thousands of accelerators running 7×24 to keep up with demand. Therefore:

  • Inference accounts for roughly 80%–90% of a model's lifecycle compute;
  • Inference chips will make up about 60%–70% of the ~$400B AI accelerator market in 2026, up from only ~40% in 2023;
  • Inference chip growth (estimated +52.7% YoY) significantly outpaces training chips (+28.4%); the share of inference-side compute demand exceeded training-side for the first time in 2026, reaching 54% (~$1010B).

The economics of inference are straightforward: training cost is amortized to near-zero, while inference cost becomes the entire bill. Every 1% cut in inference cost flows directly to profit — for a company whose inference traffic reaches hyperscale like OpenAI, the half of the bill is a number followed by a string of zeros.

2. Market Size: Structural Growth Inflection Point Has Arrived​

Market2026 SizeGrowthNotes
Global dedicated inference chips$412.7B+38.4%14.2 pct higher growth than training chips
China dedicated inference chips$118.6B (28.7% of global)+44.1%Strongest single market in APAC by growth
Global AI training/inference chips (incl. GPU/NPU)exceeds $1850B+40.2%GPU ~62%

China's domestic substitution is accelerating, with domestic inference chips reaching 34.6% of shipments, up 9.8 pct from 2025.

3. Technology-Axis Share Inverts: GPU Slows, ASIC Soars​

Axis2026 Shipment ShareTrend
GPU52.6%Still leads, but growth slows to 22.7%
ASIC custom chips41.3%Up sharply from 17.8% in 2022
FPGAStableSpecific low-latency scenarios

Thanks to ecosystem maturity, GPU remains the mainstay, but NPU/ASIC already holds a 1.8× advantage over same-generation GPUs in energy efficiency, driving rapid adoption at the edge and on-device. Shipments of inference-optimized ASICs are expected to reach 11.5 million units, with unit cost about 35% lower than GPUs.

4. Five Schools Clash​

SchoolRepresentative ProductsCore StrengthUse Cases
General-purpose GPUNVIDIA Rubin / B200 / H200Mature ecosystem, train+infer unifiedFrontier training + highly interactive inference
LPU (Language Processing Unit)Groq LPUUltra-low latency, deterministic throughputReal-time dialogue, high-concurrency inference
TPU (inference-specific)Google TPU 8i (Zebrafish)288GB HBM, 384MB on-chip SRAM, 19.2 Tb/s ICIGoogle's scaled inference
Custom ASICOpenAI Jalapeno, Microsoft Maia 200, Meta MTIAStrip generality tax for own models, ~50% lower cost/tokenHyperscaler's own workloads
Air-cooled inference cardIntel Crescent Island350W air-cooled, 480GB LPDDR5X, tokens/wattCost-sensitive mid/long-tail inference

OpenAI's Jalapeno, co-developed with Broadcom, aims to cut inference token cost by roughly 50% versus a general-purpose GPU stack — the fifth member to join the "custom inference chip club" (after Google TPU, Amazon Inferentia/Trainium, Microsoft Maia, and Meta MTIA).

5. Core Metric Shifts: cost-per-token and tokens/watt​

The fundamental difference between the inference race and the training race is the low switching cost:

  • Training requires a 100k-GPU cluster + NVLink + CUDA, with extremely high migration cost;
  • Inference is "embarrassingly parallel" at the endpoint level — no million-GPU cluster needed; a node that produces tokens fast and cheaply suffices, and is replaceable per endpoint.

This means NVIDIA's three moats (fastest silicon, NVLink scale-out, CUDA) are no longer absolute on the inference side. When the largest AI buyer (OpenAI) starts treating GPUs as "one of the options," the GPU premium begins to erode — pricing power relies on scarcity, and custom chips attack that scarcity from two directions at once: both reducing merchant-chip demand and giving buyers a credible external negotiation option.

6. Edge and On-Device Explosion: Long-Tail Signal​

Demand shows significant long-tail and fragmentation:

Scenario2026 Demand SizeGrowth
Cloud inference$198.2B (48%)+24.5% (slowing)
Edge inference$126.5B (30.7%)+52.3%
On-device inference$88.0B (21.3%)+68.9%
Autonomous-driving inference$67.3B+58.2%
Industrial QA / robotics inference$42.1B+63.7%

The latency sensitivity and power constraints of inference workloads are reshaping chip architecture design priorities — which also explains why "air-cooled, large-memory" solutions like Crescent Island can find a niche.

References​

This article is compiled from publicly available 2026 market research, brokerage reports, and industry analysis. Market sizes and shares are third-party estimates with inconsistent methodologies and are for reference only.

Domestic GPU IPO Wave: The "Four Little Dragons" Assemble on Capital Markets, Moore Threads MTT S5000 Benchmarks Against H100

· 5 min read
AI Compute Cards Wiki Editorial
Industry Research Team

From December 2025 to July 2026 — just half a year — at least 6 AI chip companies have listed or are about to list on capital markets. Together with already-listed Cambricon, Hygon, and Iluvatar, the domestic GPU corps' total market cap is approaching ¥2 trillion. This marks the critical climb from domestic GPUs being "usable" to "useful."

1. The "Four Little Dragons" assemble on capital markets​

CompanyListing statusRaise / issue priceSponsor
Moore ThreadsListed (STAR Market sh688795, 2025-12-05)Issue price ¥114.28, raised ¥8BCITIC Securities
MetaXIPO accepted (2026-06-30)¥3.904B (total investment ¥5B)Huatai United
EnflamePassed review (2026-06-15)¥6B—
BirenHKEX / sprinting——

Already-listed camp: Cambricon (sh688256, STAR Market 2020-07-20), Hygon, Iluvatar (HKEX). Moore Threads turned a book profit of ¥29.35M in Q1; MetaX narrowed losses 57.7% and gave a 2026 breakeven timeline.

2. Moore Threads MTT S5000: benchmarking against H100​

Moore Threads announced its flagship AI train+inference GPU MTT S5000 successfully completed full-pipeline adaptation validation of Zhipu's new-generation large model GLM-5 — measured performance "breaks the domestic compute ceiling":

MetricMTT S5000
Architecture4th-gen "Pinghu" architecture
FP8 compute1 PFLOPS (1,000 TFLOPS)
Memory bandwidth1.6 TB/s
PositioningFull-function train+inference GPU, benchmarks against NVIDIA H100
ProductionMass-produced; clusters online supporting trillion-parameter training

Deployment validation: jointly completed full-pipeline training of embodied-brain model RoboBrain 2.5 with BAAI; partnered with SiliconFlow for high-performance DeepSeek-V3 inference, single-card speed near international top products. IPO funds go to three directions: next-gen AI train+inference chip, next-gen graphics chip, next-gen AI SoC chip.

WAIC 2026 new progress: Moore Threads showcased the MTT C256 SuperNode (first-of-its-kind single-layer Scale-up 256-card full interconnect, sub-microsecond latency) and three AI-factory solutions — "model training factory / token production factory / agent production factory"; the company pre-announced H1 2026 revenue of ¥1.65B-1.75B, up 135%-149% YoY.

3. Cambricon: dual flagships MLU590/690​

ChipProcessComputeMemoryCustomer / status
MLU590 (思元590)7nm ChipletINT8 512 TOPS / FP16 345 TFLOPS96 GB HBM2eByteDance inference mainstay, ~80% of A100 overall, mass shipments early 2026
MLU690 (思元690)5nm-class (SMIC N+2)FP16 700+ TFLOPS / INT8 2800+ TOPS196 GB HBM3 (3.35 TB/s)Dual-die packaging, MLU-Link 890 Gbps; ~70% of H100 (80-90% pure inference); ByteDance largest customer, mass production early 2026

Cambricon is the only domestic AI chip vendor with a "unified edge-cloud architecture" — one MLU instruction set spans 思元 220 (edge) → 370 (border) → 590/690 (cloud), with one NeuWare toolchain across compute tiers.

Capital and performance double explosion: Cambricon's total market cap exceeded ¥1 trillion on June 30, 2026, becoming the STAR Market's first "trillion-yuan stock," up 75%+ YTD. On performance, Q1 2026 revenue ¥2.885B (+160% YoY), deducted net profit ¥934M; full-year 2025 revenue ¥6.497B (+453% YoY), net profit attributable to parent ¥2.059B, ending long-term losses. ByteDance has cumulatively deployed over 100k 思元 590/690, its largest customer.

4. DeepSeek-V4 effect: changing the expectation coordinate system​

On April 24, 2026, DeepSeek released the trillion-parameter flagship DeepSeek-V4. Unlike a year earlier when V3's launch sparked debate over "can domestic chips even run large models," this time multiple domestic chips — Huawei Ascend, Cambricon, Hygon, MetaX, Moore Threads, Kunlun, T-Head, Iluvatar — completed adaptation on launch day.

The evaluation coordinate system is shifting: from "what percentage of NVIDIA's same-generation product performance" to "can it carry the real workloads of top-tier large models."

Industry interpretation​

  1. Capital ammunition in place: dense IPOs provide ample funding for domestic GPU R&D iteration and capacity expansion, moving from "technology breakthrough" to "commercial virtuous cycle."
  2. Train+inference becomes the mainstream route: Moore Threads takes the full-function GPU route (graphics+AI+general compute), differentiating from Huawei Ascend's "AI-focused."
  3. Software ecosystem is the decider: Day-0 adaptation and the maturity of unified software stacks (MUSA / NeuWare / MXMACA) are replacing raw peak compute as the core yardstick of domestic GPU "usability."

References​

This article continuously tracks the domestic GPU listing process and product iteration.

Huawei Ascend 950 Series Capacity & Orders Deep Dive: 950PR Monthly Capacity Jumps 10×, ByteDance Locks In 350k Units for $5.6B

· 4 min read
AI Compute Cards Wiki Editorial
Industry Research Team

The Ascend 950 series (950PR inference / 950DT training) has become the core supply of domestic AI compute. Per multiple brokerages and industry research, 950 series capacity is 100% booked with scarce spot supply; the full-year 1.2M-unit target is "100% certain," with expectations of an upward revision to 1.5M. This article summarizes capacity and order data as of July 2026.

1. Capacity pace: ~10× MoM jump in June​

Time950PR monthly capacityNotes
May 202650k-60k unitsNear full production
June 2026500k-600k units~10× MoM; SMIC, Hua Hong tier-1 suppliers on overtime
Q3 2026 (est.)700k-800k unitsPer month
Full-year 2026 target1.2M unitsUpward revision to 1.5M expected

Supply chain delivery is tight: high-speed backplanes and liquid-cooling connectors' lead time stretched from 2 weeks to 6-8 weeks; orders are booked into 2027.

2. Order structure: top cloud providers + operators + overseas​

CustomerLocked volumeAmount / Notes
ByteDance350k 950PR$5.6B, concentrated delivery from Q3 2026
Tencent / Alibaba / Baidu~250k 950PR + 150k 950DTCombined ~400k units
Three major operators200k+ unitsCentralized procurement, for intelligent compute centers and AI private networks
OverseasSouth Korea 2,000 units, Malaysia 3,000 servers, Russia ten-thousand-card clusterFrom pilot to commercial

3. Shipment forecast: firmly #1 domestic​

Per CCA (Kezhi) Consulting estimates:

Metric20252026 (forecast)
Huawei Ascend total shipments812k cards1.026M cards
Of which 950PR—~800k units
Of which 950DT—~100k-200k units

Huawei has completed the product transition from the 910 series to the 950 series. The internet industry has become Ascend's largest application market; competitive advantage is extending from single-hardware performance to software ecosystem and system capabilities.

4. Going overseas: formal South Korea entry in Q4​

Per Korean media ETNews, Huawei plans Q4 2026 to formally enter the South Korean market with the Ascend series and Atlas 950 SuperPod:

  • Local distributor agreements signed; two channel partners including SK Shieldus selected
  • Main products: 950PR (mass-produced and delivered since April) and 950DT (launched Q4)
  • Official line: 950PR inference performance is 2.87× that of H20, priced at about 1/4 of it

5. WAIC 2026: 1024-card live debut confirmed​

At WAIC 2026 (July 17-20, Shanghai), Huawei's Atlas 950 SuperPoD live hardware made its first public appearance — a 16 compute-cabinet, 1,024 Ascend-card scale — and won the conference's top honor, the SAIL Award:

  • Core metrics: total compute 1 EFLOPS FP8 / 2 EFLOPS FP4, 256 TB globally unified memory addressing, Lingqu 2.0 interconnect, 3 μs ultra-low RTT latency
  • Full configuration: 128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡ footprint, carrying 8,192 Ascend 950DT, planned Q4 2026 launch
  • Commercial foundation: previous-gen 384 SuperNode has cumulatively shipped 750+ units, deployed in 20+ industries
  • Software ecosystem: CANN fully open-sourced end of 2025; community incubated 67 projects, 12.44M+ lines of code, 3,500+ monthly active developers

WAIC's debut confirmed the 950 series' "SuperNode-first" product logic: beyond single-card compute, system-level effective compute (interconnect bandwidth + unified memory + low latency) is the key dimension for domestic compute to benchmark against international flagships.

Ascend roadmap recap​

ProductPositioningKey metrics (official roadmap)
950PRInference1 PFLOPS (FP8) / 2 PFLOPS (FP4), 2 TB/s interconnect
950DTTrainingSuperNode core, launched Q4
960Train/inference2 PFLOPS (FP8) / 4 PFLOPS
970Next-genIn planning

Industry interpretation​

  1. Domestic substitution moves from inference to training: 950PR (inference) ramps first, 950DT (training) follows in Q4, combined with the Atlas 950 SuperPoD ten-thousand-card interconnect — domestic compute now has the complete "training substitution" puzzle for the first time.
  2. Capacity is the biggest variable: order certainty is extremely high, but SMIC/Hua Hong advanced-process capacity, HBM supply, and advanced packaging remain ramp bottlenecks — the root of "scarce spot supply."
  3. Going overseas opens a second growth curve: bulk procurement from South Korea, Malaysia, Russia, and Latin America marks domestic compute's shift from "internal circulation" to "external circulation."

References​

Data in this article is based on official and major brokerage research; capacity/orders are dynamic figures and will be continuously updated.

2026 Global AI Computing Report & Ten Major Computing Industry Trends Released

· 7 min read
AI Compute Cards Wiki Editorial
Industry Research Team

On May 29, 2026, during the World Intelligence Expo 2026 in Tianjin, the China Intelligent Computing Industry Alliance, National Supercomputing Center in Tianjin, Tianjin Artificial Intelligence Society, Shenzhen Artificial Intelligence Industry Association,ZDNET, and ZDNET ThinkTank jointly released the "2026 Global AI Computing Development Research Report."

The report analyzes the current state and future trends of the global AI computing industry, revealing that the sector has entered a new stage of "intelligence-driven, system-reconstruction."

Core Viewpoints​

1. Computing power becomes a national strategic element​

The global computing industry is entering a new stage of "intelligence-driven, system-reconstruction." With the rise of the "token economy," computing power has become a key foundational element supporting national technological breakthroughs, industrial competition, and strategic positioning.

Computing is evolving from traditional IT support into a strategic bedrock driving scientific innovation and the industrial revolution.

2. AI computing development covers the full chain​

AI computing development must upgrade the full chain of chip, system, and compute cluster, while matching the differentiated computing needs of model training, inference, and data preparation.

  • Training: pre-training of super-large models needs ten-thousand-card-scale compute
  • Inference: super-large models need thousand-card-scale compute
  • Data preparation: needs tens to hundreds of cards

Compute demand at both training and inference ends will keep growing.

3. Domestic AI chip industry's distinctive path​

The domestic AI chip industry follows a route of "autonomy + cluster breakthrough + hardware-software integration + cost-performance advantage," distinct from the foreign pursuit of absolute single-chip compute — better suited to large-scale deployment.

4. Energy challenges for computing centers and solutions​

Computing centers have become the fastest-growing source of global electricity demand. The future requires a diversified energy supply of "short-term wind-solar-storage integration, mid-term nuclear, long-term hydrogen."

Meanwhile, space computing will become a new direction to solve ground-based computing bottlenecks.

5. Compute-network convergence as a core direction​

Future computing will move toward "compute-network convergence," making compute as on-demand as water and electricity — a core part of the national modern infrastructure system.

The computing network has been included in the national "15th Five-Year Plan" major engineering projects, ranked alongside public infrastructure such as hydro power.

Key Data​

Compute performance evolution​

MetricEvolution trend
Chip computefrom TFLOPS scale up to tens of PFLOPS
System formfrom single 8-card machine to thousand-card super-node architecture
Cluster scalefrom thousand-card clusters to hundreds-of-thousands-card clusters
Cluster powerfrom kilowatt to gigawatt scale

Global computing center capacity & energy forecast​

  • Global computing center total capacity: expected to grow from 102GW (2026) to 220GW (2030)

    • AI load capacity from 62GW to 156GW, share rising to 71%

  • U.S. computing center annual electricity: expected to grow from 292TWh to 606TWh, share of national demand rising to 11%

  • China computing center total capacity: ~60GW by 2030, AI load share rising to 48%

  • Global computing center electricity: per IEA base scenario, from ~415TWh (2024) to ~945TWh (2030), ~15% CAGR

Embodied intelligence compute support data​

  • Cloud compute: can generate PB-scale interaction data daily; large-model training cycle shortened from months to weeks
  • Edge compute: tens-to-hundreds of TOPS enables 10–50ms low-latency real-time perception & decision

Industry Trend Analysis​

1. Heterogeneous architecture upgrade​

From traditional CPU+GPU to a new GPU+LPU+CPU+DPU heterogeneous inference architecture.

CPU plays the core role of task scheduling, data pre-processing, serial tasks, and system interconnection in heterogeneous architectures. In 2010, "Tianhe-1A" pioneered large-scale CPU+GPU deployment, leading the global intelligent-computing underlying architecture direction.

2. Clear scale-up / scale-out paths​

  • Scale Up: pursue extreme performance by raising single-node hardware config
  • Scale Out: add nodes for load sharing and high availability

Together they form the core support of computing system capability.

3. Super-node servers become mainstream​

With ultra-high interconnect bandwidth and low communication latency, they shorten model training cycles.

Representative products:

  • Huawei Ascend 384 super-node
  • Sugon scaleX640 super-node
  • Alibaba Cloud Panjiu AL128 super-node
  • Inspur YuanNao SD200
  • Kunlunxin super-node solution

4. Long-context processing optimization​

Through Compressed Sparse Attention (CSA), Heavy-Compressed Attention (HCA) and sliding-window mechanisms, build a "coarse + fine, sparse + dense" long-context modeling system to improve compute efficiency.

Representative application: DeepSeek-V4 attention architecture design.

AI chips​

International vendors:

  • NVIDIA: leads high-end training/inference with Blackwell and Rubin architectures
    • GTC 2026 Taipei (June 1) major releases:
      • Vera Rubin platform in full mass production: NVL72 rack system, agent throughput 10x over Grace Blackwell
      • Vera CPU released: 88-core Olympus in-house Armv9.2, LPDDR5X 1.5TB, 1.2 TB/s, world's first CPU with native FP8
      • RTX Spark AI PC chip: co-developed with MediaTek and Microsoft (codename N1X), Blackwell GPU 1 PFLOP, 128GB unified memory, TSMC 3nm
      • Nemotron 3 Ultra open model: SSM+MoE hybrid, 5x inference speed, 30% lower cost
    • Expanding advantage via CUDA ecosystem
  • Google: deepens vertical HW/SW integration via in-house TPU
  • AWS: Trainium (training) + Inferentia (inference) for cost-effective cloud compute

Domestic vendors: a product matrix represented by Huawei Ascend 910C, Kunlunxin P800, Moore Threads MTT S5000, MetaX XiYun C600.

In 2026 Huawei proposed the "Tao (τ) Law," aiming to systematically reduce the time constant and raise transistor density via logic folding, driving domestic chip evolution.

AI workstations​

  • Form factors: tower, mobile, mini — for different deployment scenarios
  • Compute tiers: entry, professional, enterprise — covering personal dev to enterprise deployment

AI servers​

  • By function: training AI servers and inference AI servers
  • By deployment: cloud AI servers and edge AI servers

With high compute output, high memory bandwidth, and high-speed interconnect, suited to large-scale parallel tasks.

AI computing centers​

  • Trending toward "high AI share, high power density, high electricity consumption"
  • Ultra-large AI computing centers become the construction focus
  • Energy supply moving toward diversified clean sources

Space computing is a new direction, leveraging space's continuous sunlight, extreme cold/vacuum, and interference-free environment to solve ground centers' energy, cooling, and interconnect bottlenecks. Starcloud and Guoxing Weiyu have begun exploration.

1. Scientific research paradigm shift​

The "dry-wet closed loop" research paradigm becomes mainstream, forming a loop between AI-driven "dry experiments" and automated "wet experiments" via data feedback — shifting science from experience-driven to model-driven.

2. Synthetic biology empowerment​

AI's multi-task learning and unknown-space exploration can decode biology's complex "sequence–structure–function" mapping, enabling breakthroughs in protein synthesis, gene editing, and nucleic-acid vaccines. E.g., the AlphaFold series revolutionized protein structure prediction.

3. Embodied intelligence support​

Efficient cloud-edge compute coordination provides full-stack support for embodied intelligence — covering massive data processing, high-fidelity simulation, model training, and edge real-time perception/decision in a closed loop.

Compute-network convergence is the core direction, evolving from "interconnect first, then network" toward a national integrated computing network. The three major telecom operators have begun interconnecting their own compute with dispersed social compute nationwide, promoting ubiquitous compute supply.

The domestic computing ecosystem keeps improving, with deeper government-industry-academia-research coordination. The China Intelligent Computing Industry Alliance, National Supercomputing Center in Tianjin, regional AI societies, industry associations, and service institutions jointly build exchange platforms — driving R&D, standard-setting, technology transfer, and talent cultivation for high-quality domestic computing development.

Conclusions & Outlook​

  1. Computing power is a core element of national strategic competitiveness — major countries are increasing infrastructure investment to seize the AI-era high ground.
  2. The domestic AI chip industry follows a distinctive path — via cluster breakthrough, HW/SW integration, and cost-performance, forming advantage in large-scale deployment.
  3. Computing architecture keeps evolving — heterogeneous computing, super-node servers, and long-context processing are key directions.
  4. Application scenarios keep expanding — from research paradigm shifts to synthetic biology and embodied intelligence, AI compute deeply empowers frontier fields.
  5. Computing infrastructure evolves toward compute-network convergence — future compute will be ubiquitous public infrastructure, on-demand like water and electricity.

References:

  • "2026 Global AI Computing Development Research Report" (China Intelligent Computing Industry Alliance et al.)
  • World Intelligence Expo 2026 (Tianjin, May 29, 2026)