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AI chip industry cycle review and trend analysis

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Inference Accelerator Market 2026: 60%–70% of the Accelerator Market, GPU vs ASIC Share Inverts, Five Schools Clash

· 5 min read
Industry Research Team

For the past three years, the entire AI hardware story was "training": who had the most H100s, who could connect a hundred thousand GPUs into a cluster. That race is essentially settled — NVIDIA won. But the next battlefield, "inference," is being fought under completely different rules: the measure is no longer peak FLOPS, but cost-per-token, latency, and power. In 2026, inference chips overtake training in scale for the first time, becoming the main battlefield of AI accelerators.


1. Inference Becomes the Main Battlefield: 80%–90% of Compute Spent on Inference​

Training a large model costs hundreds of millions of dollars — once. But once the model goes live, it must answer billions of queries day after day. A popular consumer model may need tens of thousands of accelerators running 7×24 to keep up with demand. Therefore:

  • Inference accounts for roughly 80%–90% of a model's lifecycle compute;
  • Inference chips will make up about 60%–70% of the ~$400B AI accelerator market in 2026, up from only ~40% in 2023;
  • Inference chip growth (estimated +52.7% YoY) significantly outpaces training chips (+28.4%); the share of inference-side compute demand exceeded training-side for the first time in 2026, reaching 54% (~$1010B).

The economics of inference are straightforward: training cost is amortized to near-zero, while inference cost becomes the entire bill. Every 1% cut in inference cost flows directly to profit — for a company whose inference traffic reaches hyperscale like OpenAI, the half of the bill is a number followed by a string of zeros.


2. Market Size: Structural Growth Inflection Point Has Arrived​

Market2026 SizeGrowthNotes
Global dedicated inference chips$412.7B+38.4%14.2 pct higher growth than training chips
China dedicated inference chips$118.6B (28.7% of global)+44.1%Strongest single market in APAC by growth
Global AI training/inference chips (incl. GPU/NPU)exceeds $1850B+40.2%GPU ~62%

China's domestic substitution is accelerating, with domestic inference chips reaching 34.6% of shipments, up 9.8 pct from 2025.


3. Technology-Axis Share Inverts: GPU Slows, ASIC Soars​

Axis2026 Shipment ShareTrend
GPU52.6%Still leads, but growth slows to 22.7%
ASIC custom chips41.3%Up sharply from 17.8% in 2022
FPGAStableSpecific low-latency scenarios

Thanks to ecosystem maturity, GPU remains the mainstay, but NPU/ASIC already holds a 1.8× advantage over same-generation GPUs in energy efficiency, driving rapid adoption at the edge and on-device. Shipments of inference-optimized ASICs are expected to reach 11.5 million units, with unit cost about 35% lower than GPUs.


4. Five Schools Clash​

SchoolRepresentative ProductsCore StrengthUse Cases
General-purpose GPUNVIDIA Rubin / B200 / H200Mature ecosystem, train+infer unifiedFrontier training + highly interactive inference
LPU (Language Processing Unit)Groq LPUUltra-low latency, deterministic throughputReal-time dialogue, high-concurrency inference
TPU (inference-specific)Google TPU 8i (Zebrafish)288GB HBM, 384MB on-chip SRAM, 19.2 Tb/s ICIGoogle's scaled inference
Custom ASICOpenAI Jalapeno, Microsoft Maia 200, Meta MTIAStrip generality tax for own models, ~50% lower cost/tokenHyperscaler's own workloads
Air-cooled inference cardIntel Crescent Island350W air-cooled, 480GB LPDDR5X, tokens/wattCost-sensitive mid/long-tail inference

OpenAI's Jalapeno, co-developed with Broadcom, aims to cut inference token cost by roughly 50% versus a general-purpose GPU stack — the fifth member to join the "custom inference chip club" (after Google TPU, Amazon Inferentia/Trainium, Microsoft Maia, and Meta MTIA).


5. Core Metric Shifts: cost-per-token and tokens/watt​

The fundamental difference between the inference race and the training race is the low switching cost:

  • Training requires a 100k-GPU cluster + NVLink + CUDA, with extremely high migration cost;
  • Inference is "embarrassingly parallel" at the endpoint level — no million-GPU cluster needed; a node that produces tokens fast and cheaply suffices, and is replaceable per endpoint.

This means NVIDIA's three moats (fastest silicon, NVLink scale-out, CUDA) are no longer absolute on the inference side. When the largest AI buyer (OpenAI) starts treating GPUs as "one of the options," the GPU premium begins to erode — pricing power relies on scarcity, and custom chips attack that scarcity from two directions at once: both reducing merchant-chip demand and giving buyers a credible external negotiation option.


6. Edge and On-Device Explosion: Long-Tail Signal​

Demand shows significant long-tail and fragmentation:

Scenario2026 Demand SizeGrowth
Cloud inference$198.2B (48%)+24.5% (slowing)
Edge inference$126.5B (30.7%)+52.3%
On-device inference$88.0B (21.3%)+68.9%
Autonomous-driving inference$67.3B+58.2%
Industrial QA / robotics inference$42.1B+63.7%

The latency sensitivity and power constraints of inference workloads are reshaping chip architecture design priorities — which also explains why "air-cooled, large-memory" solutions like Crescent Island can find a niche.

References​


This article is compiled from publicly available 2026 market research, brokerage reports, and industry analysis. Market sizes and shares are third-party estimates with inconsistent methodologies and are for reference only.

Domestic GPU IPO Wave: The "Four Little Dragons" Assemble on Capital Markets, Moore Threads MTT S5000 Benchmarks Against H100

· 5 min read
Industry Research Team

From December 2025 to July 2026 — just half a year — at least 6 AI chip companies have listed or are about to list on capital markets. Together with already-listed Cambricon, Hygon, and Iluvatar, the domestic GPU corps' total market cap is approaching ¥2 trillion. This marks the critical climb from domestic GPUs being "usable" to "useful."

1. The "Four Little Dragons" assemble on capital markets​

CompanyListing statusRaise / issue priceSponsor
Moore ThreadsListed (STAR Market sh688795, 2025-12-05)Issue price ¥114.28, raised ¥8BCITIC Securities
MetaXIPO accepted (2026-06-30)¥3.904B (total investment ¥5B)Huatai United
EnflamePassed review (2026-06-15)¥6B—
BirenHKEX / sprinting——

Already-listed camp: Cambricon (sh688256, STAR Market 2020-07-20), Hygon, Iluvatar (HKEX). Moore Threads turned a book profit of ¥29.35M in Q1; MetaX narrowed losses 57.7% and gave a 2026 breakeven timeline.

2. Moore Threads MTT S5000: benchmarking against H100​

Moore Threads announced its flagship AI train+inference GPU MTT S5000 successfully completed full-pipeline adaptation validation of Zhipu's new-generation large model GLM-5 — measured performance "breaks the domestic compute ceiling":

MetricMTT S5000
Architecture4th-gen "Pinghu" architecture
FP8 compute1 PFLOPS (1,000 TFLOPS)
Memory bandwidth1.6 TB/s
PositioningFull-function train+inference GPU, benchmarks against NVIDIA H100
ProductionMass-produced; clusters online supporting trillion-parameter training

Deployment validation: jointly completed full-pipeline training of embodied-brain model RoboBrain 2.5 with BAAI; partnered with SiliconFlow for high-performance DeepSeek-V3 inference, single-card speed near international top products. IPO funds go to three directions: next-gen AI train+inference chip, next-gen graphics chip, next-gen AI SoC chip.

WAIC 2026 new progress: Moore Threads showcased the MTT C256 SuperNode (first-of-its-kind single-layer Scale-up 256-card full interconnect, sub-microsecond latency) and three AI-factory solutions — "model training factory / token production factory / agent production factory"; the company pre-announced H1 2026 revenue of ¥1.65B-1.75B, up 135%-149% YoY.

3. Cambricon: dual flagships MLU590/690​

ChipProcessComputeMemoryCustomer / status
MLU590 (思元590)7nm ChipletINT8 512 TOPS / FP16 345 TFLOPS96 GB HBM2eByteDance inference mainstay, ~80% of A100 overall, mass shipments early 2026
MLU690 (思元690)5nm-class (SMIC N+2)FP16 700+ TFLOPS / INT8 2800+ TOPS196 GB HBM3 (3.35 TB/s)Dual-die packaging, MLU-Link 890 Gbps; ~70% of H100 (80-90% pure inference); ByteDance largest customer, mass production early 2026

Cambricon is the only domestic AI chip vendor with a "unified edge-cloud architecture" — one MLU instruction set spans 思元 220 (edge) → 370 (border) → 590/690 (cloud), with one NeuWare toolchain across compute tiers.

Capital and performance double explosion: Cambricon's total market cap exceeded ¥1 trillion on June 30, 2026, becoming the STAR Market's first "trillion-yuan stock," up 75%+ YTD. On performance, Q1 2026 revenue ¥2.885B (+160% YoY), deducted net profit ¥934M; full-year 2025 revenue ¥6.497B (+453% YoY), net profit attributable to parent ¥2.059B, ending long-term losses. ByteDance has cumulatively deployed over 100k 思元 590/690, its largest customer.

4. DeepSeek-V4 effect: changing the expectation coordinate system​

On April 24, 2026, DeepSeek released the trillion-parameter flagship DeepSeek-V4. Unlike a year earlier when V3's launch sparked debate over "can domestic chips even run large models," this time multiple domestic chips — Huawei Ascend, Cambricon, Hygon, MetaX, Moore Threads, Kunlun, T-Head, Iluvatar — completed adaptation on launch day.

The evaluation coordinate system is shifting: from "what percentage of NVIDIA's same-generation product performance" to "can it carry the real workloads of top-tier large models."

Industry interpretation​

  1. Capital ammunition in place: dense IPOs provide ample funding for domestic GPU R&D iteration and capacity expansion, moving from "technology breakthrough" to "commercial virtuous cycle."
  2. Train+inference becomes the mainstream route: Moore Threads takes the full-function GPU route (graphics+AI+general compute), differentiating from Huawei Ascend's "AI-focused."
  3. Software ecosystem is the decider: Day-0 adaptation and the maturity of unified software stacks (MUSA / NeuWare / MXMACA) are replacing raw peak compute as the core yardstick of domestic GPU "usability."

References​


This article continuously tracks the domestic GPU listing process and product iteration.

Huawei Ascend 950 Series Capacity & Orders Deep Dive: 950PR Monthly Capacity Jumps 10×, ByteDance Locks In 350k Units for $5.6B

· 4 min read
Industry Research Team

The Ascend 950 series (950PR inference / 950DT training) has become the core supply of domestic AI compute. Per multiple brokerages and industry research, 950 series capacity is 100% booked with scarce spot supply; the full-year 1.2M-unit target is "100% certain," with expectations of an upward revision to 1.5M. This article summarizes capacity and order data as of July 2026.

1. Capacity pace: ~10× MoM jump in June​

Time950PR monthly capacityNotes
May 202650k-60k unitsNear full production
June 2026500k-600k units~10× MoM; SMIC, Hua Hong tier-1 suppliers on overtime
Q3 2026 (est.)700k-800k unitsPer month
Full-year 2026 target1.2M unitsUpward revision to 1.5M expected

Supply chain delivery is tight: high-speed backplanes and liquid-cooling connectors' lead time stretched from 2 weeks to 6-8 weeks; orders are booked into 2027.

2. Order structure: top cloud providers + operators + overseas​

CustomerLocked volumeAmount / Notes
ByteDance350k 950PR$5.6B, concentrated delivery from Q3 2026
Tencent / Alibaba / Baidu~250k 950PR + 150k 950DTCombined ~400k units
Three major operators200k+ unitsCentralized procurement, for intelligent compute centers and AI private networks
OverseasSouth Korea 2,000 units, Malaysia 3,000 servers, Russia ten-thousand-card clusterFrom pilot to commercial

3. Shipment forecast: firmly #1 domestic​

Per CCA (Kezhi) Consulting estimates:

Metric20252026 (forecast)
Huawei Ascend total shipments812k cards1.026M cards
Of which 950PR—~800k units
Of which 950DT—~100k-200k units

Huawei has completed the product transition from the 910 series to the 950 series. The internet industry has become Ascend's largest application market; competitive advantage is extending from single-hardware performance to software ecosystem and system capabilities.

4. Going overseas: formal South Korea entry in Q4​

Per Korean media ETNews, Huawei plans Q4 2026 to formally enter the South Korean market with the Ascend series and Atlas 950 SuperPod:

  • Local distributor agreements signed; two channel partners including SK Shieldus selected
  • Main products: 950PR (mass-produced and delivered since April) and 950DT (launched Q4)
  • Official line: 950PR inference performance is 2.87× that of H20, priced at about 1/4 of it

5. WAIC 2026: 1024-card live debut confirmed​

At WAIC 2026 (July 17-20, Shanghai), Huawei's Atlas 950 SuperPoD live hardware made its first public appearance — a 16 compute-cabinet, 1,024 Ascend-card scale — and won the conference's top honor, the SAIL Award:

  • Core metrics: total compute 1 EFLOPS FP8 / 2 EFLOPS FP4, 256 TB globally unified memory addressing, Lingqu 2.0 interconnect, 3 μs ultra-low RTT latency
  • Full configuration: 128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡ footprint, carrying 8,192 Ascend 950DT, planned Q4 2026 launch
  • Commercial foundation: previous-gen 384 SuperNode has cumulatively shipped 750+ units, deployed in 20+ industries
  • Software ecosystem: CANN fully open-sourced end of 2025; community incubated 67 projects, 12.44M+ lines of code, 3,500+ monthly active developers

WAIC's debut confirmed the 950 series' "SuperNode-first" product logic: beyond single-card compute, system-level effective compute (interconnect bandwidth + unified memory + low latency) is the key dimension for domestic compute to benchmark against international flagships.

Ascend roadmap recap​

ProductPositioningKey metrics (official roadmap)
950PRInference1 PFLOPS (FP8) / 2 PFLOPS (FP4), 2 TB/s interconnect
950DTTrainingSuperNode core, launched Q4
960Train/inference2 PFLOPS (FP8) / 4 PFLOPS
970Next-genIn planning

Industry interpretation​

  1. Domestic substitution moves from inference to training: 950PR (inference) ramps first, 950DT (training) follows in Q4, combined with the Atlas 950 SuperPoD ten-thousand-card interconnect — domestic compute now has the complete "training substitution" puzzle for the first time.
  2. Capacity is the biggest variable: order certainty is extremely high, but SMIC/Hua Hong advanced-process capacity, HBM supply, and advanced packaging remain ramp bottlenecks — the root of "scarce spot supply."
  3. Going overseas opens a second growth curve: bulk procurement from South Korea, Malaysia, Russia, and Latin America marks domestic compute's shift from "internal circulation" to "external circulation."

References​


Data in this article is based on official and major brokerage research; capacity/orders are dynamic figures and will be continuously updated.

2026 H1 AI Chip Industry Review: Blackwell Ultra, the Domestic Big Three, and the Inference Era

· 11 min read
Industry Research Team

In the first half of 2026, the AI chip industry underwent a historic turning point — the center of gravity shifted from the "training race" to "inference efficiency," domestic chip market share broke 40% for the first time, NVIDIA built higher barriers with Blackwell Ultra, and the inference-specific chip track bloomed in diversity.


I. Compute Doubles Again: NVIDIA Blackwell Ultra Launch (June 1)​

On June 1, 2026, NVIDIA CEO Jensen Huang unveiled the new-generation AI chip Blackwell Ultra at Computex 2026 (Taipei), setting a new starting line for the AI infrastructure race over the next two years.

Key Specs​

MetricBlackwell UltraB200Improvement
FP8 compute20 petaFLOPS~10 petaFLOPS100%
ArchitectureBlackwell UltraBlackwellUpgrade
Expected delivery2027 Q12026 Q1—
PositioningHyperscale training + inferenceTraining + inferenceFlagship

Industry Significance​

  1. Direct impact of doubled compute: 20 petaFLOPS FP8 means training time for hundred-billion-parameter models drops sharply; trillion-parameter model training moves from "scientific experiment" to "engineering routine"
  2. System-level balance: Blackwell Ultra is not just a chip but a system-level engineering breakthrough across NVLink, HBM, cooling, and power delivery
  3. Roadmap certainty: The Q1 2027 delivery timeline lets cloud vendors and AI labs plan infrastructure budgets 18 months ahead

Challenges​

  • Energy crisis: Doubled performance comes with sharply higher power; datacenter power and cooling design face extreme challenges
  • Accessibility: Top-tier compute goes first to top cloud vendors; how smaller developers and research institutes reach compute at reasonable cost via cloud services
  • Software stack adaptation: New hardware needs matching CUDA versions and framework support; software ecosystem maturity becomes the key bottleneck for compute conversion

II. Domestic AI Chips: The Tipping Point from "Usable" to "Good"​

On June 16, 2026, Xinchuang World published "2026 China Domestic AI Chip Vendor Capability Quadrant", clearly outlining the overall domestic landscape.

2.1 Capability Quadrant Ranking​

QuadrantRepresentative Vendors
Leader quadrantHuawei Ascend, Hygon, Cambricon, Alibaba T-Head, Moore Threads
Visionary quadrantBaidu Kunlunxin, Biren, Enflame, Iluvatar, HardyVision
Contender quadrantTSINGMICRO, Black Sesame, SemiDrive, Lisuan, Houmo
Challenger quadrantDenglin, Zhicun, VeriSilicon, Rockchip, Intellifusion

2.2 Huawei Ascend: The Anchor of Domestic Compute​

Market Position​

  • In 2025, Ascend series shipped 812,000 units, capturing 49% of the domestic AI accelerator card share, firmly No.1 domestically
  • Ascend 950PR single-card FP8 compute reaches 1P (PetaFLOPS), FP4 compute reaches 2P
  • Inference performance is about 2.87x that of NVIDIA H20, priced at only 72,000-75,000 RMB, a significant price/performance advantage

Full-Stack Advantage​

Huawei's "device-network-cloud-chip" integrated strategy is Ascend's core moat:

  • Chip design: Da Vinci 3.0 architecture iterating continuously
  • OS: HarmonyOS/Euler OS deeply optimized
  • Networking: Euler network protocol stack
  • Cloud: Huawei Cloud ModelArts platform seamlessly integrated

Latest Progress​

  • On June 5, 2026, Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, completed full-parameter post-training of a 1.6-trillion-parameter DeepSeek V4 Pro model on an Ascend 910C cluster
  • This is the first time domestic AI chips completed trillion-parameter-level model training, marking "domestic substitution" moving from inference to training

2.3 Cambricon: The First Profitable Domestic AI Chip Benchmark​

Performance Explosion​

MetricFull-year 20252026 Q1YoY Growth
Revenue6.497B RMB2.885B RMB+453% / +160%
Net profit2.059B RMB (first annual profit)1.013B RMB— / +185%

Core Product: Siyuan 590​

  • In DeepSeek R1 inference scenarios, TPS reaches 942, about 50% higher than H20
  • Years of joint optimization with ByteDance; strongest short-term cloud inference deployment capability
  • Of 2.885B RMB Q1 2026 revenue, Siyuan 590 contributed over 70%

Potential Risks​

Absent from the 2nd 2026 "Safe and Reliable Evaluation Results Announcement"; the reason is unclear and will affect its domestic government/enterprise market performance.

2.4 TSINGMICRO: The "Third Route" of Reconfigurable Chips​

Technical Route​

TSINGMICRO adopts a reconfigurable dataflow architecture同源 with Groq LPU, finding a balance between GPU generality and ASIC extreme efficiency.

MetricTSINGMICRO TX81Traditional GPUAdvantage
Inference costBaseline+100%Reduced 50%
Energy efficiencyBaselineBaseline3x improvement
ArchitectureReconfigurable dataflowSIMT/SIMDBetter for inference

Deployment Progress​

  • Cumulative shipments of reconfigurable chips exceed 30 million units
  • Scaled deployment in a dozen-plus thousand-card-scale intelligent computing centers nationwide
  • Has begun A-share IPO tutoring; likely to become the "first reconfigurable chip stock"

III. The Inference Chip Track: Core Signal of the Industry Shift​

On June 4, 2026, TrendForce published a deep report "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten," pointing out that the compute competition center of gravity is shifting from training to inference.

3.1 Why Now?​

Cost Structure Changed​

  • Training is a one-time cost: Once a model is trained, marginal cost approaches zero
  • Inference is a recurring cost: Every API call, every generated token represents compute consumption and gross-margin pressure
  • Per-unit inference cost and energy efficiency directly affect gross margin and scale-expansion capability

Model Compression Tech Matured​

  • 1.58-bit quantization and weight pruning let models maintain inference accuracy at extremely low memory footprint
  • MoE (Mixture of Experts) architecture activates only a few expert sub-networks per inference via "partial wake-up," greatly reducing actual computation
  • The rise of slimmed models provides commercial viability for hard-wired inference chips

3.2 NVIDIA's $20B Bet: Acquiring Groq (December 2025)​

On December 24, 2025, NVIDIA acquired Groq's inference technology license and core team for $20 billion, one of NVIDIA's largest M&A/tech acquisitions ever.

Strategic intent:

  1. Fill the inference gap: NVIDIA GPU is unshakable in training, but inference efficiency was never its strongest suit
  2. Counter specialized inference chips: Cerebras, Taalas, SambaNova and other startups are eroding the inference market
  3. Position for Agentic AI: Agentic AI needs extremely low-latency, high-throughput inference

3.3 Taalas HC1: Proof of Concept for Hard-Wired Inference​

On February 20, 2026, Canadian AI chip startup Taalas launched inference chip Taalas HC1, directly etching Meta's open-source AI model Llama 3.1 8B into the chip.

Key Metrics​

MetricTaalas HC1NVIDIA B200 (throughput optimized)Advantage
Inference rate16,960 tokens/s/userBaseline~4-5x
Cost per million tokens0.75 cents3.79 centsReduced 80%
Power~250W~700WReduced 64%
ProcessTSMC N6TSMC 4nmMore mature
HBM❌ Not used✅ HBM3eLower cost

Technical Principle​

Taalas HC1 uses an aggressive Computing-in-Memory (CIM) implementation:

  • Model weights directly固化 in Mask ROM (fully hardware-defined)
  • On-chip SRAM handles dynamic data (KV cache and LoRA fine-tuning weights)
  • Only 2 mask layers need modification to produce a dedicated chip for another AI model; turning an AI model into a physical chip takes only 2 months

Limitations​

  • Lack of flexibility: Hard-wiring cannot cope with rapidly iterating model updates
  • Ecosystem barrier: The current cloud market still relies on general-purpose platforms; customers may prefer flexible solutions that upgrade with models
  • NRE cost: High one-time engineering cost, requiring sufficient deployment scale to amortize

3.4 Cerebras: The IPO Path of Wafer-Scale Integration​

On May 14, 2026, Cerebras Systems officially listed on NASDAQ, becoming the first wafer-scale AI chip company to go public.

Core Technology: Wafer-Scale Integration (WSI)​

  • WSE-3 (third-gen wafer-scale engine): An entire 12-inch wafer as a single chip
  • 44GB on-chip SRAM: No external HBM, eliminating the memory bandwidth bottleneck
  • 21 PB/s bandwidth: On-chip communication bandwidth, thousands of times that of GPUs
  • Partnership with OpenAI: Signed a 3-year, 750MW, $20B+ compute cooperation agreement

IPO Significance​

Cerebras's listing marks the maturation of the inference-specific chip track:

  1. Capital markets begin pricing such companies
  2. Proves "non-GPU" technical routes have commercial viability
  3. Provides valuation references for other inference chip startups (Groq, SambaNova, Taalas, etc.)

3.5 Inference Chip Landscape: Multiple Technical Routes Coexist​

CompanyTechnical RouteCore AdvantageRepresentative Product
TaalasHard-wired (Mask ROM)Extreme inference efficiency, low costHC1
CerebrasWafer-scale integration (WSI)Ultra-high bandwidth, large-model inferenceWSE-3
GroqSRAM-first architectureDeterministic latency, high throughputLPU (acquired by NVIDIA)
d-MatrixDigital in-memory compute (DIMC)More flexible than hard-wiringCorsair
EtchedHard-wired TransformerWorks for all Transformer modelsSohu
Axelera AIDigital in-memory compute (D-IMC) + RISC-VHigh energy efficiencyMetis AIPU

TrendForce predicts:

  • General-purpose GPUs still dominate training and multi-model environments
  • But in mature, predictable scenarios, general-purpose GPU profit margins will be compressed
  • The industry shifts from general compute monopoly to a dual-track structure of general + specialized coexistence

IV. Overall Domestic AI Chip Landscape in H1 2026​

4.1 Industry Enters Scale-Up Phase​

Metric20252026 Q1Trend
Domestic AI accelerator shipments1.65M units (41% share)—Rising
Total China AI accelerator shipments~4M units——
Hygon revenue growth—Doubled↑
Cambricon revenue growth—+160%↑
Moore Threads revenue growth—Doubled↑

Leading vendors collectively entered the revenue realization channel, moving from "technical validation" to "scale commercialization."

Trend 1: Capitalization Wave Reshapes the Landscape​

  • Late 2025 to early 2026: Moore Threads, Iluvatar listed on the STAR Market
  • Biren listed on the Hong Kong stock exchange
  • Enflame STAR Market IPO accepted
  • Kunlunxin, T-Head initiated listing processes
  • TSINGMICRO, HardyVision and others advancing IPOs

Capitalization brings dual effects:

  • ✅ Positive: Supports R&D and ecosystem building
  • ⚠️ Negative: Valuation bubbles and revenue realization pressure

Trend 2: Capacity Becomes the Biggest Constraint Variable​

The contradiction between explosive domestic AI chip demand and limited advanced-process capacity is sharpening:

VendorAdvanced-process capacity needActually obtained
Huawei Ascend15K wafers/month (7nm-class)Priority guaranteed
SMIC total capacity~20K wafers/month (7nm-class)—
Other vendors~5K wafers/month combinedExtremely tight

Whether stable wafer capacity can be secured directly determines vendor survival. Cambricon's 75.4% inventory-to-revenue ratio is essentially a lock on capacity.

Trend 3: Competition Shifts from "Usable" to "Good"​

Early competition focused on "can it run the model"; now it's about "runtime efficiency, deployment cost":

Dimension"Usable" era"Good" era
Hardware performanceCan it run the modelRuntime efficiency, energy efficiency
Software stackBasic adaptationMaturity, framework breadth
EcosystemExistenceDeveloper community activity
Deployment costInsensitiveCore competitive factor

V. H2 2026 Outlook​

5.1 Upcoming Key Events​

TimeEventImpact
2026 Q3NVIDIA Rubin architecture details revealedNext-gen flagship specs unveiled
2026 Q3Huawei Ascend 950PR/950DT formally launchedNew benchmark for domestic inference chips
2026 Q4AMD MI350X scaled deliveryNVIDIA Blackwell competitor
2026 Q4Cambricon Siyuan 690 launch (est.)New-gen training chip
2027 Q1NVIDIA Blackwell Ultra deliveryNew compute benchmark lands

5.2 Key Competitive Factors Over the Next Three Years​

  1. Wafer capacity access: Advanced-process capacity is a scarce resource; vendors tied to SMIC and TSMC have inherent advantages
  2. Capital operation efficiency: The IPO window is limited; raising enough capital on the market determines R&D sustainability
  3. Software ecosystem depth: Hardware performance is only the entry ticket; software stack maturity, framework adaptation breadth, and developer community activity are the core moat

VI. Conclusion: A Diverse Ecosystem Will Eventually Form​

In H1 2026, the AI chip industry is undergoing a historic transition from "one dominant player" to "pluralistic coexistence."

  • NVIDIA builds higher training barriers with Blackwell Ultra while laying out inference efficiency via the Groq acquisition
  • Huawei Ascend holds the domestic compute baseline with full-stack capability; 950PR begins to surpass H20 in inference
  • Cambricon proves the commercial viability of domestic AI chips by turning profitable first; Siyuan 590 surpasses international rivals in specific scenarios
  • Cerebras, Taalas and other inference-specific chip companies opened a "non-GPU" third route
  • TSINGMICRO's reconfigurable architecture provides a diversified technical route choice for China's AI chips

Over the next three years, the domestic AI chip endgame will form a pluralistic ecosystem where GPU, ASIC, and reconfigurable computing three technical routes coexist, with cloud and edge developing in coordination. "Domestic substitution" is no longer a slogan, but an industrial reality happening now.


Data sources:

  • Xinchuang World "2026 China Domestic AI Chip Vendor Capability Quadrant" (2026-06-16)
  • TrendForce "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten" (2026-06-04)
  • RayByte "Compute Doubles! NVIDIA Blackwell Ultra Chip Launched" (2026-06-02)
  • Official financial reports and announcements of each company

Related reading:


2026 Global AI Computing Report & Ten Major Computing Industry Trends Released

· 7 min read
Industry Research Team

On May 29, 2026, during the World Intelligence Expo 2026 in Tianjin, the China Intelligent Computing Industry Alliance, National Supercomputing Center in Tianjin, Tianjin Artificial Intelligence Society, Shenzhen Artificial Intelligence Industry Association,ZDNET, and ZDNET ThinkTank jointly released the "2026 Global AI Computing Development Research Report."

The report analyzes the current state and future trends of the global AI computing industry, revealing that the sector has entered a new stage of "intelligence-driven, system-reconstruction."

Core Viewpoints​

1. Computing power becomes a national strategic element​

The global computing industry is entering a new stage of "intelligence-driven, system-reconstruction." With the rise of the "token economy," computing power has become a key foundational element supporting national technological breakthroughs, industrial competition, and strategic positioning.

Computing is evolving from traditional IT support into a strategic bedrock driving scientific innovation and the industrial revolution.

2. AI computing development covers the full chain​

AI computing development must upgrade the full chain of chip, system, and compute cluster, while matching the differentiated computing needs of model training, inference, and data preparation.

  • Training: pre-training of super-large models needs ten-thousand-card-scale compute
  • Inference: super-large models need thousand-card-scale compute
  • Data preparation: needs tens to hundreds of cards

Compute demand at both training and inference ends will keep growing.

3. Domestic AI chip industry's distinctive path​

The domestic AI chip industry follows a route of "autonomy + cluster breakthrough + hardware-software integration + cost-performance advantage," distinct from the foreign pursuit of absolute single-chip compute — better suited to large-scale deployment.

4. Energy challenges for computing centers and solutions​

Computing centers have become the fastest-growing source of global electricity demand. The future requires a diversified energy supply of "short-term wind-solar-storage integration, mid-term nuclear, long-term hydrogen."

Meanwhile, space computing will become a new direction to solve ground-based computing bottlenecks.

5. Compute-network convergence as a core direction​

Future computing will move toward "compute-network convergence," making compute as on-demand as water and electricity — a core part of the national modern infrastructure system.

The computing network has been included in the national "15th Five-Year Plan" major engineering projects, ranked alongside public infrastructure such as hydro power.

Key Data​

Compute performance evolution​

MetricEvolution trend
Chip computefrom TFLOPS scale up to tens of PFLOPS
System formfrom single 8-card machine to thousand-card super-node architecture
Cluster scalefrom thousand-card clusters to hundreds-of-thousands-card clusters
Cluster powerfrom kilowatt to gigawatt scale

Global computing center capacity & energy forecast​

  • Global computing center total capacity: expected to grow from 102GW (2026) to 220GW (2030)

    • AI load capacity from 62GW to 156GW, share rising to 71%
  • U.S. computing center annual electricity: expected to grow from 292TWh to 606TWh, share of national demand rising to 11%

  • China computing center total capacity: ~60GW by 2030, AI load share rising to 48%

  • Global computing center electricity: per IEA base scenario, from ~415TWh (2024) to ~945TWh (2030), ~15% CAGR

Embodied intelligence compute support data​

  • Cloud compute: can generate PB-scale interaction data daily; large-model training cycle shortened from months to weeks
  • Edge compute: tens-to-hundreds of TOPS enables 10–50ms low-latency real-time perception & decision

Industry Trend Analysis​

1. Heterogeneous architecture upgrade​

From traditional CPU+GPU to a new GPU+LPU+CPU+DPU heterogeneous inference architecture.

CPU plays the core role of task scheduling, data pre-processing, serial tasks, and system interconnection in heterogeneous architectures. In 2010, "Tianhe-1A" pioneered large-scale CPU+GPU deployment, leading the global intelligent-computing underlying architecture direction.

2. Clear scale-up / scale-out paths​

  • Scale Up: pursue extreme performance by raising single-node hardware config
  • Scale Out: add nodes for load sharing and high availability

Together they form the core support of computing system capability.

3. Super-node servers become mainstream​

With ultra-high interconnect bandwidth and low communication latency, they shorten model training cycles.

Representative products:

  • Huawei Ascend 384 super-node
  • Sugon scaleX640 super-node
  • Alibaba Cloud Panjiu AL128 super-node
  • Inspur YuanNao SD200
  • Kunlunxin super-node solution

4. Long-context processing optimization​

Through Compressed Sparse Attention (CSA), Heavy-Compressed Attention (HCA) and sliding-window mechanisms, build a "coarse + fine, sparse + dense" long-context modeling system to improve compute efficiency.

Representative application: DeepSeek-V4 attention architecture design.

AI chips​

International vendors:

  • NVIDIA: leads high-end training/inference with Blackwell and Rubin architectures
    • GTC 2026 Taipei (June 1) major releases:
      • Vera Rubin platform in full mass production: NVL72 rack system, agent throughput 10x over Grace Blackwell
      • Vera CPU released: 88-core Olympus in-house Armv9.2, LPDDR5X 1.5TB, 1.2 TB/s, world's first CPU with native FP8
      • RTX Spark AI PC chip: co-developed with MediaTek and Microsoft (codename N1X), Blackwell GPU 1 PFLOP, 128GB unified memory, TSMC 3nm
      • Nemotron 3 Ultra open model: SSM+MoE hybrid, 5x inference speed, 30% lower cost
    • Expanding advantage via CUDA ecosystem
  • Google: deepens vertical HW/SW integration via in-house TPU
  • AWS: Trainium (training) + Inferentia (inference) for cost-effective cloud compute

Domestic vendors: a product matrix represented by Huawei Ascend 910C, Kunlunxin P800, Moore Threads MTT S5000, MetaX XiYun C600.

In 2026 Huawei proposed the "Tao (τ) Law," aiming to systematically reduce the time constant and raise transistor density via logic folding, driving domestic chip evolution.

AI workstations​

  • Form factors: tower, mobile, mini — for different deployment scenarios
  • Compute tiers: entry, professional, enterprise — covering personal dev to enterprise deployment

AI servers​

  • By function: training AI servers and inference AI servers
  • By deployment: cloud AI servers and edge AI servers

With high compute output, high memory bandwidth, and high-speed interconnect, suited to large-scale parallel tasks.

AI computing centers​

  • Trending toward "high AI share, high power density, high electricity consumption"
  • Ultra-large AI computing centers become the construction focus
  • Energy supply moving toward diversified clean sources

Space computing is a new direction, leveraging space's continuous sunlight, extreme cold/vacuum, and interference-free environment to solve ground centers' energy, cooling, and interconnect bottlenecks. Starcloud and Guoxing Weiyu have begun exploration.

1. Scientific research paradigm shift​

The "dry-wet closed loop" research paradigm becomes mainstream, forming a loop between AI-driven "dry experiments" and automated "wet experiments" via data feedback — shifting science from experience-driven to model-driven.

2. Synthetic biology empowerment​

AI's multi-task learning and unknown-space exploration can decode biology's complex "sequence–structure–function" mapping, enabling breakthroughs in protein synthesis, gene editing, and nucleic-acid vaccines. E.g., the AlphaFold series revolutionized protein structure prediction.

3. Embodied intelligence support​

Efficient cloud-edge compute coordination provides full-stack support for embodied intelligence — covering massive data processing, high-fidelity simulation, model training, and edge real-time perception/decision in a closed loop.

Compute-network convergence is the core direction, evolving from "interconnect first, then network" toward a national integrated computing network. The three major telecom operators have begun interconnecting their own compute with dispersed social compute nationwide, promoting ubiquitous compute supply.

The domestic computing ecosystem keeps improving, with deeper government-industry-academia-research coordination. The China Intelligent Computing Industry Alliance, National Supercomputing Center in Tianjin, regional AI societies, industry associations, and service institutions jointly build exchange platforms — driving R&D, standard-setting, technology transfer, and talent cultivation for high-quality domestic computing development.

Conclusions & Outlook​

  1. Computing power is a core element of national strategic competitiveness — major countries are increasing infrastructure investment to seize the AI-era high ground.
  2. The domestic AI chip industry follows a distinctive path — via cluster breakthrough, HW/SW integration, and cost-performance, forming advantage in large-scale deployment.
  3. Computing architecture keeps evolving — heterogeneous computing, super-node servers, and long-context processing are key directions.
  4. Application scenarios keep expanding — from research paradigm shifts to synthetic biology and embodied intelligence, AI compute deeply empowers frontier fields.
  5. Computing infrastructure evolves toward compute-network convergence — future compute will be ubiquitous public infrastructure, on-demand like water and electricity.

References:

  • "2026 Global AI Computing Development Research Report" (China Intelligent Computing Industry Alliance et al.)
  • World Intelligence Expo 2026 (Tianjin, May 29, 2026)