48 posts tagged with "NVIDIA"

在旧金山举行的微软 Windows AI 与 Surface 活动上，NVIDIA 一手开启 RTX Spark 笔记本预订，一手预览 DGX Station for Windows——从 1 PFLOP FP4 的笔记本到 20 PFLOPS FP4 的桌面工作站，AI 算力正在从数据中心一路铺到办公桌。

RTX Spark 笔记本正式开订​

在微软于旧金山举行的 Windows AI 与 Surface 活动上，NVIDIA 宣布 RTX Spark 笔记本正式开启预订，首批产品将于 10 月 16 日（周五）发货；紧凑型桌面产品则计划在 11 月跟进上市。

OEM 阵容覆盖了几乎所有主流 PC 品牌：Acer、ASUS、Dell、HP、Lenovo、Microsoft（Surface Laptop Ultra）、MSI、Gigabyte 全部在列。从发布即有如此完整的品牌背书来看，RTX Spark 显然不是一款演示性产品，而是要成长为一个完整的终端新品类。

Blackwell RTX + Grace CPU：数据中心架构下沉终端​

RTX Spark 的硬件方案可以概括为"把 Grace Blackwell 的思路压缩进 PC"：

• GPU：基于 Blackwell 架构的 RTX GPU，最高 6144 个 CUDA 核心；
• CPU：最多 20 核的 Grace CPU；
• 互联：CPU 与 GPU 之间提供 600 GB/s 高速链路；
• 算力：最高 1 PFLOP FP4；
• 内存：最高 128GB 统一内存，CPU 与 GPU 共享同一内存池；
• 软件：运行完整 CUDA 栈。

其中"统一内存 + 完整 CUDA 栈"是两个关键点：前者决定了本地能装下多大的模型，后者决定了云端训练的代码可以低成本迁移到本地调试，开发者不必为桌面场景另学一套工具链。

DGX Station for Windows 首次预览​

如果说 RTX Spark 面向个人开发者，那么同场预览的 DGX Station for Windows 则瞄准了更高一层的需求。它基于 GB300 Grace Blackwell Ultra Desktop Superchip，拥有 748GB 一致性内存，算力最高可达 20 PFLOPS FP4，目标是让用户在本地运行约 1 万亿参数的模型。

对 Linux 生态的兼容也给出了务实答案：Linux 工具链可以通过 WSL（Windows Subsystem for Linux）访问。DGX Station for Windows 将于 Q4 上市，由 ASUS、Dell、HP、Lenovo 四家推出。

Surface Laptop Ultra 与内存挤压隐忧​

作为活动的另一主角，Surface Laptop Ultra 已于 10 月 7 日开启预订，最高配备 128GB 统一内存——这个容量已经接近入门级推理服务器的水平。

但 DIGITIMES 提出了一个不容忽视的问题：AI PC 的内存供给正在被服务器需求挤压。在内存厂商的优先级排序中，服务器 DRAM 需求被放在首位，AI PC 依赖的 LPDDR5X 供给承压。在存储供应紧张的背景下，128GB 统一内存的 AI PC 能否稳定供货，本身就是一个变数。

从云端到桌面的算力分层​

把 NVIDIA 目前的桌面产品线摆在一起，可以清晰看到一条算力分层路线：

产品	形态	关键规格	定位
DGX Spark	桌面 AI 超算	64GB 统一内存、1 PFLOP FP4	4,999 美元，个人与小团队原型验证
RTX Spark 笔记本	笔记本	最高 6144 CUDA 核心 + 最多 20 核 Grace CPU、最高 128GB 统一内存	随身开发与调试
DGX Station for Windows	桌面工作站	GB300 Grace Blackwell Ultra Desktop Superchip、748GB 一致性内存、最高 20 PFLOPS FP4	本地运行约 1 万亿参数模型

这条路线的逻辑是：云端负责大规模训练与生产推理，桌面负责原型验证、微调与敏感数据场景，笔记本负责日常开发与演示。当模型越做越大、数据合规要求越来越严，"把算力放在身边"的价值正在上升。

Windows CUDA 原生化与 WSL 的务实路线​

过去十几年，CUDA 的主战场在 Linux 服务器上，Windows 开发者在工具链上长期处于跟随位置。RTX Spark 与 DGX Station for Windows 意味着完整 CUDA 栈第一次以原生姿态大规模进入 Windows 桌面场景。

而 WSL 桥接 Linux 工具链的安排，则是一种典型的务实路线：既照顾 Windows 用户的使用习惯，又不要求现有 Linux 工作流推倒重来。对于在 Windows 环境中做模型开发和内部工具的企业开发者来说，迁移成本被明显降低；对 NVIDIA 而言，这等于把整个 CUDA 开发者生态延伸到了全球存量最大的桌面操作系统上。

小结​

RTX Spark 笔记本开订与 DGX Station for Windows 预览，标志着 NVIDIA 把 AI 算力的故事延伸到了最后一米：从数据中心，到桌面工作站，再到背包里的笔记本。1 PFLOP FP4 到 20 PFLOPS FP4 的分层算力、128GB 到 748GB 的统一内存、WSL 桥接的 Linux 工具链，共同构成了一条完整的桌面 AI 开发路径。剩下的悬念有两个：一是 LPDDR5X 供给紧张会不会卡住 AI PC 的出货节奏，二是 11 月的紧凑型桌面和 Q4 上市的 DGX Station 能否如期落地。

2026年10月4日，NVIDIA正式发布N1X PC处理器，直接切入Intel与AMD长期分割的PC处理器市场。消息公布当日，Intel与AMD股价双双下跌4.2%——资本市场用最直接的方式表达了对这场"降维打击"的担忧。

发布当日：资本市场的剧烈反应​

N1X发布当天，Intel与AMD股价各下跌4.2%。这不是一次普通的产品发布，而是PC处理器市场四十年来首次迎来真正的"第三极"。此前，x86双寡头格局虽然在ARM阵营（高通）的冲击下出现过裂缝，但NVIDIA携GPU生态与AI势能入场，威胁等级完全不同。

N1X是什么：基于RTX Spark的PC战略核心​

N1X由NVIDIA与微软合作打造，基于2026年6月Computex上发布的RTX Spark芯片，面向消费级和OEM Windows PC市场。其核心规格如下：

规格	参数
CPU	最多20核 Arm CPU
GPU	6144 CUDA 核心（Blackwell 架构）
统一内存	最高 128GB LPDDR5X
内存带宽	300GB/s
模型能力	可运行1200亿参数模型
上下文长度	100万 token
上市时间	2026年秋季

从规格上看，N1X本质上是一颗"能当CPU用的AI显卡"：20核Arm CPU负责日常计算与Windows系统负载，6144个CUDA核心的Blackwell GPU则让本地运行千亿参数大模型成为可能。100万token的上下文窗口，也远超当前多数消费级平台的本地推理能力。

三重竞争关系：高通、苹果与x86双寡头​

对高通：N1X与Snapdragon X Elite走的是同一条Arm PC路线，但NVIDIA手中握有高通无法匹敌的王牌——CUDA生态。Arm PC推广多年来最大的痛点是软件兼容性，而NVIDIA的GPU驱动、AI软件栈（TensorRT、cuDNN）和游戏生态都是现成的，这让N1X在"AI PC"叙事上比高通更完整。

对苹果：N1X的统一内存架构明显对标Apple Silicon。128GB统一LPDDR5X加上300GB/s带宽，思路与M系列芯片的统一内存如出一辙——CPU与GPU共享大容量内存，这正是本地大模型推理的关键。苹果证明了这条路能跑通，NVIDIA则试图凭借更大的CUDA生态基本盘分食这块蛋糕。

对Intel与AMD：这才是最致命的。x86双寡头四十年来首次同时面对：一个掌握AI算力定义权的对手、一个深度绑定微软Windows的Arm方案、以及一个在数据中心已经验证过平台化打法（CPU+GPU+网络）的竞争者。当日4.2%的跌幅，反映的正是市场对"第三极"长期侵蚀份额的定价。

份额转化取决于什么​

当然，发布日的股价下跌不等于市场份额的转移。N1X的实际份额转化取决于三个变量：

1. 兼容性：Arm架构Windows在x86应用转译、外设驱动、游戏反作弊等方面的表现，仍是高通路线上的老问题，NVIDIA与微软的深度合作能否解决尚待观察；
2. OEM采纳：N1X面向消费级和OEM市场，联想、戴尔、惠普等大厂的整机定价、渠道投入将决定其出货规模；
3. 性价比：RTX Spark方案的成本能否支撑有竞争力的整机价格，是消费者用钱包投票的最终标准。

小结​

N1X的发布标志着PC处理器市场进入"三强时代"：Intel与AMD的x86双寡头、苹果的Apple Silicon、以及NVIDIA+微软的Arm AI PC阵营。秋季上市之后，N1X能否将资本市场的恐慌转化为真实的出货量，要看兼容性、OEM采纳与性价比三大变量的兑现程度。想了解N1X的完整规格与参数细节，详见站内芯片页：NVIDIA N1X。

2026年进入第四季度，AI芯片竞争的关键词从"发布"转向"交付"。Rubin能否持续放量、Helios能否如期爬坡、昇腾950DT如何定价上市，将共同决定2027年竞争格局的起点。

NVIDIA：Rubin放量与生态开放双线推进​

Q4期间NVIDIA的计划主线：

• Vera Rubin NVL72：2026下半年持续放量，MLPerf Inference v6.1首秀已登顶（Qwen3-VL较GB300最高3.7倍），HBM4平台优势开始兑现；
• N1X：基于RTX Spark的PC处理器按计划2026年秋季上市，打开消费级战场；
• Blackwell Ultra（B300）：租用价格参考Nebius口径约9.50美元/GPU小时，仍是当前租赁市场的重要基准；
• 后续代际：Rubin Ultra等后续路线待发；
• 生态动作：NVLink Fusion持续开放生态，NVHBM定制内存方案推进。

产品/计划	Q4状态
Vera Rubin NVL72	2026下半年持续放量
N1X	秋季上市
B300租用	9.50美元/GPU小时（Nebius口径）
Rubin Ultra	待发布
NVLink Fusion / NVHBM	生态开放与定制内存推进

AMD：Helios从首发出货到Q4爬坡​

AMD在Q4的核心任务是交付：

• Helios机架：MI455X首批出货目标Q3末，Q4进入量产爬坡阶段；
• 客户部署：OpenAI 6GW、Meta 6GW部署合作推进中，微软作为首批客户计划2026年下半年交付；
• MI430X：驱动欧洲LUMI-AI超算，拓展科学计算场景；
• ROCm：软件生态继续补齐；
• 下一代：Helios II / MI500级产品路线待公布。

华为：昇腾950DT上市与云服务全球商用​

华为Q4的关键节点最为明确：

• 昇腾950DT：Q4上市，报价超25万元；
• 昇腾950智算集群云服务：9月30日已国内商用，11月30日全球商用；
• 960系列：计划2027年接棒，970/980排在2028-2029年。

阿里平头哥：真武V900量产倒计时​

平头哥的时间表指向2027年：真武V900计划2027年Q1量产上云，配套磐久AL128与50万卡集群规划；J900排期2027年Q3。Q4将进入量产前最后的验证阶段。

OpenAI/博通 Jalapeño：多吉瓦部署推进​

OpenAI与博通合作的Jalapeño定制芯片规格已明确：13.4 PFLOPS（4-bit精度）、232GB内存，多吉瓦部署规划正在推进。这枚自研芯片的量产进度，将直接影响OpenAI未来的算力自给率。

关键变量：三大约束​

Q4的交付兑现程度，将取决于三个外部约束：

1. HBM供给：戴尔CEO警告2027年可能比2026年更紧缺，HBM产能是所有GPU路线图的共同瓶颈；
2. 国产涨价传导：昇腾950DT涨价20%-50%、寒武纪690涨价20%-30%（路透，HBM成本驱动），涨价将传导至国产算力服务价格；
3. 电力约束：Emerald AI/Google/NVIDIA成立的AEMA电网响应模式，预示电力正在成为算力扩张的第一性约束。

三条观察建议​

基于上述事实，给三类角色的观察点（非投资建议）：

• 采购方：昇腾950DT与寒武纪690的涨价幅度表明国产算力已进入卖方市场，锁量谈判宜早不宜迟；同时关注Helios Q4实际爬坡数据，作为第二供应源评估依据；
• 开发者：ROCm生态补齐与NVLink Fusion开放，意味着2027年异构算力混布的软件门槛正在降低，可提前在推理侧做多框架适配；
• 投资者：可跟踪的公开观察点包括——Helios首批交付兑现情况、昇腾950云服务11月30日全球商用落地、HBM价格走势对各家毛利率的影响信号。

小结​

2026年Q4是"交付验证季"：NVIDIA Rubin放量、AMD Helios爬坡、昇腾950DT上市与云服务全球商用、平头哥V900量产倒计时——各家计划均已排定，剩下的变量集中在HBM供给、涨价传导与电力约束三点。所有时间节点以"计划/预计/排期"口径为准，Q4末回看兑现率，就是对2027年格局的最好预判。

当芯片厂商开始"造内存"、云厂商开始"造芯片"，AI基础设施的分工边界正在瓦解——存储不再是采购来的标准件，而是与加速器协同设计的战略资产。

NVHBM：AWS与NVIDIA的定制内存联姻​

AI Infra Summit 2026（9月17日）上爆出的消息显示：亚马逊旗下Annapurna Labs正与NVIDIA合作开发NVHBM定制高带宽内存技术。

这个组合本身就足以说明问题。Annapurna Labs是AWS自研芯片体系的核心（Graviton CPU、Trainium/Inferentia加速器都出自该团队），而NVIDIA则是AI加速器绝对主导者。两家联手开发定制HBM，意味着最强势的云厂商与最强势的芯片厂商决定共同绕开标准内存路线，为AI负载打造私有化的内存方案。

存储协同设计：行业范式转移​

NVHBM并非孤立事件。AI Infra Summit 2026前后，存储行业的密集动作勾勒出一幅"存储深度嵌入AI"的图景：

厂商	时间	动作	关键内容
亚马逊+NVIDIA	9月17日报道	合作开发NVHBM	定制高带宽内存
SK海力士	9月17日	发布"New Spectrum"组合	HBF高带宽闪存、PIM存内计算、eSSD、SALT-KV
SK海力士	9月18日	成立SK hynix Ventures（硅谷）	拓展全球AI生态投资
美光	9月15日	超密度服务器内存模组	全球首款

2026年9月21日的半导体周报对这一趋势给出了精辟概括："Memory is being co-designed with AI accelerators rather than treated as a commodity"——内存正在与AI加速器协同设计，而不再被视为大宗商品。

这句话宣告了一个时代的结束：过去几十年，内存是标准化的商品，JEDEC规范统一接口，谁家买都一样。而在AI时代，内存的带宽、容量、拓扑直接决定集群效率，"标准件"思维已经跟不上需求。

为什么绕过JEDEC走定制路线​

超大规模厂商选择定制HBM，动机有三：

• 性能天花板：标准HBM的规格迭代节奏由JEDEC委员会决定，而AI负载的内存需求以年为单位翻倍。定制方案可以围绕特定加速器优化堆栈数、接口带宽和容量配比，榨取最大能效。
• 供应安全：HBM产能持续紧张，已成为整个AI芯片产业的瓶颈。定制协议绑定的不只是技术规格，更是产能分配——把内存供应商变成深度盟友。
• 成本控制：HBM占AI加速器物料成本的重要比重。云厂商自建芯片团队后，有动力也有能力参与内存定义，消除中间层的规格冗余。

HBM短缺：国产芯片涨价潮的根源​

定制HBM军备赛的另一面，是HBM产能的普遍短缺。近期的国产芯片涨价潮，其根源正是HBM供应不足——当NVIDIA、AMD以及各云厂商自研芯片都在争夺有限的HBM产能时，位于优先级末端的采购方（包括部分国产AI芯片厂商）面临的是"有芯片设计、没有内存可用"的窘境，成本随之水涨船高。

这解释了为什么HBM产能与成本已成为芯片厂商的核心竞争维度：谁能锁定HBM供应，谁就能锁定出货量；谁的定制内存方案能效更高，谁的产品就更具竞争力。存储厂商的地位因此空前提升——SK海力士在发布"New Spectrum"后次日即于硅谷设立SK hynix Ventures投资AI生态，正是从供应商向生态节点跃迁的标志性动作。

对下一代平台意味着什么​

NVHBM若落地，影响将体现在两个层面：

• NVIDIA Vera Rubin及后续代际：定制内存与加速器协同设计，意味着未来Rubin后续产品的内存子系统可能针对AWS负载定制，云厂商对芯片平台的参与度从"采购方"升级为"共同定义方"。
• 机架级内存竞赛：AMD已展示31TB HBM4机架方案，机架级内存容量的军备竞赛已经开打。当内存容量从单卡432GB演进到机架数十TB，内存架构的设计自由度（定制HBM vs 标准HBM4）将直接决定产品竞争力。

小结​

AWS联手NVIDIA开发NVHBM，标志着存储正式从"采购关系"进入"协同设计"时代：SK海力士以HBF/PIM/eSSD/SALT-KV重构存储产品线并设立风投部门，美光推出超密度内存模组，超大规模厂商开始绕过JEDEC定制内存。HBM短缺引发的国产芯片涨价潮则揭示了新秩序的残酷一面——内存即产能，产能即话语权。当"造内存"成为芯片巨头的必修课，AI基础设施的竞争维度被彻底改写。

This article is based on market analysis published by Bloomberg Intelligence and Bernstein in September 2026 and public reporting; market share and revenue figures are analyst estimates, not official disclosures.

On September 28, two Wall Street reports simultaneously painted a dramatic picture: the balance of market share in China's AI compute market completed an almost total flip within 12 months.

1. The Share Flip: 40% to 8%, Ascend to 50%​

Bernstein's latest forecast:

• NVIDIA's share of the China AI chip market will fall from about 40% to about 8% by the end of this year
• Huawei Ascend rises to nearly 50%
• The immediate trigger: China's September ban on new H20 orders from NVIDIA, which shut the last channel for NVIDIA's return to the Chinese market
• ByteDance, Alibaba, and Tencent have all placed large Ascend orders

On the timeline, this was not a sudden shock but the cumulative result of three years of tightening export controls: NVIDIA's share of the China AI chip market once peaked at 95%; as high-end chips were cut off, Chinese hyperscale cloud providers pivoted wholesale to Huawei and domestic alternatives. Even when Washington allowed H200 sales to China in January 2026, the gears of that shift had already meshed — there was no going back.

2. Ascend 950PR: The "Chinese H200" in Analysts' Eyes​

What underpins this share data is product strength itself:

• The Ascend 950PR entered mass production in March this year, with FP4 compute of up to 2 PFLOPS and 128GB of domestic HBM
• Analysts rate it as roughly on par with the NVIDIA H200
• Huawei's AI chip revenue is expected to reach $12 billion this year, up 60% from $7.5 billion in 2025

For the full specifications of the 950 series, see our earlier in-depth articles: Ascend 950PR/950DT Dual-Configuration Analysis and Ascend 960 Official Launch — the 960 was ready three quarters ahead of schedule, confirming a one-generation-per-year cadence.

3. The Model Side: Chinese Open Models Take the OpenRouter Token Pie​

While chip shares flipped, the model usage data is equally striking (OpenRouter platform statistics):

Metric	Data
DeepSeek token share (June)	16.3%, surpassing Google, Anthropic, and OpenAI individually to rank first
Combined token share of Chinese open-weight models (May)	About 61% (DeepSeek, Qwen, MiniMax, Tencent Hunyuan, etc.)
Weekly token consumption of Chinese models	About 18 trillion, versus about 5.5 trillion for US models — a gap of more than 3x, with the overtake completed within a year
China-US frontier model performance gap (June)	Narrowed to 6%, a historic low (9% in May)

Compute and models form a positive feedback loop: cards that cannot be bought force domestic compute to scale up; scaled-up domestic compute produces cheap tokens; and cheap tokens let Chinese open-source models swallow the bulk of global inference traffic.

4. But the Stock Market Isn't Buying It​

Bloomberg Intelligence pointed out a contradiction in the same period: the valuation discount of the China Tech 8 relative to the US Magnificent Seven has widened to more than 50%, the widest of the year, and BI believes only a "true AI breakthrough" can close it. Year-to-date stock performance: Alibaba about -7%, Tencent about -23%, while US AI infrastructure leaders broadly gained more than 15%.

There are two readings of this divergence: either the market is underestimating China's AI fundamentals, or earnings execution (Alibaba's EPS missed expectations by 17.3% last quarter, Baidu's by 36%) has dragged down the delivery of the AI narrative. For industry observers, the notable point is: the compute-side data (share, revenue, shipments) has moved ahead, while application-side monetization is still on the way.

5. Three Takeaways for Compute Buyers​

1. For deployments in China, the Ascend ecosystem is already the default option. The cost of migrating from CUDA to CANN is one-time, while supply uncertainty is persistent; after the September ban, there is no compliant path to procuring new NVIDIA cards in the Chinese market.
2. Domestic compute "matching the H200" is a watershed. The implicit assumption of domestic substitution used to be "discounted performance, discounted price"; when single-card performance catches up to the H200 generation, procurement decisions return to pure TCO and supply-security calculations — we recommend using the TCO Calculator to put electricity, depreciation, and utilization into the same table.
3. The token cost curve determines the application landscape. Chinese models' 61% share of OpenRouter tokens shows that the chain of compute self-sufficiency leading to token price drops leading to application prosperity has completed its first leg; the next question is whether inference costs can keep falling.

Summary​

From 40% to 8% is not a slogan but a market reshuffle driven jointly by the ban, product strength, and the model ecosystem. For the Chinese market, the mass-production cadence of Ascend 950/960 and the maturity of the CANN ecosystem will determine whether this share can be held; for the global market, the combination of China's compute "internal circulation + open-source models going overseas" is rewriting the geographic distribution of inference traffic.

(Market share and revenue forecasts come from Bernstein / Bloomberg Intelligence analyst reports; actual figures are subject to each company's financial reports.)

This article is based on NVIDIA official product pages, the March 2026 GTC architecture blog, and third-party benchmark data; performance figures are vendor architecture comparisons, and actual gains should be verified with your own tests.

NVIDIA has confirmed that Groq 3 LPX — the "seventh chip" of the Vera Rubin platform — has entered full mass production, manufactured at Samsung's Pyeongtaek campus. This is the first time the deal has landed in the form of production silicon since December 2025, when NVIDIA spent roughly $20 billion to obtain a non-exclusive IP license to Groq plus its core engineering team.

For the inference hardware landscape, this is a paradigm-level event: for the first time, NVIDIA has incorporated a "specialized inference architecture defined by someone else" into its own flagship platform — and not as an add-on sale, but as deep co-design.

1. The Groq 3 LPU Chip and the LPX Rack: Specs at a Glance​

Single Groq 3 LPU (4nm, Samsung foundry):

Item	Value
Compiler-managed on-chip SRAM	500 MB
SRAM bandwidth	150 TB/s
Chip-to-chip scale-up bandwidth	2.5 TB/s (96 chip-to-chip links, 112 Gbps each)

A single LPX rack (32 1U liquid-cooled trays, 8 LPUs per tray):

Item	Value
Total LPUs	256
FP8 compute	315 PFLOPS
Total on-chip SRAM	128 GB
Aggregate SRAM bandwidth	40 PB/s
In-rack scale-up bandwidth	640 TB/s
DDR5 memory	12 TB (hosting large model weights)

The 500 MB of SRAM per LPU may not look like much, but multiplied by 256 LPUs and stacked with 40 PB/s of aggregate bandwidth, it forms the physical foundation of "deterministic low-latency decoding" — the LPU's design philosophy is precisely to use compiler static scheduling of on-chip SRAM to completely eliminate memory-fetch stalls during the inference decoding phase, which is exactly the most typical bottleneck of GPU inference.

2. AFD: Attention and FFN Split Up, GPU and LPU Each Do Their Own Job​

LPX does not replace the GPU; instead, it forms a heterogeneous system with Vera Rubin NVL72, centered on AFD (Attention-FFN Disaggregation):

1. Rubin GPUs handle prefill and attention — building the KV cache over large contexts and executing attention layers, consuming HBM capacity and high throughput;
2. Groq 3 LPUs handle FFN / MoE expert-layer decoding — latency-sensitive and pattern-predictable, exactly the home turf of deterministic SRAM scheduling;
3. Intermediate activations are exchanged between the two engines token by token, orchestrated and routed by NVIDIA Dynamo: the GPU computes every attention layer, the LPU computes every feed-forward layer, jointly producing each output token.

The logic of this division of labor is clear: agentic AI applications can consume 15x the tokens of traditional AI applications, and the bottleneck shifts from "can it finish computing" to "can it keep emitting tokens at stable low latency." Let the big HBM container run attention, and let the deterministic SRAM engine run decode — each plays to its strengths.

3. Measured Results and Official Figures​

• Third-party benchmarks (Artificial Analysis): with Gemma 4 31B at a 100K token context, LPX output reaches roughly 3400 tokens/s — inter-token intervals below 1 millisecond, a qualitative leap in interactivity for long-context agentic scenarios
• Official architecture comparisons: with LPX added, Vera Rubin NVL72 achieves up to 35x higher throughput per megawatt on trillion-parameter models; up to 10x more revenue opportunity per watt in "high-value token" scenarios
• Launch customers: Nebius is the first to deploy LPX racks to expand its token capacity; CoreWeave already connects Vera Rubin racks in production with Spectrum-X Multiplane

It must be emphasized: the 35x/10x figures are architecture comparisons at specific high-interaction operating points, not universal conclusions. For training, high-throughput batch inference, and workloads that need CUDA ecosystem flexibility, the GPU remains the right answer; LPX's home turf is scenarios where "single-user interactive latency is the product" — agent loops, real-time coding assistants, long-context conversations.

4. Three Industry Signals​

1. Specialized inference chips get absorbed, not opposed. The old narrative of the LPU as a "GPU challenger" has become part of Vera Rubin. The endgame for inference hardware may not be one architecture winning, but the heterogeneous combination of "GPU + specialized decoding engines" becoming the standard. For other inference chip startups (Cerebras, Etched, etc.), this is both proof that the ceiling has risen and a warning: get integrated or find differentiation.

2. Samsung foundry lands a high-end AI order. Against the backdrop of TSMC's near-monopoly on AI main chips, Samsung 4nm taking on LPX mass production is highly significant — combined with Tesla's earlier AI6 2nm order, Samsung foundry has a shot at returning to full-year profitability in 2027.

3. Inference economics enters the "priced per MW" era. When vendors start telling their story with tokens/MW and revenue per watt, the core KPI of compute selection has completely shifted from peak compute (TFLOPS) to token output per unit of energy. This is consistent with the power-and-electricity cost model built into our TCO Calculator: the chip with the best-looking peak specs is not necessarily the chip with the lowest cost per token.

Summary​

Groq 3 LPX mass production marks the arrival of a heterogeneous era for inference hardware: "GPUs manage throughput, LPUs manage latency." For teams currently selecting inference clusters, the recommendation is to evaluate workloads separately: keep batch offline inference on GPUs, and separately calculate the unit cost of LPX-class solutions for interactive long-context agents. If in doubt, run the 3-year total cost of ownership of both architectures through the TCO Calculator before deciding.

(Performance data in this article comes from NVIDIA official architecture comparisons and Artificial Analysis third-party benchmarks; for actual deployments, please rely on your own testing.)

On September 16, MLCommons released the MLPerf Inference v6.1 Closed Division results, and NVIDIA's Vera Rubin NVL72 completed its benchmark debut. The same day, CoreWeave announced that a multi-rack Vera Rubin cluster was live on its cloud — a "rent the new hardware on launch day" cadence that is compressing the cycle from next-generation compute announcement to billable output down to a quarter.

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1. Debut Results: 3.7x and 2.5x​

NVIDIA, via preview submissions (entries 6.1-0106 / 6.1-0074), provided an apples-to-apples comparison of its two flagship generations:

Benchmark Model	Vera Rubin NVL72 vs GB300 NVL72	Software Stack
Qwen3-VL-235B-A22B (235B multimodal MoE)	Throughput up to 3.7x (across offline / server / interactive scenarios)	vLLM + NVIDIA Dynamo
DeepSeek-R1-671B (671B inference model)	Throughput up to 2.5x	TensorRT-LLM

The three technologies behind these numbers:

• NVFP4 precision: compresses the memory footprint of model weights, attention tensors, and the KV Cache, enabling significantly larger effective batch sizes;
• Disaggregated serving: prefill (compute-intensive) and decode (bandwidth-intensive) are split across separate GPU pools, each independently optimized;
• Expert parallelism: MoE expert layers route across chips in a distributed fashion, paired with sixth-generation NVLink / NVLink Switch (NVIDIA claims 10x the packet rate of commodity Ethernet at 3x lower latency).

2. Same-Session Highlights: Scaling Efficiency and the Software Dividend​

• GB300 four racks, 288 chips, 99% scaling efficiency: in the DeepSeek-R1 offline scenario, scaling from a single rack of 72 chips to 4 racks of 288 chips shows almost no loss (entries 6.1-0073 / 6.1-0074) — the first time rack-scale interconnect scaling efficiency has been validated at the 288-chip level;
• The software dividend is still being paid out: on the same GB300 hardware, v6.1 software optimizations deliver up to 1.6x Qwen3-VL gains over v6.0; NVIDIA also reported post-submission gains for GPT-OSS-120B and DLRMv3 (not verified by MLCommons);
• 19 partners submitted, 8 of them using multi-node Blackwell NVL72 configurations (ASUS, Azure, Cisco, CoreWeave, Crusoe, Dell, Fujitsu, HPE, Lambda, Nebius, OCI, Supermicro, and others); Nebius also submitted Vera Rubin preview results.

3. CoreWeave Online the Same Day: Rentable at Launch​

On the same day the MLPerf results were published, CoreWeave announced that its multi-rack Vera Rubin NVL72 cluster was live on its cloud:

• Spectrum-X networking links hundreds of Rubin GPUs into a single scale-out cluster, with each GPU paired with 2 ConnectX-9 SuperNICs (1.6Tb/s scale-out bandwidth);
• The AI object store LOTA cuts read latency by 8x;
• On the operations side: Valvey software-defined liquid cooling (NVIDIA spec: 45°C liquid inlet), the Racky rack control layer, and Rack LifeCycle Controller manage an entire NVL72 rack as a single programmable entity;
• Back in July, CoreWeave's own testing put Vera Rubin at 10x tokens/s/MW versus GB200 NVL72 on DeepSeek R1 (company figures, not MLCommons-verified).

4. The Competitive Picture​

• AMD + Crusoe: set MLPerf's all-time high aggregate throughput of 5.75M tokens/s on 512 chips (AMD had the broadest submission coverage this round);
• SemiAnalysis AgentX preview: Vera Rubin up to 30x over GB300 on agentic workloads (preview figures); the MLPerf Endpoints benchmark is forthcoming and will bring agentic inference into standardized measurement;
• Pending validation: Vera Rubin results are preview submissions awaiting independent reproduction; no quantified quality metrics were given for NVFP4's "virtually lossless" claim; per-token cost and power-consumption scaling comparisons have not been published. Matching submissions from Google TPU v7 and AMD MI455X UALoE72 are expected within 2026.

On-site spec comparisons: Rubin R200 (288GB / 22TB/s), B300 Ultra (GB300-class core).

5. Takeaways​

• Vera Rubin NVL72 debut: Qwen3-VL 3.7x, DeepSeek-R1 2.5x over GB300 NVL72 (preview figures);
• GB300 across four racks of 288 chips at 99% scaling efficiency — rack-scale interconnects have entered the usable range;
• CoreWeave brought a multi-rack cluster online the same day — the cycle from next-gen compute launch to billable output is now measured in quarters;
• What to watch: independent reproductions and formal (non-preview) submissions, TPU v7 / MI455X comparison results, and measured per-MW token throughput.

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Further Reading​

• Rubin R200 Spec Page / B300 Ultra Spec Page (this site)
• NVIDIA Vera Rubin Mass Production and Liquid Cooling Deployment
• Hot Chips 2026 Full Recap: Rubin, MI455X, Crescent Island on the Same Stage

References​

• NVIDIA Blog: Vera Rubin NVL72 Makes Its First Appearance in MLPerf Inference v6.1 (2026-09-16)
• MLCommons: MLPerf Inference v6.1 Closed Division results (entries 6.1-0073 / 6.1-0074 / 6.1-0106)
• CoreWeave Investor Relations: multi-rack Vera Rubin NVL72 availability announcement (2026-09-16)
• AMD Blogs: MLPerf Inference v6.1 submission results

This article is compiled from public MLCommons results and vendor official statements. Vera Rubin results are preview submissions; some gain figures are not MLCommons-verified and are flagged item by item.

本周（2026 年 9 月 1 日–5 日）AI 算力行业的题眼，是两条相反方向的成本重构：海外，英伟达以史上最大并购吞下开发者生态入口，同时给旗舰减配显存——"内存太贵"倒逼硬件从单卡堆料走向系统级互联；国内，DeepSeek 16 万颗昇腾订单把"国产替代"从口号变成头部实验室的资产负债表决策，字节近 300 亿美元融资为算力扩张装上杠杆。

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1. DeepSeek 拟购 16 万颗昇腾 950DT：国产算力的"标志性订单"​

彭博社 9 月 4 日报道，DeepSeek 计划在内蒙古乌兰察布新建的约 1GW 数据中心部署至少 16 万颗华为昇腾 950DT，主要用于推理而非训练。按每颗约 11.1 万元的市场价估算，订单总额约 178 亿元人民币（约 25.6 亿美元）——这是迄今已知规模最大的昇腾集群，是半年前深圳首个万卡级集群的 16 倍。

三个关键读数：

• 主动选择，而非被迫替代：DeepSeek 是公认最会"榨干"算力的实验室。创始人梁文锋 7 月曾直言：华为超节点能完成 GB300 的任务、延迟没有明显差别，但约需 4 颗昇腾才抵 1 颗英伟达、技术上落后约两年。选择昇腾跑推理，是在综合成本、供应链安全与本土化后的理性决策——推理对软件生态依赖较浅，正是国产芯片的突破口；
• 瓶颈在供给端：受高端内存（HBM）短缺制约，昇腾 950DT 今年产量仅数十万颗（2026 年全部昇腾 die 计划约 160 万颗），DeepSeek 希望加购更多但产能所限，整单交付或需一年以上——国产 HBM 与先进封装成为整条链的胜负手；
• 过渡性押注：DeepSeek 同时在与中芯国际合作开发自研推理芯片，并于 6 月完成约 500 亿元融资、继续洽谈数十亿美元基建融资。国产算力的终局是多元自主，而非单一依赖。

单颗 950DT：144GB HBM、4.0TB/s 带宽、2.0TB/s 互联，原生支持 FP8/FP4/HiF8，详见昇腾 950DT 规格页。

2. 英伟达 129.3 亿美元收购 Hugging Face：买下"铲子的交易所"​

当地时间 9 月 3 日，英伟达宣布以 129.3 亿美元收购全球最大开源 AI 平台 Hugging Face，超过 2020 年 69 亿美元收购 Mellanox，成为其史上最大并购。交易含约 119 亿美元股权款与最高约 10 亿美元员工留任计划，预计 2027 年上半年完成，待监管批准。

Hugging Face 托管超 300 万个模型、50 万个数据集，服务超 1800 万名开发者。黄仁勋承诺平台继续开放中立运营：不强制绑定英伟达资源、开源属性完整保留。

解读：算力霸主的护城河从"芯片 + 网络 + 软件栈"一路修到了"模型分发 + 开发者生态"——卖铲人开始收购铲子的交易所。平台的"中立性"承诺能否兑现，将成为全球监管与竞争性云厂商持续盯防的焦点；对国内产业而言，模型托管、权重分发这类"轻资产 AI 基础设施"与芯片一样，正在成为大国科技博弈的卡点。

3. Rubin Ultra 显存减配：内存占 TCO 40% 后的算术题​

SemiAnalysis 最新报告（科创板日报 9 月 3 日转引）显示，英伟达已将旗舰 Rubin Ultra 的 HBM 配置从 HBM4E 12-Hi（384GB 档）下调至 HBM4 8-Hi（192GB），三星正配合开发 8 层产品。

• 动因：HBM/DRAM 涨价后，内存已占整机 TCO 约 40%；减配后 HBM 成本降超 50%，即便计入 2026 年 HBM 涨价预期，内存占总资本开支比例也将从 40% 压至 28%；
• 钱去了哪：转向 Scale-up 纵向扩展网络——以 NVL576 NPO 方案测算，光模块取代机架间互连后，Scale-up 网络占机架总支出比例从 4% 升至 12%；
• 连锁反应：TrendForce 显示英伟达自 2026 Q3 起并行评估 HBM4E 8-Hi / 12-Hi / HBM4 8-Hi 多套方案，部分云厂商也在考虑下调下一代自研 ASIC 的 HBM 容量。

连定价权最强的英伟达都给旗舰"减配求量"，等于官宣：当前 AI 硬件最紧的约束是内存（美光高管称新增内存供应 2028 年前难有实质放量），单卡堆料的军备竞赛告一段落，硬件价值重心正迁移到光互联、CPO、高速交换与 PTFE 背板。华泰测算 2027 年存储供需缺口将从约 -7% 收窄至 -3%——上行周期未逆转，但从"普涨"走向"结构性紧缺"。

详见本站已同步更新的 Rubin Ultra 规格页与HBM4 量产竞速分析。

4. 推理 ASIC 军备提速：谷歌"一年两款"，Jalapeño 规格落地​

• 谷歌 TPU 迭代周期从两年一代压缩至"每年两款"（华创证券 9 月 4 日研报）：第八代已拆分为训练（8t）与推理（8i）双架构，8i 把内存/算力配比拉到 8t 的 1.65 倍，专为推理放量设计；
• OpenAI Jalapeño 规格披露：6 堆栈 HBM4 共 216GB、带宽 15.4TB/s、700W，围绕投机解码设计；OpenAI 称在 DeepSeek R1 负载下 tokens/kW 达 GB300 的 1.7 倍；RTL 冻结到流片 9 个月，首批硅片后约 10 周承载 ChatGPT 流量。详见规格页（本站已更新）；
• workload-specific 时代开场：训练、推理、推荐各自长出专用芯片，上游 HBM/封装/光互联的供应节奏必须跟上"半年一代"。

5. 国内动态：字节 296 亿美元加杠杆，摩尔线程 Token 超节点投产​

• 字节跳动获约 296 亿美元融资安排（彭博 9 月 3 日），较最初约 200 亿美元目标大幅上调，用于数据中心与 AI 基建；另据产业报道正洽谈在内蒙古新增 5-6GW 算力产能——中国 AI 公司迄今最大规模基建融资之一，算力正被当作可融资、可证券化的重资产经营；
• 摩尔线程 × 趋境科技 "Token 超节点"投产（光明网 9 月 4 日）：以 MTT S500 承担 Prefill 与 KV Cache 生成、高带宽 GPU 专注 Decode 的 PD 异构方案，实测平均生成速度超 50 TPS、KV Cache 命中率超 90%、稳定性 99.9%，已承接头部模型厂商官方业务流量——超节点竞争维度从"单卡参数"转向"单位 Token 生产成本"；
• OpenAI 发布 GPT-6 Astra（9 月 4 日）：超 10 万颗 GPU 在 Stargate 集群完成训练，推理放量与超大规模集群仍是全球算力叙事主线；
• SemiAnalysis 基准：AMD MI355X 新提交在 AgentX 基准低交互区间tokens/$ TCO 击败 B300——vLLM + LMCache 软件栈的贡献首次被独立机构量化认可。

6. 市场：中美算力资产一涨一调​

美东 9 月 4 日，美国 8 月非农仅增 8.9 万人（预期 16 万），10 年期美债收益率回落至 3.78%，成长股走强：科技板块 XLK 周涨 4.2%，英伟达周涨 8.7% 收于 230.36 美元。A股 9 月 4 日反向回调：AI 算力芯片板块 -1.99%、服务器 -2.51%、超节点 -2.86%，浪潮信息跌停、寒武纪 -2.54%——基本面无恶化（博通、戴尔、中际旭创订单与财报持续验证景气），更多是交易层面获利兑现。

下周起三连催化密集：CIOE 光博会（9/9-11）→ 华为全联接大会（9/17-19）→ 云栖大会（9/22-24）。国产超节点从"发布会 PPT"到"批量交付"的成色，将迎来集中检验。

本周一句话​

内存太贵改变了所有人的算法：英伟达给旗舰减配显存、把钱投给互联；DeepSeek 用 16 万颗昇腾买推理确定性；谷歌把 TPU 迭代压到半年一代。2026 年 Q4 起，"每兆瓦/每美元 token 数"将取代"单卡 PFLOPS"，成为算力采购的第一指标。

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相关链接​

• 华为昇腾 950DT 规格页
• NVIDIA Rubin Ultra 规格页
• OpenAI Jalapeño 规格页
• NVIDIA Rubin 规格页

参考资料​

• 彭博社（转引）：DeepSeek 拟部署 16 万颗昇腾 950DT（2026-09-04）
• cnBeta/今日头条：DeepSeek 据称采购 16 万颗华为昇腾 950DT 芯片（2026-09-05）
• 科创板日报：SemiAnalysis 拆解 Rubin Ultra 减配（2026-09-03）
• Natural News/DailyAI：Nvidia To Acquire Hugging Face For $12.9B（2026-09-05）
• 光明网：摩尔线程 × 趋境科技 PD 异构推理方案投产（2026-09-04）
• AGI Hunt：AI News Daily 2026-09-05

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本文基于彭博社、科创板日报、SemiAnalysis、TrendForce、华创证券研报及光明网等公开报道整理。订单金额与市场数据为媒体/机构预估口径，实际以相关公司正式披露为准。

This article is based on official announcements from AWS and NVIDIA (September 5, 2026) and public statements by executives of both companies.

On September 5, 2026, AWS and NVIDIA announced an expanded strategic partnership: on top of the "1 million additional GPUs starting in 2026" plan announced at GTC 2026, they will deploy 2 million more NVIDIA GPUs, covering three architecture generations — Blackwell Ultra, Rubin, and Rubin Ultra — with a deployment window of 2027-2028. Demand growth exceeding all previous forecasts was the direct reason both companies cited.

This is no longer a simple "chip purchase" — it is a full-stack partnership spanning GPUs, CPUs, interconnect, memory, open-source models, and software. We break the key information into six points.

1. Composition and Timeline of the 2 Million GPUs​

• Scale: 2 million GPUs (added on top of the original 1 million GPU plan, tripling the total committed scale)
• Architectures: Blackwell Ultra, Rubin, Rubin Ultra
• Timeline: 2027-2028, deployed across AWS global infrastructure (including newly built AI factories)
• Context: Amazon's 2026 capital expenditure guidance has been raised from $200 billion to $220 billion, and CEO Andy Jassy has explicitly said it is still not enough to meet AI compute demand

For reference, the figures Jensen Huang gave at GTC 2026 put cumulative orders and demand for the Blackwell and Rubin platforms through 2027 on track to reach $1 trillion (at GTC 2025, the estimate for 2026 was roughly $500 billion). AWS's add-on order is one of the heaviest puzzle pieces in that big picture.

2. Vera CPU Comes to AWS for the First Time​

This is the most structurally significant change in the partnership: NVIDIA Vera CPU infrastructure will enter AWS.

The Vera CPU is the general-purpose processor in the Vera Rubin platform designed for agentic AI, positioned to efficiently turn AI resources into "completed agent tasks." As agentic workloads rise, CPU-side pressure on task orchestration, memory management, and data scheduling rises in step — pure GPU expansion is no longer enough, and AWS needs a matching high-performance CPU layer. This also aligns with AWS's strategy of "offering the broadest compute choices, from in-house chips (Graviton/Trainium) to partner chips": Vera does not replace Trainium, but fills in the CPU compute layer alongside the accelerated infrastructure.

3. NVLink Fusion × NVHBM: Open Architecture Goes Deeper​

At re:Invent 2025, AWS announced that its next-generation Trainium chip would support NVIDIA NVLink Fusion high-speed interconnect. This time, both companies took the partnership one step further:

• Amazon Annapurna Labs will support NVIDIA's new custom high-bandwidth memory NVHBM (developed in collaboration with memory vendors)
• Trainium thereby gains a faster, more power-efficient memory option
• Trainium and GPUs can work together within the same rack-scale architecture, sharing scale-up interconnect

For the chip industry, this is a signal worth watching closely: NVLink Fusion + NVHBM means NVIDIA's interconnect and memory technologies have started "supplying" competing ASICs. The boundary between the in-house ASIC camp (Trainium, TPU, MTIA) and the NVIDIA GPU camp is shifting from "either/or" to "hybrid deployment."

4. 100,000 GPUs: The U.S. Government Sovereign AI Factory​

A dedicated public-sector business is carved out of the partnership: AWS and NVIDIA will build AI factories for the U.S. government, deploying 100,000 GPUs on secure AWS infrastructure to host federal and national security workloads (Impact Level 6 and above), supporting the development of advanced AI models within strict regulatory frameworks.

Sovereign AI turning from a slogan into concrete numbers is a defining feature of this cycle — government customers are becoming first-class buyers of AI compute.

5. Software and Physical AI Deepen in Parallel​

Beyond hardware, the software layer of the partnership is also strengthening:

• NVIDIA Nemotron open-source models continue to arrive on Amazon Bedrock and SageMaker
• Amazon EMR data processing and OpenSearch vector indexing are accelerated by cuDF / cuVS
• Amazon Robotics officially adopts the NVIDIA physical AI platform (Jetson, Omniverse, Isaac) for warehouse automation and next-generation robotics

Physical AI (robotics, embodied intelligence) is becoming a new growth pole in cloud providers' compute narratives — the same trend as JD.com, Tesla, and others writing embodied intelligence into their compute procurement logic.

6. Implications for Compute Buyers​

Observation	Implication
Demand "beat all forecasts"	Supply tightness is not a short-term phenomenon; the 2027-2028 compute window must be locked in now
Mixed procurement across three architectures	During the Rubin/Rubin Ultra production ramp-up, Blackwell Ultra remains the delivery mainstay; procurement needs cross-generation planning
CPU layer revalued	agentic AI pushes the bottleneck from GPU to CPU orchestration and memory bandwidth; do not focus only on accelerator cards when selecting
Sovereign AI lands	Government-scale orders enter the market, further tightening the allocatable supply of high-end GPUs

For decision-makers weighing build versus rent, every massive add-on order from cloud giants reprices the future rental curve. If you are evaluating GPU purchase or rental options, we recommend running a quantitative calculation with the TCO Calculator: enter chip price, power draw, utilization, and rental rates to compare 3-year total cost of ownership.

Summary​

2 million GPUs, Vera CPU in the cloud, NVHBM opening up, 100,000 sovereign compute GPUs — this round of expansion between AWS and NVIDIA pushes the "AI factory" race into the full-stack era. Compute scarcity will most likely only tighten before 2027; whether you are buying, renting, or betting on domestic alternatives, locking in supply and cost curves early is the surest move right now.

(The data in this article comes from official AWS/NVIDIA announcements and public statements by executives of both companies; architecture performance figures are as released by the vendors.)

2026 年 9 月初，供应链信息确认：英伟达 Vera Rubin 平台已于 8 月正式量产、9 月启动批量出货，无延期、无卡顿。与 Blackwell 迭代初期的产能波折不同，这次量产节奏异常平稳——谷歌云、微软 Azure、CoreWeave、甲骨文云等头部云厂商已启动机架部署。但真正值得产业记住的，不是"又一代 GPU 量产了"，而是 Rubin 把液冷从"可选配置"变成了"硬性前置条件"。

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1. 量产节奏：史上最平稳的一次平台切换​

根据产业链调研与券商跟踪信息：

• 2026 年 8 月：Vera Rubin 正式量产；
• 2026 年 9 月：批量出货启动；
• 2026 下半年：CoreWeave、谷歌云、微软 Azure、甲骨文云机架部署落地；
• 2026 年：上代 GB 架构机柜出货量有望达 6 万台（同比翻倍）；
• 2027 年：GB 与 Rubin 两代平台合计出货体量有望接近 10 万台，Rubin 新机柜远期产能目标为每天 1000 个 NVL72 机柜。

需求侧同样在加码：华尔街报告披露，英伟达管理层表示 FY28 同比增长 70% 的目标并非需求上限——若供应不受限，增速可能超过 100%。当前主要约束已从需求端转向先进晶圆与 HBM 供应。

2. 单卡 2300W：风冷时代的终结​

Rubin 平台与前代最根本的差异不在算力，而在功耗密度：

指标	H100	GB300	Rubin
单 GPU TDP	700W	~1400W	2300W
机柜功耗	~40kW	~140kW	190–230kW
散热方案	风冷为主	风液混合	100% 全液冷
供电架构	48V	48V	800V 高压直流

单芯片 TDP 从 700W 升至 2300W、单机柜功率密度突破风冷物理极限——这意味着 液冷不再是高端算力的选配升级，而是运行 Rubin 服务器的先决条件。英伟达官方将 Rubin 全液冷架构定义为"数据中心历史上最重要的能效突破之一"，并已写入 DSX AI 工厂参考设计：所有跟随英伟达技术路线的云厂商和数据中心运营商，都必须采用全面液冷方案。

三个关键架构变化：

1. 无风扇整机：GPU、CPU、交换机、DPU 全部器件强制采用直接冷板式液冷，45℃ 温水冷板成为出厂标配；
2. 液冷边界延伸：散热覆盖范围从 GPU 冷板延伸至 CPU、DPU、交换机乃至光模块（液冷 Cage/鼠笼开始从"可选"变"刚需"），整套液冷系统价值量较 GB300 提升约 40%；
3. 800VDC 供电：替代传统 48V 机架配电，整机电源 BOM 价值增长 30% 以上，PSU 电源模块从 5.5kW 向 18.3kW 迭代，固态变压器、高压直流 CDU 成为数据中心新增核心设备。

3. 对产业链的三重传导​

第一重：液冷从"配套"变"主角"。 2026 下半年以小规模部署验证为主，真正的放量窗口在 2027 年——Rubin 机架大规模铺货后，冷板、快速接头、CDU、液冷泵进入业绩兑现期。台系供应链 7 月数据已率先验证：AVC 奇鋐 7 月营收 185.9 亿新台币创历史新高（同比 +57.4%），双鸿、健策 7 月同比分别 +116.7%、+91.0%。

第二重：国产液冷供应链进入核心 BOM。 国内厂商由外围冷源和代工环节逐步进入芯片平台、服务器 ODM 和海外云厂商供应体系，替代路径从 Manifold、管路推进至高可靠快接头和冷板。英维克 26H1 海外收入占比 71.4%，飞龙股份液冷泵小功率平台订单超 5 万台——液冷全核心零部件自主可控正在成为现实。

第三重：供电与散热边界融合。 800VDC 架构下，电源模块、PDB 配电单元、高速交换芯片自身发热也达到很高水平，部分电源组件同样需要液冷辅助散热——电源与温控两条产业链正在合并成一条。

4. 需求矩阵扩容：云厂商之外，太空算力入场​

Rubin 的客户矩阵已从传统云厂商扩展至三个层次：

• 全球云厂商：谷歌云、Azure、甲骨文云、CoreWeave；
• AI 科技巨头：马斯克公开披露 2027 年 8GW 超大规模 IDC 建设规划；SpaceX 将 Vera Rubin 架构定义为"最优 AI 计算架构"，计划地面与太空双向部署，支撑 "Starmind" 卫星算力项目；
• 主权与边缘：远期 Rubin Ultra 及 2027 年后更高功耗机型单机柜有望冲击 600kW+。

普华永道预计全球数据中心累计投资到 2035 年将达 31.6 万亿美元。AI 基础设施建设的确定性，已经从"是否建设"变成"多快建设"。

5. 对采购方的启示​

• 机房规划前置：2027 年起采购 Rubin 级算力，液冷改造（单千瓦改造成本较高）或按全液冷标准新建，必须在预算周期一开始就纳入；
• 看 PUE 也看水温：45℃ 温水直冷允许更高进水温度，可利用自然冷源压低 PUE——选址时人工冷源依赖度成为新的评估维度；
• 供应商组合即风险对冲：HBM 与先进封装供应是当前核心瓶颈（详见本站 HBM4 竞速分析），供应链多元化比单点性能更重要。

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相关链接​

• NVIDIA Rubin 规格页
• NVIDIA Rubin Ultra 规格页
• NVIDIA Rubin CPX 规格页

参考资料​

• 英伟达官方博客：Rubin 全液冷架构解析
• 财联社：Rubin 全面量产，看好液冷二次侧放量（2026-09-04）
• 东方财富研报：Vera Rubin 开启量产周期，AI 算力硬件环节迎来量价齐升（2026-08-27）
• 雪球：Vera Rubin 量产交付落地，全液冷 800V 高压架构重构（2026-09-03）

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本文基于 2026 年 9 月初供应链调研、券商研报与英伟达官方披露整理。出货量与功耗数据为产业链预估口径，实际以英伟达及客户正式披露为准。