15 posts tagged with "Product Launch"

AMD 确认下一代移动端旗舰处理器 Ryzen AI Max 400 系列，代号 Gorgon Halo。这是继 Strix Halo 之后，AMD 在端侧 AI 算力赛道投下的又一枚重锤。然而，这次发布的时间点极其微妙——正值 DRAM 价格创下约15年新高之际，192GB 统一内存的豪华规格能否真正大规模供货，成为业界最大的悬念。

距离第一代 Maia 100 发布两年多之后，微软的第二代自研 AI 加速器 Maia 200 终于从传闻走向量产部署。这枚专为推理打造的芯片，正在改写 Azure 的成本结构。

从跳票到落地：Maia 200 的问世之路​

微软的自研芯片计划于 2023 年 11 月首次公开，与 Cobalt CPU 同期亮相。但 Maia 系列的推进并不顺利，据公开报道，设计变更与人员流失曾迫使时间表一再推迟，量产节点最终落到 2026 年。2026 年 1 月 26 日，微软正式发布 Maia 200，部署几乎随后展开，从首颗封装芯片到机柜上线的时间据称缩短至同类项目的一半以内。

这枚芯片的核心参数相当激进：台积电 3 纳米工艺，单颗集成超过 1400 亿晶体管；配备 216GB HBM3e 显存，带宽达 7TB/s，另有 272MB 片上 SRAM 与专用 DMA 引擎；在 750W 的 SoC 功耗包络内，提供超过 10 PetaFLOPS 的 FP4 算力与超过 5 PetaFLOPS 的 FP8 算力。微软称其 FP4 性能是亚马逊第三代 Trainium 的 3 倍，FP8 性能超过谷歌第七代 TPU，每美元性能较 Azure 现有最新硬件提升 30%。

标准以太网上的超大推理集群​

Maia 200 在系统层面有一个鲜明取舍：放弃私有互联协议，全面基于标准以太网构建两层 Scale-up 网络。每颗加速器提供 2.8TB/s 的双向专用带宽，单个托架内四颗芯片通过直连链路全互联，机架内与机架间则统一采用 Maia AI 传输协议，集群规模最大可扩展至 6144 颗加速器。

这套设计的商业逻辑很直白：推理是 Azure 每天承载的最大负载，而以太网生态的成熟度与成本优势远非私有协议可比。配合第二代闭环液冷换热单元和与 Azure 控制平面的原生集成，微软宣称这是其迄今部署过的效率最高的推理系统。

服务 GPT-5.2 与 Copilot，但不取代英伟达​

Maia 200 首批部署在爱荷华州德梅因附近的 US Central 区域，亚利桑那州菲尼克斯附近的 US West 3 区域紧随其后。它将承载 OpenAI 最新 GPT-5.2 系列模型的推理、Microsoft Foundry 与 Microsoft 365 Copilot 服务；微软超级智能团队也用它进行合成数据生成与强化学习，为下一代自研模型供料。与此同时，微软开放了 Maia SDK 预览，包含 Triton 编译器、PyTorch 支持与模拟器等工具。

值得注意的是，纳德拉明确表示微软将坚持"自研加外购"的双轨策略，继续向英伟达和 AMD 采购芯片。Maia 200 的定位是异构算力矩阵中针对推理优化的一环，而非全面替代。微软 2026 财年第一财季资本开支高达 349 亿美元，自研芯片每一分省下的成本，都直接体现在 Azure AI 的利润率上。

小结​

从 Maia 100 的试水到 Maia 200 的规模化部署，微软用两年多时间补上了超大规模云厂商自研芯片这块拼图。据公开报道，接替者 Maia 300 已在设计之中，时间线指向 2027 年。在谷歌 TPU 已开始对外销售、亚马逊 Trainium 加速扩张的背景下，Maia 系列的每美元性能优势，将决定 Azure 在 AI 推理时代的议价能力。

RTX Spark 笔记本的首发潮终于来了。微软与联想相继公布旗舰级 AI PC：一款把矛头直接对准 MacBook Pro，一款则用128GB 统一内存和1 PFLOP FP4 算力重新定义 Windows 阵营的端侧 AI 上限。这批产品背后，是一段长达三年的等待史。

在旧金山举行的微软 Windows AI 与 Surface 活动上，NVIDIA 一手开启 RTX Spark 笔记本预订，一手预览 DGX Station for Windows——从 1 PFLOP FP4 的笔记本到 20 PFLOPS FP4 的桌面工作站，AI 算力正在从数据中心一路铺到办公桌。

RTX Spark 笔记本正式开订​

在微软于旧金山举行的 Windows AI 与 Surface 活动上，NVIDIA 宣布 RTX Spark 笔记本正式开启预订，首批产品将于 10 月 16 日（周五）发货；紧凑型桌面产品则计划在 11 月跟进上市。

OEM 阵容覆盖了几乎所有主流 PC 品牌：Acer、ASUS、Dell、HP、Lenovo、Microsoft（Surface Laptop Ultra）、MSI、Gigabyte 全部在列。从发布即有如此完整的品牌背书来看，RTX Spark 显然不是一款演示性产品，而是要成长为一个完整的终端新品类。

Blackwell RTX + Grace CPU：数据中心架构下沉终端​

RTX Spark 的硬件方案可以概括为"把 Grace Blackwell 的思路压缩进 PC"：

• GPU：基于 Blackwell 架构的 RTX GPU，最高 6144 个 CUDA 核心；
• CPU：最多 20 核的 Grace CPU；
• 互联：CPU 与 GPU 之间提供 600 GB/s 高速链路；
• 算力：最高 1 PFLOP FP4；
• 内存：最高 128GB 统一内存，CPU 与 GPU 共享同一内存池；
• 软件：运行完整 CUDA 栈。

其中"统一内存 + 完整 CUDA 栈"是两个关键点：前者决定了本地能装下多大的模型，后者决定了云端训练的代码可以低成本迁移到本地调试，开发者不必为桌面场景另学一套工具链。

DGX Station for Windows 首次预览​

如果说 RTX Spark 面向个人开发者，那么同场预览的 DGX Station for Windows 则瞄准了更高一层的需求。它基于 GB300 Grace Blackwell Ultra Desktop Superchip，拥有 748GB 一致性内存，算力最高可达 20 PFLOPS FP4，目标是让用户在本地运行约 1 万亿参数的模型。

对 Linux 生态的兼容也给出了务实答案：Linux 工具链可以通过 WSL（Windows Subsystem for Linux）访问。DGX Station for Windows 将于 Q4 上市，由 ASUS、Dell、HP、Lenovo 四家推出。

Surface Laptop Ultra 与内存挤压隐忧​

作为活动的另一主角，Surface Laptop Ultra 已于 10 月 7 日开启预订，最高配备 128GB 统一内存——这个容量已经接近入门级推理服务器的水平。

但 DIGITIMES 提出了一个不容忽视的问题：AI PC 的内存供给正在被服务器需求挤压。在内存厂商的优先级排序中，服务器 DRAM 需求被放在首位，AI PC 依赖的 LPDDR5X 供给承压。在存储供应紧张的背景下，128GB 统一内存的 AI PC 能否稳定供货，本身就是一个变数。

从云端到桌面的算力分层​

把 NVIDIA 目前的桌面产品线摆在一起，可以清晰看到一条算力分层路线：

这条路线的逻辑是：云端负责大规模训练与生产推理，桌面负责原型验证、微调与敏感数据场景，笔记本负责日常开发与演示。当模型越做越大、数据合规要求越来越严，"把算力放在身边"的价值正在上升。

Windows CUDA 原生化与 WSL 的务实路线​

过去十几年，CUDA 的主战场在 Linux 服务器上，Windows 开发者在工具链上长期处于跟随位置。RTX Spark 与 DGX Station for Windows 意味着完整 CUDA 栈第一次以原生姿态大规模进入 Windows 桌面场景。

而 WSL 桥接 Linux 工具链的安排，则是一种典型的务实路线：既照顾 Windows 用户的使用习惯，又不要求现有 Linux 工作流推倒重来。对于在 Windows 环境中做模型开发和内部工具的企业开发者来说，迁移成本被明显降低；对 NVIDIA 而言，这等于把整个 CUDA 开发者生态延伸到了全球存量最大的桌面操作系统上。

小结​

RTX Spark 笔记本开订与 DGX Station for Windows 预览，标志着 NVIDIA 把 AI 算力的故事延伸到了最后一米：从数据中心，到桌面工作站，再到背包里的笔记本。1 PFLOP FP4 到 20 PFLOPS FP4 的分层算力、128GB 到 748GB 的统一内存、WSL 桥接的 Linux 工具链，共同构成了一条完整的桌面 AI 开发路径。剩下的悬念有两个：一是 LPDDR5X 供给紧张会不会卡住 AI PC 的出货节奏，二是 11 月的紧凑型桌面和 Q4 上市的 DGX Station 能否如期落地。

This article is based on NVIDIA official product pages, the March 2026 GTC architecture blog, and third-party benchmark data; performance figures are vendor architecture comparisons, and actual gains should be verified with your own tests.

NVIDIA has confirmed that Groq 3 LPX — the "seventh chip" of the Vera Rubin platform — has entered full mass production, manufactured at Samsung's Pyeongtaek campus. This is the first time the deal has landed in the form of production silicon since December 2025, when NVIDIA spent roughly $20 billion to obtain a non-exclusive IP license to Groq plus its core engineering team.

For the inference hardware landscape, this is a paradigm-level event: for the first time, NVIDIA has incorporated a "specialized inference architecture defined by someone else" into its own flagship platform — and not as an add-on sale, but as deep co-design.

1. The Groq 3 LPU Chip and the LPX Rack: Specs at a Glance​

Single Groq 3 LPU (4nm, Samsung foundry):

A single LPX rack (32 1U liquid-cooled trays, 8 LPUs per tray):

The 500 MB of SRAM per LPU may not look like much, but multiplied by 256 LPUs and stacked with 40 PB/s of aggregate bandwidth, it forms the physical foundation of "deterministic low-latency decoding" — the LPU's design philosophy is precisely to use compiler static scheduling of on-chip SRAM to completely eliminate memory-fetch stalls during the inference decoding phase, which is exactly the most typical bottleneck of GPU inference.

2. AFD: Attention and FFN Split Up, GPU and LPU Each Do Their Own Job​

LPX does not replace the GPU; instead, it forms a heterogeneous system with Vera Rubin NVL72, centered on AFD (Attention-FFN Disaggregation):

1. Rubin GPUs handle prefill and attention — building the KV cache over large contexts and executing attention layers, consuming HBM capacity and high throughput;
2. Groq 3 LPUs handle FFN / MoE expert-layer decoding — latency-sensitive and pattern-predictable, exactly the home turf of deterministic SRAM scheduling;
3. Intermediate activations are exchanged between the two engines token by token, orchestrated and routed by NVIDIA Dynamo: the GPU computes every attention layer, the LPU computes every feed-forward layer, jointly producing each output token.

The logic of this division of labor is clear: agentic AI applications can consume 15x the tokens of traditional AI applications, and the bottleneck shifts from "can it finish computing" to "can it keep emitting tokens at stable low latency." Let the big HBM container run attention, and let the deterministic SRAM engine run decode — each plays to its strengths.

3. Measured Results and Official Figures​

• Third-party benchmarks (Artificial Analysis): with Gemma 4 31B at a 100K token context, LPX output reaches roughly 3400 tokens/s — inter-token intervals below 1 millisecond, a qualitative leap in interactivity for long-context agentic scenarios
• Official architecture comparisons: with LPX added, Vera Rubin NVL72 achieves up to 35x higher throughput per megawatt on trillion-parameter models; up to 10x more revenue opportunity per watt in "high-value token" scenarios
• Launch customers: Nebius is the first to deploy LPX racks to expand its token capacity; CoreWeave already connects Vera Rubin racks in production with Spectrum-X Multiplane

It must be emphasized: the 35x/10x figures are architecture comparisons at specific high-interaction operating points, not universal conclusions. For training, high-throughput batch inference, and workloads that need CUDA ecosystem flexibility, the GPU remains the right answer; LPX's home turf is scenarios where "single-user interactive latency is the product" — agent loops, real-time coding assistants, long-context conversations.

4. Three Industry Signals​

1. Specialized inference chips get absorbed, not opposed. The old narrative of the LPU as a "GPU challenger" has become part of Vera Rubin. The endgame for inference hardware may not be one architecture winning, but the heterogeneous combination of "GPU + specialized decoding engines" becoming the standard. For other inference chip startups (Cerebras, Etched, etc.), this is both proof that the ceiling has risen and a warning: get integrated or find differentiation.

2. Samsung foundry lands a high-end AI order. Against the backdrop of TSMC's near-monopoly on AI main chips, Samsung 4nm taking on LPX mass production is highly significant — combined with Tesla's earlier AI6 2nm order, Samsung foundry has a shot at returning to full-year profitability in 2027.

3. Inference economics enters the "priced per MW" era. When vendors start telling their story with tokens/MW and revenue per watt, the core KPI of compute selection has completely shifted from peak compute (TFLOPS) to token output per unit of energy. This is consistent with the power-and-electricity cost model built into our TCO Calculator: the chip with the best-looking peak specs is not necessarily the chip with the lowest cost per token.

Summary​

Groq 3 LPX mass production marks the arrival of a heterogeneous era for inference hardware: "GPUs manage throughput, LPUs manage latency." For teams currently selecting inference clusters, the recommendation is to evaluate workloads separately: keep batch offline inference on GPUs, and separately calculate the unit cost of LPX-class solutions for interactive long-context agents. If in doubt, run the 3-year total cost of ownership of both architectures through the TCO Calculator before deciding.

(Performance data in this article comes from NVIDIA official architecture comparisons and Artificial Analysis third-party benchmarks; for actual deployments, please rely on your own testing.)

Just five days after Huawei officially announced the Ascend 960 at HUAWEI CONNECT on September 17, Alibaba unveiled its new unified training-and-inference AI chip, Zhenwu V900, at the Apsara Conference in Hangzhou on September 22 — which Alibaba calls "the most powerful Chinese self-developed AI chip in terms of compute performance to date." This article is compiled from Alibaba's official announcements and reports from Sina Tech, C114, Huanqiu.com, and other sources.

1. Single Chip: 3x M890, 216GB + 1200GB/s​

Three takeaways:

• Memory crosses into the 200GB+ tier: 216GB puts it in the same capacity class as the Ascend 960DT (288GB self-developed HBM) and NVIDIA Rubin (288GB HBM4), leveling the capacity threshold for long-context and very large MoE models;
• 1200GB/s chip-to-chip interconnect: laying the foundation for the supernode's "memory-semantics interconnect" — the chip-level prerequisite that pairs with ICN Switch;
• Precision coverage across all scenarios: officially described as "high-precision training, low-precision and ultra-low-precision inference across all scenarios," with native FP8/FP4 support aligned with the common spec of 2026's new cards.

The absolute single-chip compute figure has not been officially disclosed; this site records it using the official relative figure of "3x M890." See the Zhenwu M890 spec page for M890 details.

2. System Level: ICN Switch + Panjiu Supernode, a 500,000-Card Single Cluster​

V900's real selling point is not the single chip but system-level collaboration:

• ICN Switch self-developed interconnect chip: once connected, the supernode gains native memory semantics and unified memory addressing, with a thousand cards interconnected at full bandwidth — over a thousand V900s can "work together like a single super chip";
• Panjiu supernode server: integrates V900 (compute) + ICN Switch (interconnect) + Panmai intelligent NIC (network) + Zhenyue SSD controller (storage), a fully self-developed compute-storage-network stack;
• 500,000-card single cluster: combined with Alibaba Cloud's next-generation intelligent computing center network architecture, a single cluster can scale up to 500,000 cards.

This mirrors Huawei's "11 key chips" approach: the unit of competition has shifted from the single chip to whole-system delivery capability — Zhenwu handles compute, Yitian handles general-purpose computing, Panmai handles networking, Zhenyue handles storage, and ICN Switch handles interconnect.

3. Business and Roadmap​

• The Zhenwu family has served over 650+ enterprise customers (as of June 2026), spanning autonomous driving, finance, large models, embodied AI, energy, and manufacturing;
• Supernodes based on the M890 are already deployed at scale, running models with over 2 trillion parameters such as Qwen3.8 and Kimi K3; Alibaba Cloud will add new serving nodes in Q4 to expand supernode supply;
• Roadmap: V900 enters mass production and sales in 2027 Q1; Zhenwu J900 is planned for release in 2027 Q3;
• CPU synergy: Yitian 720 / 730 arrive in 2027 (the 730 is the first to adopt T-Head's fully self-developed CPU microarchitecture, with single-core SPECint2017/GHz up to 1.4x that of Yitian 710); the 2029 Yitian 750 will interconnect directly with Zhenwu AI chips via the ICN bus;
• Alibaba Group CEO Eddie Wu said T-Head's AI chip annual shipment volume will increase substantially.

4. Competitive Coordinates: Two Swords in One Week​

Viewing the two mid-September launches side by side, the landscape of "system-level competition" among domestic AI chips is now clear:

Huawei is taking the "supernode + open-source CANN ecosystem" route, while Alibaba is taking the "full cloud stack + open-source model ecosystem" route; both still trail in per-card specs, but what they deliver are procurable, operable ultra-large-scale clusters. The substitution logic against NVIDIA's CUDA ecosystem is shifting from "performance parity" to "supply certainty + system efficiency."

5. Summary​

• V900: 3x M890, 216GB, 1200GB/s chip-to-chip interconnect, native FP8/FP4, mass production in 2027 Q1;
• System: ICN Switch with thousand-card full bandwidth, Panjiu supernode with a fully self-developed compute-storage-network stack, 500,000-card single cluster;
• Cadence: J900 in 2027 Q3, Yitian 730 in 2027, Yitian 750 in 2029 — T-Head's first three-year generational roadmap;
• What to watch: actual mass production and Alibaba Cloud deployment scale in 2027 Q1, disclosure of V900's absolute compute, and the possibility of external supply of ICN Switch.

Further Reading​

• Zhenwu M890 spec page (this site)
• Ascend 960 Official Launch: FP4 Compute Doubled, World's First NPO Supernode
• Domestic Top Three in H2 2026: Localization Rate Breaks 40%, Heading Toward 60%

References​

• Huanqiu.com: T-Head launches new unified training-and-inference AI chip Zhenwu V900 (2026-09-22)
• Sina Tech / TechWeb: Alibaba T-Head launches new AI chip Zhenwu V900, mass production in the first quarter of 2027
• C114: Alibaba launches new AI chip Zhenwu V900, mass production in 2027 Q1

This article is compiled from Alibaba's official announcements and public reports. The absolute single-chip compute of V900 has not been officially disclosed; supernode and cluster scale figures are official claims, subject to actual future delivery.

2026 年 9 月 17 日，华为全联接大会（HC2026），华为常务董事、ICT 基础设施业务总裁汪涛正式发布昇腾 960。与 8 月数字中国峰会上的"路线图预告"不同，这次是完整的规格官宣——而且提前三个季度就绪。本文基于华为官网新闻稿及多方报道整理，逐项拆解 960 的规格、超节点与路线图含义。

1. 昇腾 960：双版本，训练先行​

昇腾 960 分为两个版本，节奏错开一个季度：

三个读数：

• 提前三个季度就绪：960DT 原计划 2027 年 Q4，现在 2027 Q1 就绪、Q2 上市——与 950DT"提前上线华为云"一脉相承，路线图可信度在持续兑现；
• 精度口径与英伟达对齐：FP8 / FP4 主口径（辅以自研 HiF8 / HiFP8），FP4 已是 2026 新卡的通用口径；
• 288GB 自研 HBM + 9.6TB/s：显存容量与带宽同步翻倍，对训练长上下文大模型是实打实的容量红利。

单卡规格详见昇腾 960 规格页；上一代昇腾 950DT 规格页。

2. 昇腾 960 超节点：全球首个 NPO 超节点​

这是本场发布真正的"重器"——昇腾 960 超节点是全球第一个采用 NPO（近封装光学）的超节点：

NPO 意味着什么：传统光模块挂在交换机面板上，信号要先出封装再转电—光；NPO 把光引擎挪到交换芯片封装近旁，大幅缩短 SerDes 距离、降低功耗与时延。华为的具体数字：

• 5500 个自研 Hi-ONE 光引擎（业界首个量产 NPO，单引擎 7.2T）；
• 替代 4.8 万颗 800G 光模块；
• 降低功耗 550kW 以上，同时支撑 2μs 级互联时延。

对比 8 月数字中国峰会的口径（Atlas 960 单超节点 15488 卡），官方最新口径为单超节点 4096 卡（1 个超集群可由多超节点组成）——以华为官网最新新闻稿为准。

⚠️ 华为还给出了"MFU 提升 2.75 倍""推理时延降低 70%"等收益数据，均出自华为马尔科夫实验室仿真，尚无独立第三方实测，阅读时注意口径。

3. 一年一代：970（2028）→ 980（2029）​

华为首次把"一年一代"从愿景变成官宣承诺：

支撑这一节奏的是华为提出的"韬定律"：算力规格每代翻倍，访存带宽、访存容量、互联带宽同步大幅提升。

生态侧的同场数据也值得记录：CANN 外部开发者占比首次超过 61%、月活开发者 5200 人；910C 超节点部署已超 1000 套。

4. 竞争坐标：单卡有代差，系统级对打​

把 960DT 放到 2027 年的棋盘上看：

• 对 NVIDIA Rubin（R200：288GB HBM4 / 50 PFLOPS FP4）：单卡 FP4 算力约为 R200 的 8%（4 vs 50 PFLOPS），单卡代差客观存在；但 4096 卡超节点 + NPO 互联是系统级竞争——用"可交付的超大集群"对打单卡性能；
• 对采购方：960 的价值主张是"在国产量产约束内拿到最大可用集群"。DeepSeek 拟采购 16 万颗 950DT 跑推理的订单已经证明：当供给与生态到位，头部实验室愿意主动选国产；
• 对国产链条：950→960 的显存翻倍直接拉动国产 HBM 迭代，这是整条链的胜负手。

5. 小结​

• 960DT：FP8 2P / FP4 4P、288GB HBM、9.6TB/s，2027 Q2 上市，提前三个季度；
• 960 超节点：全球首个 NPO 超节点，4096 卡 / 8 EFLOPS FP8 / 1PB HBM / RTT 2μs；
• 路线图：一年一代官宣至 2029，950、960 均提前兑现，规划可信度显著上升；
• 看什么：2027 Q2 实际交付节奏、国产 HBM 产能、CANN 生态的第三方模型覆盖度。

相关阅读​

• 昇腾 960 规格页（本站，含双版本与超节点完整参数）
• 国产三强 2026 H2：国产化率突破 40% 向 60% 迈进（已按 960 官宣更新）
• 2026 H2 AI 芯片路线图重大更新（已按 960 官宣更新）
• 昇腾 950 超节点 Q4 上市，中兴、新华三、曙光全线跟进

参考资料​

• 华为官网：发布全球首个采用 NPO 的超节点（昇腾 960 超节点）（2026-09-17）
• 电子工程专辑：国产 AI 芯片新突破！华为昇腾 960 芯片将提前发布
• 环球网：华为全联接大会 2026 主题演讲报道

本文基于华为官网新闻稿与公开报道整理。MFU、时延等收益数据为华为实验室仿真口径；2028 / 2029 产品仅为路线图官宣，规格以未来发布为准。

June 6, 2026 — COMPUTEX 2026 concluded yesterday in Taipei. Under the theme "AI Together," this year's event set records with 1,500+ exhibitors and 6,000 booths. The head-to-head battle between NVIDIA, Intel, and AMD in the AI PC space was the defining story of the show.

1. NVIDIA RTX Spark: June Launch at $1,399​

Less than a week after its COMPUTEX debut, the NVIDIA-MediaTek RTX Spark Superchip confirmed its commercial timeline:

Market Reaction: AMD, Intel, and Qualcomm shares fell following the announcement. Analysts believe RTX Spark will reshape the market across three fronts — Windows AI PCs, creator workstations, and edge inference nodes.

2. Intel 18A in Full Production: Clearwater Forest + Crescent Island​

Intel CEO Lip-Bu Tan delivered his first COMPUTEX keynote with two key updates:

Clearwater Forest (Xeon 6+)​

• 288 cores, Darkmont architecture
• First Intel 18A process node data center CPU
• Foveros Direct 3D packaging
• Now in full production

Crescent Island AI GPU​

• 480 GB LPDDR5x memory
• 350 W air-cooled PCIe form factor
• Native FP4 support, targeting agentic inference
• Shipping H2 2026

"As AI moves into the agentic era, the CPU returns to the center of modern AI infrastructure." — Lip-Bu Tan

3. AMD Ryzen AI 400 Series Now Shipping​

AMD showcased the Ryzen AI 400 series (Zen 5 + Zen 5C hybrid + XDNA2 NPU) at COMPUTEX:

• NPU performance: 60 TOPS, the highest in x86
• 7 consumer SKUs + commercial PRO series
• Multiple OEM models already available or launching soon
• Advancing AI 2026 summit set for July in San Francisco

4. Chinese Domestic Chips Gaining Momentum​

5. The AI PC Era: Three-Way Roadmap Comparison​

This Week in AI Compute (6/1 – 6/6)​

Sources: COMPUTEX Daily, Tencent News, Phoenix Technology, Xueqiu, The Silicon Review.

June 1-5, 2026, Taipei — Computex 2026 (Taipei International Information Technology Show) wrapped up successfully this week. With the theme "AI Together," industry giants including NVIDIA, Intel, AMD, and Qualcomm unveiled numerous AI compute products in rapid succession. Below, MirrorFrog brings you a roundup of the most noteworthy developments in the compute card space this week.

① NVIDIA DGX Station for Windows: A Desktop AI Supercomputer​

NVIDIA officially launched the DGX Station for Windows during its Computex 2026 keynote, calling it "the world's most powerful desktop AI supercomputer."

Core Specifications​

Significance: DGX Station compresses AI compute power (20 PFLOPS FP4) that previously required datacenter-class clusters into a single desktop workstation. 748GB of unified memory means developers can run models with hundreds of billions or even trillions of parameters locally, without cloud dependency.

② Intel Crescent Island: Inference-Specialized AI GPU​

At Computex, Intel disclosed detailed specifications for its next-generation datacenter AI inference GPU, Crescent Island.

Significance: Crescent Island represents Intel's key strategic move in the AI inference market. 480GB of massive LPDDR5x memory (non-HBM) means significantly lower cost compared to NVIDIA H200/B200 and other competing products, targeting enterprise inference deployment scenarios.

③ Intel Xeon 6+ (Clearwater Forest): First Intel 18A Datacenter CPU​

Intel also unveiled the new Xeon 6+ processor, codenamed Clearwater Forest, its first datacenter CPU built on the 18A process:

• 288 Darkmont architecture cores
• L2 288MB + L3 576MB cache
• 12-channel DDR5-8000 memory
• Foveros Direct 3D advanced packaging
• AI Agent Era: CPU returns to the center of infrastructure

④ NVIDIA RTX Spark Ecosystem Takes Shape​

This week, the RTX Spark super chip developed in collaboration between NVIDIA and MediaTek continued to generate buzz. Multiple OEMs showcased RTX Spark-based laptop and compact desktop prototypes:

• ASUS, Dell, HP, Lenovo, Microsoft Surface, MSI all confirmed as launch partners
• Equipped with 20-core Grace CPU + Blackwell GPU (6144 CUDA cores)
• AI compute 1 PFLOPS
• Retail availability Fall 2026

⑤ Intel × Foxconn AI Infrastructure Partnership​

Intel and Foxconn announced a joint AI infrastructure initiative, covering the complete chain from chip → server → rack-scale system, targeting the datacenter market opportunity driven by surging AI inference demand.

⑥ Domestic AI Chip Developments​

According to the IDC 2025 annual report, total AI accelerator card shipments in China reached approximately 4 million units, with domestic vendors shipping approximately 1.65 million units, capturing a market share exceeding 41%. Huawei's Ascend 950 series has entered mass production and delivery, while Cambricon's MLU690 has begun shipping to internet customers.

This Week's Compute Roundup​

Sources: NVIDIA GTC Taipei 2026 / Computex 2026 official announcements, Intel press releases, ifeng Tech, IT Home.

June 1, 2026, Taipei — During the Computex 2026 opening keynote, NVIDIA CEO Jensen Huang officially unveiled the RTX Spark super chip, marking NVIDIA's formal entry into the personal computer processor market dominated by Intel, AMD, Qualcomm, and Apple.

RTX Spark: The "Heart" of the Personal AI Computer​

RTX Spark was developed in collaboration between NVIDIA and MediaTek, featuring a heterogeneous package with a 20-core Grace CPU + Blackwell RTX GPU, equipped with 6144 CUDA cores. AI compute reaches 1 PFLOPS (one quadrillion floating-point operations per second), meaning personal computers now possess computing power comparable to a datacenter-class H100 GPU for the first time.

Jensen Huang's "Full-Stack AI" Strategy​

The launch of RTX Spark is a key step in NVIDIA's "full-stack AI" strategy. Jensen Huang stated during the keynote: "AI should not only run in the cloud. Everyone's computer should have the ability to run AI agents."

RTX Spark transforms NVIDIA from a datacenter GPU monopolist into a full competitor in the personal computing market. Following the announcement, shares of AMD, Intel, and Qualcomm fell accordingly.

Market Impact​

• Intel: Personal computer AI processor business faces direct threat
• AMD: Ryzen AI series must compete at the same level
• Qualcomm: Snapdragon X Elite's Copilot+ PC positioning challenged
• Apple: M-series chips are no longer the only high-performance AI PC option

Vera Rubin Platform Enters Full Mass Production​

During the same keynote, Jensen Huang also announced that the NVIDIA Vera Rubin platform has entered full mass production. Rubin R200 features a 6-chip CoWoS-L package (1× Vera CPU + 2× Rubin GPU die + I/O/HBM die), equipped with 288GB HBM4, 22 TB/s bandwidth, and 50 PFLOPS FP4 compute (sparse).

The Rubin NVL72 rack (72 Rubin GPUs + 36 Vera CPUs) will begin shipping in H2 2026.

Other Highlights from Computex 2026​

• AMD: Showcased the MI350 series (192GB HBM3e, 5 PFLOPS FP8 dense), officially launching in June
• Intel: Jaguar Shores publicly unveiled for the first time
• Qualcomm: AI 200 / 300 series inference card roadmap updated
• Domestic AI Chip Zone: Huawei, Cambricon, Moore Threads, and others showcased their latest products

Industry Significance​

The launch of RTX Spark means AI compute is no longer confined to datacenters. Individual developers, designers, and researchers will be able to run large model tasks locally that previously required cloud GPUs, potentially redefining the market landscape for personal AI computing.

The mass production of Vera Rubin further consolidates NVIDIA's absolute leadership in datacenter AI training. Together, both product lines form NVIDIA's full-stack AI computing landscape of "cloud training + personal inference."

This report is based on official NVIDIA announcements from Computex 2026 / GTC Taipei on June 1, 2026.