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AMD Instinct MI450 Series (CDNA 5 · 432GB HBM4 · Cornerstone of the Helios Rack)

Product Overview​

The AMD Instinct MI450 Series is AMD's fourth-generation Instinct data center GPU line for frontier AI and sovereign AI, built on the 5th Gen AMD CDNA architecture and officially unveiled at Advancing AI 2026 on July 23, 2026. The family comprises two parts: MI455X (flagship for large-scale AI training and inference, purpose-built for the Helios rack) and MI430X (for HPC and sovereign AI, with hardware FP64).

MI450 is the first Instinct accelerator built on TSMC 2nm. Official technical material confirms that the accelerated compute dies (XCDs) are fabricated on TSMC N2P, while the active interposer die (AID) and I/O die use TSMC N3P, integrated into a CoWoS-L advanced package in a 3.5D form factor. AMD's official CDNA architecture page describes this as an "advanced chiplet architecture that partitions compute, memory, cache, and I/O functions across specialized dies," and notes that compute dies are stacked and connected through 3D hybrid bonding for improved compute density.

On memory, the MI450 Series steps up from the MI350's 288GB HBM3e to 432GB HBM4. One important caveat: when AMD first introduced Helios at the 2025 OCP Summit, the stated bandwidth figure was 19.6 TB/s; after the formal launch at Advancing AI 2026, AMD's product page and CDNA architecture page updated the peak theoretical bandwidth for MI455X to 23.3 TB/s (12 HBM4 stacks). This card uses the latest official product page figure.

Interconnect is the second major differentiator. Each GPU EAM delivers up to 3.6 TB/s bi-directional scale-up bandwidth per GPU (36 bi-directional UALoE links ×2) and supports the open UALink / UALoE (UALink over Ethernet) standard. In the AMD Helios rackscale solution, 72 MI450 Series GPUs are connected through a single-hop UALoE fabric, giving the rack 260 TB/s of scale-up bandwidth, while scale-out uses Ethernet (UEC / Open ESUN) at 43 TB/s.

Commercially, the MI450 Series is the centerpiece of AMD's openness strategy. AMD has announced commitments from OpenAI (6 GW), Anthropic (up to 2 GW, with the first 1 GW starting in the first half of 2027), Oracle (50,000 units), and Meta, and says customer demand already exceeds its internal forecast for 2027.

Key Specifications​

ParameterValue
ArchitectureAMD CDNA 5 (5th Gen, Wave32 execution, 256 WGPs)
ProcessTSMC 2nm (compute chiplets XCD) + 3nm (I/O and cache chiplets)
Memory432 GB
Memory TypeHBM4 (12 stacks)
Memory Bandwidth23.3 TB/s
FP820.1 PFLOPS
FP440.3 PFLOPS
FP1610.1 PFLOPS
INT8Not disclosed
TDPNot disclosed
Interconnect3.6 TB/s bi-directional scale-up per GPU (UALoE, 36 bi-directional links ×2); 600 GB/s bi-directional UALink scale-out; 3 × 800 Gbps AMD AI-NIC
Release / ProductionReleased 2026-07-23; volume shipments in the second half of 2026

Bandwidth caveat: AMD used a 19.6 TB/s figure when first introducing Helios at the 2025 OCP Summit; after the Advancing AI 2026 launch, the official product page and CDNA architecture page updated this to 23.3 TB/s. This table uses the latter (MI455X official product page).

TDP: AMD's official specification page does not publish a per-card TDP for the MI450 Series.

FP16 caveat: matrix compute including structured sparsity; FP4 / FP8 are OCP MXFP peak figures.

Key Features​

CDNA 5 Architecture Upgrades​

  • Wave32 execution: the new Work Group Processor (WGP) architecture delivers higher throughput per clock, while Wave32 execution reduces synchronization overhead and improves SIMD utilization
  • Low-precision data types: native MXFP8 / MXFP6 / MXFP4 with block-scale 16/32 and fractional scaling, up to 4× the throughput of previous-gen Instinct GPUs
  • 4-bit Tensor LUT instructions: efficiently convert compressed 4-bit tensor values into FP4, FP6, or FP8 MXFP compute formats on the Vector ALU, performing dequantization and preprocessing immediately before matrix multiplication
  • E5M3 floating-point format: uses the unused sign bit to add an extra exponent bit, extending range and improving accuracy on real workloads

Memory and Cache Hierarchy​

  • 432GB HBM4 in 12 stacks, with a 192-channel HBM4 interface and 192 MB global L2 cache
  • Two fabric and cache dies (FCD) carry the HBM interface and L2 cache, enabling chiplet-level independent optimization of compute, memory, cache, and I/O
  • Refined page-replacement builds on prior generations, providing more proactive protection against memory-level faults detected in the field

Data Movement Efficiency​

  • Tensor Data Mover (TDM): direct asynchronous global LDS with no register staging
  • L2 multicast: one memory fetch serves multiple WGPs, eliminating redundant memory traffic
  • WGP clustering: multiple WGPs cooperate on matrix operations

Open Interconnect Ecosystem​

  • UALink / UALoE: in-rack, a single-hop multi-plane UALink over Ethernet fabric connects all 72 GPUs through 12 UALoE switches across 6 switch trays; loss of any link, cable, or switch triggers automatic rerouting
  • Open networking strategy: scale-out runs on industry-standard Ethernet with UEC technologies and the Open ESUN framework, requiring no proprietary fabric
  • AMD Fabric Manager: configures the UALoE scale-up network and manages Virtual Pods, with its agent embedded directly in switch silicon

Use Cases​

  • ✅ Frontier model training (trillion-parameter class) and large-scale inference
  • ✅ Helios rackscale reference design (72 GPUs, 2.9 EF FP4 / 1.4 EF FP8, 31 TB HBM4)
  • ✅ Sovereign AI and HPC scientific computing (MI430X, hardware FP64)
  • ✅ Hyperscale data centers (public deployment commitments from OpenAI / Anthropic / Oracle / Meta)
  • ❌ Retail single cards (AMD Helios is a reference design built by OEMs and ODMs)

Comparison​

Data Sources​