Skip to main content

Huawei Ascend 960DT

Product Overview​

The Ascend 960DT is the training and Decode variant of Huawei's sixth-generation Ascend AI silicon. It shares a microarchitecture generation with the Prefill-oriented 960PR, but its memory subsystem is deliberately skewed toward bandwidth. At HUAWEI CONNECT 2026 in Shanghai on September 17, 2026, rotating chairman Wang Tao announced that the 960 family had completed development ahead of schedule with overall performance doubled, and that the 960DT would be ready in Q1 2027 — three quarters earlier than the original roadmap.

The officially disclosed headline figures are 2 PFLOPS of FP8 compute, 4 PFLOPS of FP4 compute, 288 GB of memory capacity, 9.6 TB/s of memory bandwidth, and 2.2 TB/s of die-to-die interconnect. Against the preceding 950DT (1 PFLOPS FP8, 2 PFLOPS FP4, 144 GB, 4 TB/s, 2 TB/s interconnect), compute, capacity, bandwidth, and interconnect all double or better — with the 9.6 TB/s memory bandwidth representing a 2.4x gain over the 950 generation. Huawei calls this continuously doubling trajectory the Tau Scaling Law (τ-law).

The 960DT moves to an all-new SIMD/SIMT dual-programming-model microarchitecture with full downward coverage of FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, and HiF4 data formats. HiF8 and HiF4 are Huawei's own formats that account for both precision and dynamic range; the company claims a single one of them can express information that would otherwise require two standard floating-point formats. The practical effect is that Huawei's low-precision compute path no longer depends entirely on formats defined by NVIDIA.

At the system level, the 960DT is the compute tile of the Ascend 960 SuperPoD. Alongside it, Huawei introduced the first supernode in the industry to adopt NPO (Near-Packaged Optics) engines, built on Lingqu UnifiedBus plus the Hi-ONE optical engine. A single supernode scales to 4,096 accelerators and delivers 8 EFLOPS FP8 and 16 EFLOPS FP4 in a fully liquid-cooled, orthogonal-architecture design. The 960DT pairs with the air-cooled Atlas 860 SuperPoD (planned for Q2 2027), which can be deployed in conventional data halls without any liquid-cooling retrofit.

⚠️ Disclosure caveat: Huawei has not published the 960DT's process node, packaging, core count, or TDP. Official materials give only compute and memory figures from a roadmap slide. Third-party analysis suggests two compute chiplets alongside eight HBM stacks based on keynote photography, but that is inference rather than an official claim. Volume delivery comes as a supernode or cluster, never as a standalone card.

Key Specifications​

ParameterValue
ArchitectureSIMD/SIMT dual programming model (new-generation Ascend microarchitecture)
ProcessNot disclosed
Memory288 GB
Memory TypeNot disclosed
Memory Bandwidth9.6 TB/s
FP82 PFLOPS
FP44 PFLOPS
FP16Not disclosed
INT8Not disclosed
TDPNot disclosed
Interconnect2.2 TB/s (die-to-die)
Release / ProductionReady Q1 2027, on sale Q2 2027

📌 On undisclosed fields: process node, memory type (the specific HiBL or HiZQ designation), FP16 and INT8 compute, and TDP are all withheld by Huawei, so every one of them is marked "Not disclosed" above with no speculative fill. Third-party reporting describes the 288 GB / 9.6 TB/s configuration as "on the level of eight 12-layer HBM3E stacks" and speculates CXMT as a possible supplier, but neither is an official Huawei claim.

📌 Supported data formats: FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, HiF4 (officially listed as supported; no per-format compute figures given).

Key Features​

1. All Four Metrics Double​

MetricAscend 950DTAscend 960DTChange
FP8 compute1 PFLOPS2 PFLOPS2x
FP4 compute2 PFLOPS4 PFLOPS2x
Memory capacity144 GB288 GB2x
Memory bandwidth4 TB/s9.6 TB/s2.4x
Die-to-die interconnect2 TB/s2.2 TB/s1.1x

2. Bandwidth Tuned for the Decode Stage​

  • Decode (token-by-token generation) is bound by memory bandwidth rather than compute, because model weights must stream through the memory system for every single token
  • At 9.6 TB/s across 288 GB, a single card can sustain larger batch sizes and longer context windows
  • Paired with MXFP4 and MXFP8 block floating-point formats to further reduce the volume of weights and KV cache moved per step

3. Proprietary Low-Precision Formats: HiF8 and HiF4​

  • Huawei states that HiF8 and HiF4 account for precision and dynamic range together, letting a single format express information that would otherwise need two standard floating-point formats
  • Huawei's low-precision compute path no longer rests entirely on NVIDIA's FP8 and FP4 encodings
  • ⚠️ The accuracy claims cannot be independently verified by anyone outside Huawei

4. An NPO Optical SuperPoD​

  • The Ascend 960 SuperPoD is the first supernode in the industry to use NPO (Near-Packaged Optics) engines
  • The Hi-ONE optical engine delivers 7.2T per engine — the first NPO product with real mass-production readiness, the highest transmission capacity currently in the industry, and the only one with a built-in light source
  • The system uses an orthogonal architecture and full liquid cooling, with unified memory addressing over Lingqu, scaling to 4,096 cards
  • 5,500 Hi-ONE engines replace the 48,000 800G optical modules that would otherwise be required, cutting power draw by more than 550 kW
  • Mean time between failures doubles and system availability reaches 99.8%
  • Multiple supernodes interconnect over Lingqu or RoCE: up to 512,000 accelerators on a two-tier CLOS four-plane fabric, and up to 1 million with multi-track topologies

5. Ecosystem Status​

  • Over 1,000 Ascend supernodes have been delivered to more than 370 customers, and the Ascend 950 SuperPoD has entered large-scale commercial deployment
  • CANN is fully open source and has entered normalized open-community operation; third-party developers now account for 61% of the community, with monthly active developers exceeding 5,200
  • The accompanying OceanStor M900 cluster provides one-hop direct access to petabyte-scale KV cache over the Lingqu bus, extending usable KV cache from gigabytes to terabytes per NPU

Use Cases​

  • ✅ Training frontier models at the ten-trillion-parameter scale (4,096-card supernode with unified memory addressing)
  • ✅ High-concurrency Decode inference (where the 9.6 TB/s bandwidth is the core payoff)
  • ✅ Conventional data hall deployment (air-cooled Atlas 860 SuperPoD, no liquid-cooling retrofit needed)
  • ✅ Workloads that want a proprietary low-precision format stack (HiF8 and HiF4)
  • ❌ Standalone card procurement (sold as supernode or cluster)
  • ❌ Deployment within 2026 (the chip launches in 2027)

Comparison​

Data Sources​