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Meta MTIA 450 (Custom AI Accelerator · Generative AI Inference)

Product Overview​

Meta MTIA 450 is the member of Meta's custom MTIA family purpose-built for generative AI inference, announced on March 11, 2026 alongside MTIA 300 / 400 / 500, with mass production scheduled for early 2027.

Meta's framing of the MTIA 450 is direct — inference-first. Meta's own words: mainstream chips are typically built for the most demanding workload (large-scale GenAI pre-training) and then applied, often less cost-effectively, to other workloads like GenAI inference; MTIA takes the opposite approach, optimizing MTIA 450 and 500 first for GenAI inference, then using them for other workloads as needed, including ranking and recommendations training and inference, as well as GenAI training. This keeps MTIA well-tuned to anticipated growth in GenAI inference demand.

The MTIA 450's headline change is doubled memory bandwidth. Against the MTIA 400's 9.2 TB/s, the MTIA 450 reaches 18.4 TB/s. Meta describes this bandwidth as "much higher than that of existing leading commercial products," which media read as a comparison against NVIDIA's H100 / H200. The reasoning is physically grounded: during the decode stage of transformer inference the bottleneck is memory bandwidth, not raw FLOPs, and mainstream GPUs are architected to maximize FLOPS for large-scale pre-training, carrying a cost and power overhead Meta considers unnecessary for inference.

For low-precision compute, the MTIA 450 supports the MX4 format, which Meta says delivers 6× the MX4 FLOPS of FP16/BF16, using mixed low-precision computation that avoids the software overhead of data type conversion. Meta also notes hardware acceleration for FlashAttention and mixture-of-experts feed-forward network computation, along with custom low-precision data types co-designed for inference.

On architecture and deployment, the MTIA 450, 400, and 500 use the same chassis, rack, and network infrastructure — each new generation drops into the existing physical footprint for easy interchange. This modularity is what underpins MTIA's roughly six-month chip cadence, itself far faster than the industry's typical one-to-two year cycle.

Key Specifications​

ParameterValue
ArchitectureMTIA 450 (custom accelerator optimized for generative AI inference, evolved from the MTIA 400)
ProcessNot disclosed
Memory288 GB
Memory TypeNot disclosed
Memory Bandwidth18.4 TB/s
FP87 PFLOPS
FP421 PFLOPS
FP16Not disclosed
INT8Not disclosed
TDP1400 W
InterconnectScale-up domain of 72 chips @ 1.2 TB/s (unidirectional); scale-out 100 GB/s (unidirectional)
Release / ProductionReleased 2026-03-11; mass production in early 2027

Data format caveat: Meta's official table lists compute as FP8/MX8 7 PFLOPS, MX4 21 PFLOPS, and BF16 3.5 PFLOPS. The FP4 entry here corresponds to Meta's MX4 (block-scaled 4-bit format, not FP4); Meta did not publish an absolute FP16/BF16 compute figure for this part, so the FP16 entry is marked as not disclosed.

Unidirectional bandwidth: the scale-up and scale-out bandwidths in this table are unidirectional figures.

Process: Meta co-developed this chip with Broadcom (across chip design, advanced packaging, and networking), but no specific process node or packaging form has been officially published.

Key Features​

Bandwidth-First Inference Architecture​

  • HBM bandwidth doubled versus the MTIA 400 (9.2 TB/s → 18.4 TB/s), which Meta explicitly benchmarks against and claims surpasses NVIDIA H100 / H200
  • HBM capacity is 288 GB, identical to the MTIA 400 — bandwidth doubled while capacity stays flat, showing Meta steered resources squarely toward bandwidth rather than capacity
  • This tradeoff directly serves the decode stage: every generated token requires reading model weights from memory, and insufficient bandwidth leaves compute units idle

MX4 Mixed Low-Precision Compute​

  • Native MX4 support, which Meta says delivers 6× the FLOPS of FP16/BF16
  • Mixed low-precision computation avoids software-level data type conversion overhead
  • Narrower formats cut the compute required for inference while, Meta says, not significantly hurting model quality

Inference-Specific Hardware Acceleration​

  • FlashAttention hardware acceleration
  • Mixture-of-experts (MoE) feed-forward network compute acceleration
  • Custom low-precision data types co-designed for inference

Generational Comparison with the MTIA 400​

MetricMTIA 400MTIA 450Change
Workload focusGeneral (R&R and GenAI)GenAI inference firstNarrowed focus
FP8/MX8 compute6 PFLOPS7 PFLOPS+17%
MX4 compute12 PFLOPS21 PFLOPS1.75×
HBM bandwidth9.2 TB/s18.4 TB/s2×
HBM capacity288 GB288 GBFlat
TDP1,200 W1,400 W+17%
Scale-up domain72 chips72 chipsFlat
StatusLab testing completeEarly 2027 mass production—

Key insight: versus the MTIA 400, the MTIA 450 gains 1.75× the MX4 compute while doubling HBM bandwidth and adding only 17% more TDP. Judged on FLOPS alone the generation looks modest; the real increment is in data movement — fully consistent with Meta's position that decode is bandwidth-bound rather than FLOPs-bound.

Position in the Roadmap​

Meta says that from MTIA 300 to MTIA 500, HBM bandwidth increases 4.5× and compute FLOPs increase 25×. The MTIA 450 is the GenAI inference workhorse along that curve, while the higher-end MTIA 500 adds another 50% of HBM bandwidth and up to 80% more HBM capacity.

Use Cases​

  • ✅ Generative AI inference (Meta's primary focus, with other workloads supported as needed)
  • ✅ Large-scale decode-heavy serving (bandwidth-first design matches the bottleneck directly)
  • ✅ Mixture-of-experts (MoE) model serving (MoE FFN hardware acceleration)
  • ✅ Long-context inference (288GB capacity + 18.4 TB/s bandwidth)
  • ✅ Meta internal infrastructure (internal use only, not sold externally)
  • ❌ Large-scale GenAI pre-training (mainstream GPUs remain Meta's training workhorses)
  • ❌ Retail / third-party procurement

Comparison​

Data Sources​