Skip to main content

Groq LPU v2 (LPU Inference, 2024)

Overview

Groq LPU v2 (unofficial codename) is Groq's second-generation LPU inference chip, released 2024-Q3, TSMC 4nm process, 80GB SRAM memory (industry's largest SRAM capacity), 15 TB/s memory bandwidth (highest LPU bandwidth in the industry), 188 TOPS INT8 compute, TDP 200W. It is Groq's last independent LPU product before the NVIDIA acquisition, paired with GroqCloud LPU cloud service.

Generational evolution:

  • LPU v1 (2022): Samsung 14nm, 230MB SRAM, 80 TOPS INT8 — existing others/groq-lpu.md
  • LPU v2 (2024-Q3): TSMC 4nm, 80GB SRAM, 188 TOPS INT8 — this page
  • LPU v3 LPX (2026, post-NVIDIA acquisition): 256 chips/rack, 40 PB/s SRAM, 640 TB/s intra-domain — existing nvidia/groq-3-lpx.md

Core Specifications

ItemSpec
ArchitectureGroq LPU v2 (deterministic dataflow)
ProcessTSMC 4nm
Memory TypeSRAM (on-chip)
SRAM Capacity80 GB (industry's largest)
Memory Bandwidth15 TB/s (highest LPU bandwidth in industry)
INT8188 TOPS
BF1694 TFLOPS
FP1694 TFLOPS
TDP200 W (one of the industry's most efficient inference chips)
Form FactorPCIe Gen5 x16
InterconnectGroqLink (proprietary, NVLink-like)
GroqLink Bandwidth900 GB/s (4-card intra-domain)
Mass Production2024-Q3
Unit Price~$20,000-30,000

LPU Architecture Principles

DimensionTraditional GPUGroq LPU
Compute ParadigmAsync, parallel, out-of-orderSynchronous, dataflow, deterministic
Execution ModelCUDA cores + Tensor coresStreaming Architecture
LatencyHBM-bound (nanoseconds + queuing)Deterministic (no queuing, nanosecond)
ThroughputHigh (HBM-bound)Extremely high (SRAM zero-wait)
TTFT100-500ms (queued)< 5ms (no queue)
TPOT30-50ms5-10ms (10x advantage)
Best forLarge model trainingLarge model inference (real-time)

Deterministic Dataflow Advantages

Traditional GPU inference:
Input -> HBM queue -> Compute -> HBM output
Latency: ~100ms (HBM access + scheduling)

Groq LPU inference:
Input -> 80GB SRAM (weights pre-loaded) -> Compute -> Output
Latency: ~5ms (SRAM zero-wait)

Key characteristics:

  • Weights loaded once into 80GB SRAM
  • No HBM access needed during inference (SRAM only)
  • Synchronous execution (all chips same clock)
  • Predictable latency (no queue jitter)

SRAM Capacity Evolution

GenerationSRAMFits Models
LPU v1 (2022)230 MBLlama 2 7B
LPU v2 (2024)80 GBLlama 3 70B FP8 / Llama 2 70B FP16
LPU v3 LPX (2026)80 GB x 256 chipsTrillion-parameter

80GB SRAM revolution: First time a single chip can fit a 70B-parameter FP16 model (140GB slightly exceeds, needs FP8 70GB to fit), eliminating HBM access, reducing latency from 100ms to 5ms.

GroqCloud Service

ItemSpec
ServiceGroqCloud LPU Inference API
API CompatibilityOpenAI Chat Completions API 100% compatible
Model SupportLlama 3 70B, Mixtral 8x7B, Gemma 7B
LatencyTTFT < 5ms, TPOT 5-10ms
Pricing$0.27 / 1M tokens (Llama 3 70B)
CustomersAnthropic partial inference, Cursor IDE, Vercel, Whisper transcription
StatusPreserved post-NVIDIA acquisition (GroqCloud continues)

4-Card Intra-Domain 900 GB/s

DimensionSpec
Single-Card SRAM80GB
4-Card Intra-Domain320GB SRAM (unified addressing)
Interconnect Bandwidth900 GB/s
Fits ModelsLlama 3 405B FP8 (210GB)
Latency4-card TTFT < 10ms
Price~$100K (4-card server)

vs NVIDIA H100 (Inference)

MetricGroq LPU v2NVIDIA H100Advantage
TTFT< 5ms100-300msLPU 20-60x
TPOT5-10ms30-50msLPU 3-5x
TDP200W700WLPU 3.5x power savings
Memory80GB SRAM80GB HBM3LPU zero-wait
Batch ThroughputMediumHighH100 +50%
Price~$25K~$25-30KComparable
SoftwareGroqWare (small)CUDA (large)H100 mature
API CompatibilityOpenAI 100%-LPU killer feature

LPU killer feature: TTFT < 5ms is 20-60x H100, making it the best HW for real-time AI inference (chatbot, code completion, speech transcription).

Vendor Information

ItemDetails
CompanyGroq, Inc.
FounderJonathan Ross (former Google TPU architect)
Founded2016
HeadquartersMountain View, CA, USA
Funding$1B+ (Series C 2024-Q2 led by D1 Capital)
2024 Revenue~$50M
FabTSMC 4nm
GroqCloud CustomersAnthropic partial inference, Cursor, Vercel, Anthropic SDK

NVIDIA Acquisition

In 2026-Q1, NVIDIA announced a $20B acquisition of Groq (excluding GroqCloud), with the Groq team joining NVIDIA's Vera Rubin platform LPU division. LPU v3 LPX becomes a rack-scale LPU co-processor for NVIDIA's Rubin platform. GroqCloud continues independent operations (Jonathan Ross stays), serving existing OpenAI-compatible API customers.

LPU Use Cases

  • Real-time AI inference (chatbot, code completion)
  • Speech transcription (Whisper Large V3 real-time)
  • API services (OpenAI compatible)
  • Ultra-low latency trading (HFT AI inference)
  • Autonomous driving (real-time vision/object detection)
  • AI training (LPU inference only)
  • Large batch inference (GPU throughput higher)
  • Traditional deep learning (CNN training)

LPU v1 vs v2 vs v3 Comparison

MetricLPU v1 (2022)LPU v2 (2024-Q3)LPU v3 LPX (2026)
ProcessSamsung 14nmTSMC 4nmTSMC 3nm
SRAM230MB80GB80GB x 256 chips = 20TB
Bandwidth80 TB/s15 TB/s40 PB/s (256-chip intra-domain)
INT880 TOPS188 TOPS2.4 P TOPS (256 chip)
TDP200W200W4 kW (256 chip rack)
Intra-Domain4 chips4 chips256 chips / rack
CustomersGroqCloudGroqCloud + EnterpriseNVIDIA Vera Rubin
StatusEOL (2025)In production (2024-Q3)Roadmap (2026)