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MetaX XiYun C550

MetaX Integrated Circuit's iterative upgrade model based on XiYun C500, released in 2024, FP16 peak compute 22.4 TFLOPS, memory bandwidth ~1600–1800 GB/s, performance targeting international mainstream AI training cards.

Core Specifications​

SpecificationValue
ArchitectureXCORE 1.0 (XiYun architecture, C500 iteration)
Process7 nm (estimated)
TDP300 W (estimated)
Memory64 GB HBM2e (same as C500)
Memory Bandwidth~1600–1800 GB/s
FP32 Compute15 TFLOPS (same as C500, estimated)
FP16 / BF16 Compute22.4 TFLOPS
INT8 Compute44.8 TOPS (estimated)
InterfacePCIe 4.0 x16 (estimated)
InterconnectMetaXLink (estimated)
Release2024-06 (estimated)
PriceNot disclosed (estimated ¥45,000)

Technical Highlights​

  • C500 iterative upgrade: Improved FP16 compute to 22.4 TFLOPS based on C500
  • Ultra-high memory bandwidth: ~1600–1800 GB/s, close to A100 level
  • Multi-precision mixed compute: Supports FP32/FP16/BF16/INT8
  • MetaXLink interconnect: Supports multi-card expansion, building large-scale training clusters
  • MXMACA software stack: CUDA ecosystem compatible, reducing migration costs

Product Positioning​

XiYun C550 is MetaX's iterative upgrade model based on C500, FP16 compute improved by ~49% (15→22.4 TFLOPS), memory bandwidth also significantly improved. Targeting NVIDIA A100 40GB, focusing on AI training and inference scenarios.

Application Scenarios​

  • AI model training (CV, NLP, multimodal)
  • Large model pre-training and fine-tuning
  • Scientific computing and simulation
  • Data center AI computing infrastructure
  • Domestic A100 replacement scenarios

Comparison with C500​

MetricXiYun C500XiYun C550Improvement
FP16 Compute15 TFLOPS22.4 TFLOPS+49%
Memory Bandwidth~1200 GB/s~1600–1800 GB/s+33–50%
Release Time20232024Iteration
Price~¥38,900Not disclosed—

Reference Price​

ChannelPriceDescription
Official pricingNot disclosedReleased in 2024, estimated ¥40,000–50,000/card
Channel estimate≈ ¥45,000Estimated based on C500 pricing ratio

References​