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Orient Silicon DF1000

The world's first software-defined near-memory 3D AI chip, unveiled in Shanghai on July 13, 2026. Built on 14nm mature process with a fully domestic supply chain (design → fabrication → 3D advanced packaging → test, all in China), it uses DRAM-Logic wafer-level hybrid bonding to break through the memory wall, bandwidth wall, and power wall — with no HBM dependency and no need for EUV-class lithography.

Core Specifications​

SpecValue
ArchitectureSoftware-defined near-memory computing (software-defined architecture + 3D-stacked DRAM-Logic hybrid bonding)
Process14nm (mature node + 3D advanced packaging in lieu of leading-edge process)
BF16520 TFLOPS (official launch figure)
MemoryUndisclosed (3D-stacked DRAM; HBM not required)
Memory bandwidth6.4 TB/s (near-memory access bandwidth)
Interconnect900 GB/s (scale-up)
Precision supportBF16 headline figure; other precision peaks undisclosed
TDPUndisclosed
Launch2026-07-13 (Shanghai)
Cluster validation128-card cluster, fully functional stable operation
PriceUndisclosed

📌 Sourcing note (2026-09 cross-validation): BF16 520 TFLOPS / 6.4TB/s / 900GB/s / 14nm figures come from the July 13, 2026 launch coverage by CGTN, ZhiDongXi (Leiphone), Cailian Press, and Yicai (First Financial) — multiple independent sources in agreement, high confidence. Memory capacity and TDP were not disclosed; left unlisted per the no-estimates policy.

Highlights​

  • 3D hybrid bonding: DRAM-Logic wafer-level vertical stacking with sub-micron interconnect pitch, fundamentally bypassing HBM dependency
  • Software-defined architecture: spatial parallelism plus time-division multiplexing of hardware resources raises utilization and reduces reliance on leading-edge process nodes
  • Fully domestic supply chain: chip design, wafer fabrication, 3D packaging, and test all completed domestically
  • Full-stack product matrix: DF1000 accelerator card, TY64 supernode (33 PFLOPS BF16 per node), QY100 8-card server, and HS512 AI cluster

Positioning​

Orient Silicon (Shanghai Orient Computing Core Technology Co., Ltd.) was founded in May 2024, headquartered in Zhangjiang, Shanghai, by Dr. Wei Shaojun — former director of Tsinghua University's Institute of Microelectronics and chair of the IC Design branch of the China Semiconductor Industry Association. The company closed an A+ round in April 2026 at a post-money valuation of RMB 12.275 billion. The DF1000 represents the domestic "advanced packaging + architecture innovation" route as an alternative to advanced process nodes. Roadmap: DF2000 in Q4 2026 (2x performance), DF3000 in Q4 2027.

Use Cases​

  • Large-model training and inference (520 TFLOPS BF16, validated on a 128-card cluster)
  • AI data center builds (HS512 cluster solution)
  • Government/enterprise deployments with strict supply-chain sovereignty requirements
  • ❌ Workloads requiring mature out-of-the-box software ecosystems (self-developed stack, maturity to be observed)

References​